Dissertations / Theses: 'Integrated circuits Integrated circuit layout'

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Harter, Andrew Charles. "Three-dimensional integrated circuit layout." Thesis, University of Cambridge, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.335724.

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Paroski, Andrew John. "Deform a new approach for redistributing placements /." Diss., Online access via UMI:, 2006.

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3

Griffin, Glenn. "Intelligent circuit recognition for VLSI layout verification." Master's thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-04272010-020102/.

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Ahmed, Mohammad Abrar. "Early Layout Design Exploration in TSV-based 3D Integrated Circuits." PDXScholar, 2017. https://pdxscholar.library.pdx.edu/open_access_etds/3617.

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Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during the early layout design stage. The goal of this thesis is to meet the design challenges of 3D ICs by providing new capabilities to the existing floorplanning framework [87]. The additional capabilities included in the existing floorplanning tool is the co-placement of TSV islands with circuit blocks and performing non-deterministic assignment of signals to TSVs. We also replace the wirelength and number of TSVs in the floorplanning cost function with the total delay in the nets. The delay-aware cost function accounts for RC delay impact of TSVs on the delay of individual signal connection, and obviates the efforts required to balance the weight contributions of wirelength and TSVs in the wirelength-aware floorplanning. Our floorplanning tool results in 5% shorter wirelength and 21% lesser TSVs compared to recent approaches. The delay in the cost function improves total delay in the interconnects by 10% - 12% compared to wirelength-aware cost function. The influence of large coupling capacitance between TSVs on the delay, power and coupling noise in 3D interconnects also offers serious challenges to the performance of 3D-IC. Due to the degree of design complexity introduced by TSVs in 3D ICs, the importance of early stage evaluation and optimization of delay, power and signal integrity of 3D circuits cannot be ignored. The unique contribution of this work is to develop methods for accurate analysis of timing, power and coupling noise across multiple stacked device layers during the floorplanning stage. Incorporating the impact of TSV and the stacking of multiple device layers within floorplanning framework will help to achieve 3D layouts with superior performance. Therefore, we proposed an efficient TSV coupling noise model to evaluate the coupling noise in the 3D interconnects during floorplanning. The total coupling noise in 3D interconnects is included in the cost function to optimize positions of TSVs and blocks, as well as nets-to-TSVs assignment to obtain floorplans with minimized coupling noise. We also suggested diagonal TSV arrangement for larger TSV pitch and nonuniform pitch arrangement for reducing worst TSV-to-TSV coupling, thereby minimizing the coupling noise in the interconnects. This thesis also focuses on more realistic evaluation and optimization of delay and power in TSV based 3D integrated circuits considering the interconnect density on individual device layers. The floorplanning tool uses TSV locations and delay, non-uniform interconnect density across multiple stacked device layers to assess and optimize the buffer count, delay, and interconnect power dissipation in a design. It is shown that the impact of non-uniform interconnect density, across the stacked device layers, should not be ignored, as its contribution to the performance of the 3D interconnects is consequential. A wire capacitance-aware buffer insertion scheme is presented that determines the optimal distance between adjacent buffers on the individual device layers for nonuniform wire density between stacked device layers. The proposed approach also considers TSV location on a 3D wire to optimize the buffer insertion around TSVs. For 3D designs with uniform wire density across stacked device layers, we propose a TSV-aware buffer insertion approach that appropriately models the TSV RC delay impact on interconnect delay to determine the optimum interval between adjacent buffers for individual 3D nets. Moreover, our floorplanning tool help achieve 3D layouts with superior performance by incorporating the impact of nonuniform density on the delay, power and coupling noise in the interconnects during floorplanning.

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Chowdhury, M. Foysol. "An expert system for analogue integrated circuit layout design." Thesis, University of Essex, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.303493.

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Srinivasan, Gopikrishna. "Multiscale EM and circuit simulation using the Laguerre-FDTD scheme for package-aware integrated-circuit design." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24705.

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Thesis (Ph.D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.
Committee Chair: Prof. Madhavan Swaminathan; Committee Member: Prof. Andrew Peterson; Committee Member: Prof. Sungkyu Lim

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Hong, Seong-Kwan. "Performance driven analog layout compiler." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/15037.

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Jangkrajarng, Nuttorn. "Analog/RF VLSI layout generation : layout retargeting via symbolic template /." Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/6084.

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9

Kim, Kwanghyun. "An interactive design rule checker for integrated circuit layout." Thesis, Virginia Polytechnic Institute and State University, 1985. http://hdl.handle.net/10919/50034.

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An implementation of an interactive design rule checker is described in this thesis. Corner-based design rule checking algorithm is used for the implementation. Due to the locality of checking mechanism of the corner-based algorithm, it is suitable for hierarchical and interactive local design rule checking. It also allows the various design rules to be specified very easily. Interactive operations are devised so that the design rule checker can be invoked from inside the layout editor. All the information about the violation, such as position, type of violation, and symbol definition name are provided in an interactive manner. In order to give full freedom to the user to choose the scope of checking, three options, "Flattening", "Unflattening" and "User-defined window" are implemented in creating the database to be checked. The "User-defined window" option allows hierarchical design rule checking on a design which contains global rectangles. Using these three options, very efficient hierarchical checking can be performed.
Master of Science
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Zhang, Xibo. "RF integrated circuit design options : from technology to layout /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20ZHANG.

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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.
Includes bibliographical references (leaves 59-61). Also available in electronic version. Access restricted to campus users.

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Zhang, Lihong [Verfasser]. "Layout Synthesis of Analog Integrated Circuits / Lihong Zhang." Aachen : Shaker, 2003. http://d-nb.info/1179024044/34.

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Schneider, Jan [Verfasser]. "Transistor-Level Layout of Integrated Circuits / Jan Schneider." Bonn : Universitäts- und Landesbibliothek Bonn, 2014. http://d-nb.info/1238687121/34.

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Rutherford, William C. "Gallium arsenide integrated circuit modeling, layout and fabrication." Thesis, University of British Columbia, 1987. http://hdl.handle.net/2429/26733.

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The object of the work described in this thesis was to develop GaAs integrated circuit modeling techniques based on a modified version of SPICE 2, then layout, fabricate, model and test ion implanted GaAs MESFET integrated sample and hold circuits. A large signal GaAs MESFET model was used in SPICE to evaluate the relative performance of inverted common drain logic (ICDL) digital integrated circuits compared to other circuit configurations. The integrated sample and hold subsequently referred to as an integrated sampling amplifier block(ISAB), uses a MESFET switch with either one or two guard gates to suppress strobe feedthrough. Performance guidelines suggested by the project sponsor indicate an optimal switch sampling pulse width capability of 25 ps with 5 ps rise and fall time. Guard gates are included in the switch layout to evaluate pulse feedthrough minimization. The project sponsor suggested -20 dB pulse feedthrough isolation and minimum sampling switch off isolation of -20 dB at 10 GHz as project guidelines. Simulations indicate that a 0.5 µm gate length process approaches the suggested performance guidelines. A mask layout was designed and modeled including both selective implant and refractory self aligned gate processes. The refractory self aligned gate process plasma etched t-gate structure produces a sub 0.5 µm gate length.
Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate

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Liu, Le-Chin Eugene. "Global routing and pin assignment for multi-layer chip-level layout /." Thesis, Connect to this title online; UW restricted, 1997. http://hdl.handle.net/1773/5898.

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Diesing, Norbert Carleton University Dissertation Engineering Electrical. "ALE - a custom layout methodology for bipolar integrated circuits." Ottawa, 1987.

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Bhattacharya, Sambuddha. "Template-driven parasitic-aware optimization of analog/RF IC layouts /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6121.

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Subramanian, Shankar. "CAD oriented database for integrated circuit layouts." Thesis, Virginia Polytechnic Institute and State University, 1986. http://hdl.handle.net/10919/94475.

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Modern integrated circuit layouts are so complex that databases often have to deal with a million or more geometric objects. For circuit and layout designers to be able to cope with such complex circuits, we (tool designers) must provide more and more support in such areas as design rule checking, circuit extraction, compaction, and routing. To support these tools the database must provide fast geometric operations for region queries, neighbor finding, and location of empty space. Furthermore, in order to build practical interactive systems the database must also permit fast incremental modifications. This thesis describes the design of a database that satisfies the above requirements. The database, based on a data structure called corner stitching, consists of all data structure definitions and operations, the rule based system, hierarchical structures, database I/O, and interface for the CAD tool designer. The implementation techniques for a layout editor are also described. The most important feature of the database is that the complexity of key operations for neighbor finding, region queries, and location of empty space depend on local factors and are independent of overall layout size. The above mentioned features should make it possible to design tools that operate incrementally.
M.S.

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Wang, Jun. "Physical design with fabrication : friendly layout /." View the Table of Contents & Abstract, 2004. http://sunzi.lib.hku.hk/hkuto/record/B30575643.

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Liesenberg, H. K. E. "A layout module for a silicon compiler." Thesis, University of Newcastle Upon Tyne, 1985. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.353769.

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20

Gani, Sohail M. "A gate matrix approach to VLSI logic layout." Thesis, University of Essex, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.238380.

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21

Harimoto, Seiyu. "PC-ICICLE: an interactive color integrated circuit layout editor for personal computers." Thesis, Virginia Tech, 1987. http://hdl.handle.net/10919/45790.

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An interactive color graphics layout editor for VLSI has been implemented on the IBM PC. The software, PC-ICICLE, is written in Microsoft PASCAL and the 8086/88 Assembly Language under the DOS 2.0 environment. The basic hardware requirement is the standard configuration of the IBM PC with 256K bytes, and color graphics monitor and adapter. Without the need for any special hardware, PC-ICICLE makes layout editors more readily available to VLSI chip designers. PC-ICICLE has also been executed on the IBM PC-XT, IBM PC-AT, and Zenith's IBM compatible PC without any modifications.

Master of Science

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Mukherjee, Souvik. "Layout-level Circuit Sizing and Design-for-manufacturability Methods for Embedded RF Passive Circuits." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/16131.

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The emergence of multi-band communications standards, and the fast pace of the consumer electronics markets for wireless/cellular applications emphasize the need for fast design closure. In addition, there is a need for electronic product designers to collaborate with manufacturers, gain essential knowledge regarding the manufacturing facilities and the processes, and apply this knowledge during the design process. In this dissertation, efficient layout-level circuit sizing techniques, and methodologies for design-for-manufacturability have been investigated. For cost-effective fabrication of RF modules on emerging technologies, there is a clear need for design cycle time reduction of passive and active RF modules. This is important since new technologies lack extensive design libraries and layout-level electromagnetic (EM) optimization of RF circuits become the major bottleneck for reduced design time. In addition, the design of multi-band RF circuits requires precise control of design specifications that are partially satisfied due to manufacturing variations, resulting in yield loss. In this work, a broadband modeling and a layout-level sizing technique for embedded inductors/capacitors in multilayer substrate has been presented. The methodology employs artificial neural networks to develop a neuro-model for the embedded passives. Secondly, a layout-level sizing technique for RF passive circuits with quasi-lumped embedded inductors and capacitors has been demonstrated. The sizing technique is based on the circuit augmentation technique and a linear optimization framework. In addition, this dissertation presents a layout-level, multi-domain DFM methodology and yield optimization technique for RF circuits for SOP-based wireless applications. The proposed statistical analysis framework is based on layout segmentation, lumped element modeling, sensitivity analysis, and extraction of probability density functions using convolution methods. The statistical analysis takes into account the effect of thermo-mechanical stress and process variations that are incurred in batch fabrication. Yield enhancement and optimization methods based on joint probability functions and constraint-based convex programming has also been presented. The results in this work have been demonstrated to show good correlation with measurement data.

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Robinson, Jayne Helen. "Artifical intelligence applied to MMIC layout." Thesis, Queen's University Belfast, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.295424.

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Nickoloff, Jacob L. "Layout generation and its application." Online access for everyone, 2007. http://www.dissertations.wsu.edu/Thesis/Summer2007/J_Nickoloff_081407.pdf.

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Zhu, Yongdong. "Parasitic-aware design and layout for RF CMOS analogue integrated circuits." Thesis, University of Essex, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.442535.

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Wang, Jun, and 王雋. "Physical design with fabrication: friendly layout." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2004. http://hub.hku.hk/bib/B45015119.

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Phillips, Shawn A. "Automating layout of reconfigurable subsystems for systems-on-a-chip /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/5979.

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Buddi, Naveen. "Layout Synthesis for Datapath Designs." PDXScholar, 1996. https://pdxscholar.library.pdx.edu/open_access_etds/5240.

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As datapath chips such as microprocessors and digital signal processors become more complex, efficient CAD tools that preserve the regularity of datapath designs and result in small layout area are required. The standard-cell placement techniques ignore the regularity of datapath designs and hence give inefficient layouts. This has necessitated the development of new techniques for datapath module placement. We developed a layout synthesis tool DataPathLAYOUT, for the bit-slice datapath logic designed using standard-cell libraries. We developed fast and area efficient heuristics for placing the cells in a bit-slice such that the regularity of datapath circuits is preserved and the number of channels in which a control signal is routed is minimized. The placement heuristics proposed here are general and also applicable to regular logic like systolic arrays. In addition, we propose a novel window- based heuristic, applicable to datapath and non-datapath circuits, for global routing of multi-terminal nets. We compared the area and run-time efficiency of the DPLAYOUT with an existing standard-cell placement and routing tool. We achieved 98-99% improvement in placement time, 28-33% improvement in area and 8-80% in total time. We conducted some experiments and demonstrated that for standard-cell based datapath designs, bit-slice-based layout generation approach is superior to non-bit-slice-based layout generation approach both in terms of area and run-time. Finally, by providing interface to Verilog hardware description language, we developed a general tool which can be easily integrated with any highlevel synthesis system. This tool is critical in any Datapath Silicon Compiler, to generate mask geometries from the behavioral level input specifications written in a hardware description language.

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Sen, Padmanava. "Estimation and optimization of layout parasitics for silicon-based millimeter-wave integrated circuits." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/26585.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.
Committee Chair: Dr. Joy Laskar; Committee Member: Dr. Chang- Ho Lee; Committee Member: Dr. Federico Bonetto; Committee Member: Dr. John D. Cressler; Committee Member: Dr. John Papapolymerou; Committee Member: Dr. Linda S. Milor. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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He, Yingchun. "VLSI Implementation of a Run-time Configurable Computing Integrated Circuit - The Stallion Chip." Thesis, Virginia Tech, 1998. http://hdl.handle.net/10919/36845.

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Reconfigurable computing architectures are gaining popularity as a replacement for general-purpose architectures for many high performance embedded applications. These machines support parallel computation and direct the data from the producers of an intermediate result to the consumers over custom pathways. The Wormhole Run-time Reconfigurable (RTR) computing architecture is a concept developed at Virginia Tech to address the weaknesses of contemporary FPGAs for configurable computing. The Stallion chip is a full-custom configurable computing "FPGA"-like integrated circuit with a coarse grained nature. Based on the result of the first generation device, the Colt chip, the Stallion chip is a follow-up configurable computing chip. This thesis focuses on the VLSI layout implementation of the Stallion chip. Effort has been made to explain many facts and advantages of the Wormhole Configurable Computing Machine (CCM). Design techniques, strategies, circuit characterization, performance estimation, and ways to solve problems when using CAD layout design tools are illustrated.
Master of Science

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Bagchi, Tanuj. "An Efficient Hybrid Heuristic and Probabilistic Model for the Gate Matrix Layout Problem in VLSI Design." Thesis, University of North Texas, 1993. https://digital.library.unt.edu/ark:/67531/metadc500878/.

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In this thesis, the gate matrix layout problem in VLSI design is considered where the goal is to minimize the number of tracks required to layout a given circuit and a taxonomy of approaches to its solution is presented. An efficient hybrid heuristic is also proposed for this combinatorial optimization problem, which is based on the combination of probabilistic hill-climbing technique and greedy method. This heuristic is tested experimentally with respect to four existing algorithms. As test cases, five benchmark problems from the literature as well as randomly generated problem instances are considered. The experimental results show that the proposed hybrid algorithm, on the average, performs better than other heuristics in terms of the required computation time and/or the quality of solution. Due to the computation-intensive nature of the problem, an exact solution within reasonable time limits is impossible. So, it is difficult to judge the effectiveness of any heuristic in terms of the quality of solution (number of tracks required). A probabilistic model of the gate matrix layout problem that computes the expected number of tracks from the given input parameters, is useful to this respect. Such a probabilistic model is proposed in this thesis, and its performance is experimentally evaluated.

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Roberts, Rebecca Mimi Catherina. "Automated parameter extraction for Single Flux Quantum integrated circuits with LVS." Thesis, Stellenbosch : Stellenbosch University, 2015. http://hdl.handle.net/10019.1/96992.

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Thesis (MEng)--Stellenbosch University, 2015.
ENGLISH ABSTRACT: Thorough layout verification of superconductor integrated circuits goes beyond design rule checking and parameter value extraction. The former is used to verify adherence to process design rules, and the latter to determine the element values of components such as inductors and resistors and Josephson junction critical currents. Still, neither gives much warning against subtle layout errors that could result in unintended parasitic elements, or a circuit that does not reflect the original circuit topology. A specialized implementation for Cadence Virtuoso allows layout-versus-schematic verification, but it is limited both to commercial software and in terms of its usefulness. Parameter extraction software such as InductEx is used to extract the component element values of a circuit from its layout if the circuit topology is provided as a netlist, which is mostly created by the designer. However, the element values are extracted for the supplied topology, even if a layout mistake such as creating a connection to the wrong node or a mistake in the netlist results in a model mismatch. After a failed verification, further diagnosis is required to determine whether the error is indeed in the layout or in the input topology - prolonging the verification process significantly. Here we present a free-standing layout-versus-schematic verification toolkit for superconductive integrated circuits, and discuss its implementation after systematically considering the algorithms at its core. We demonstrate results of the layout-versus-schematic verification and how the layout-versus-schematic toolkit is used as a whole in conjunction with InductEx to perform automated parameter extraction for cell-level layout verification. The current version of this toolkit provides the user with three stand-alone tools that are best used in conjunction with InductEx: A GDSII file flattener, a layout-to-schematic netlist extractor (with the option of viewing a pictorial reconstruction of the netlist and schematic) and a netlist comparison tool by which the user can determine whether a layout agrees with an input schematic. We conclude that the netlist comparison and viewing tool provides a valuable method for expediting the layout verification process, making it more efficient and minimizing the chances of mistakes. In its current form the layout-to schematic tool is still limited in that it cannot yet fully support circuits with mutual coupling. Although many improvements can still be made to this toolkit, the implemented version of these tools can already provide great benefit to Rapid Single Flux quantum (RSFQ) cell designers.
AFRIKAANSE OPSOMMING: Deeglike uitleg verifikasie van supergeleier geïntegreerde stroombane strek verder as bloot die nasien van ontwerpreëls en die onttrekking van parameter waardes. Eersgenoemde word gebruik om vas te stel of daar voldoen word aan die proses se ontwerpreëls, en laasgenoemde om die waardes van komponente soos induktors en resistors en die kritiese strome van Josephson aansluitings te bepaal. Nogtans bied nie een van hulle veel waarskuwing teen subtiele uitlegfoute wat onbeplande parasitiese elemente kan veroorsaak nie, of teen ‘n stroombaan wat nie die oorspronklike stroombaan topologie weerspieël nie. ‘n Gespesialiseerde implementasie van Cadence Virtuoso maak LVS (layout-versus-schematic) verifikasie moontlik, maar dit is beperk tot kommersiële sagteware en ook beperk in terme van bruikbaarheid. Parameter onttrekking sagteware soos InductEx word gebruik om waardes van die komponent-elemente van ‘n stroombaan vanuit die uitleg te onttrek wanneeer die stroombaan topologie as ‘n netlist, wat meestal deur die ontwerper geskep is, voorsien word. Die elementwaardes word egter onttrek volgens die topologie wat verskaf is, al is daar uitlegfoute, soos byvoorbeeld wanneer ‘n koppeling met ‘n verkeerde node plaasvind, of wanneer daar netlist foute is wat modelteenstrydighede veroorsaak. Na ‘n mislukte verifikasie poging word verdere diagnostiese stappe gedoen om te bepaal of die fout in die uitleg lê, of in die spesifieke topologie wat verskaf is, wat natuurlik die verifikasieproses aansienlik verleng. Hier stel ons ‘n vrystaande LVS verifikasie sagteware-pakket vir supergeleier geïntegreerde stroombane bekend, en bespreek, deur middel van die algoritmes wat die kern daarvan uitmaak, die implementering van hierdie sagteware-toestel. Ons bied die resultate van die LVS verifikasie aan en wys hoe die LVS sagteware toestel as geheel saam met InductEx gebruik kan word om automatiese parameter uittrekking vir sel-vlak uitleg verifikasie te berwerkstellig. Die huidige weergawe van die pakket bied die verbruiker drie alleenstaande programme wat verkieslik saam met InductEx gebruik moet word: ‘n GDSII “file flattener”, ‘n uitleg-tot-schematiese diagram netlist ekstraktor (met die opsie om ‘n herkonstruktueerde beeld van netlist en skematiese diagram te besigtig) en ‘n netlist vergelyking toestel waarmee die verbruiker kan vasstel of ‘n uitleg met ‘n oorspronklike skematiese diagram ooreenstem. Ons lei af dat die netlist vergelyking toestel ‘n waardevolle metode bied om die uitleg verifikasie proses te bespoedig en vergemaklik en die kanse van foute te minimaliseer. In sy huidige vorm is die uitleg-tot-skematiese diagram toestel beperk omdat dit nog nie stroombane met koppeling kan steun nie.

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33

Hubscher, Pedro Inacio. "Avaliação de desempenho de partes de controle de circuitos integrados." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 1992. http://hdl.handle.net/10183/26548.

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Este trabalho objetiva o estudo da avaliação de desempenho de partes de controle de circuitos integrados, em relação ao consumo de área em silício e atraso de propagação de sinais. Para a implementação são adotados dois diferentes estilos de leiaute (PLA e gate matrix). Para ambos os casos foi utilizado um conjunto único de regras de projeto. A análise dos circuitos visando implementação com PLA 6 é feita com base em estimativas de área e atraso deste, sendo definidas as suas células básicas. Para gate matrix, é feita a síntese de leiaute com um gerador automático de leiaute para circuitos em lógica aleatória e o atraso é estimado por modelo simplificado. A avaliação elétrica para calcular o atraso dos sinais é baseada em modelos simplificados de timing, previamente estudados, que levam em conta elementos parasitas das redes de transistores. São analisadas partes de controle de sistemas reais e máquinas de estados finitos hipotéticas. O trabalho visa propor a melhor estratégia de implementação, através da previsão do desempenho dos circuitos, em função do tamanho e complexidade (em número de portas e sinais de interface) do circuito.
The subject of this work is the performance analysis of control parts of integrated circuits, as a function of silicon area and signals propagation delay. Two different layout styles are used for implementation (PLA and gate matrix). Both of them use the same design rules. The analysis of the circuits implemented with PLA is based on area and delay estimation, with the basic cells already defined. For gate matrix, the layout synthesis is made with an automatic layout generator for random logic circuits and the delay is estimated by simplified models. The electrical evaluation to compute the delay signal is based on simplified timing models, previously studied, taking into account parasitic elements of the transistor networks. Control parts of real systems and finite state machines are analysed. This work aims to select the best implementation strategy, based on performance estimation, as a function of the size and complexity (gates and interface signals) of the circuit.

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Robinson, David Lyle. "Automatic Synthesis of VLSI Layout for Analog Continuous-time Filters." PDXScholar, 1995. https://pdxscholar.library.pdx.edu/open_access_etds/4913.

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Automatic synthesis of digital VLSI layout has been available for many years. It has become a necessary part of the design industry as the window of time from conception to production shrinks with ever increasing competition. However, automatic synthesis of analog VLSI layout remains rare. With digital circuits, there is often room for signal drift. In a digital circuit, a signal can drift within a range before hitting the threshold which triggers a change in logic state. The effect of parasitic capacitances for the most part, hinders the timing margins of the signal, but not its functionality. The logic functionality is protected by the inherent noise immunity of digital circuits. With analog circuits, however, there is little room for drift. Parasitic influence directly affects signal integrity and the functionality of the circuit. The underlying problem automatic VLSI layout programs face is how to minimize this influence. This thesis describes a software tool that was written to show that the minimization of parasitic influence is possible in the case of automatic layout of continuous-time filters using transconductance-capacitor methods.

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Grover, Samir. "Solving layout compaction and wire-balancing problem using linear programming on the Monsoon multiprocessor." Thesis, Connect to online version, 1995. http://0-wwwlib.umi.com.mercury.concordia.ca/cr/concordia/fullcit?pMQ90885.

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Zampronho, Neto Fernando. "Analise, projeto e layout de uma topologia de circuito regulador de tensão para aplicação em microprocessadores." [s.n.], 2009. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259236.

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Orientadores: Jacobus Willibrordus Swart, Jader Alves de Lima Filho
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
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Resumo: Este trabalho tem como objetivo o estudo de uma arquitetura de regulador de tensão do tipo multi-fase para alimentação de microprocessadores, os quais demandam pequena variação em sua tensão, mesmo face aos seus agressivos transitórios de corrente. O estudo engloba a análise, que descreve as vantagens e desvantagens de topologias de reguladores chaveados, o projeto, a simulação, a fabricação e a caracterização experimental do regulador. Na etapa de projeto, uma nova abordagem no dimensionamento do filtro externo LC é apresentada, considerando-se seus respectivos elementos parasitas, a partir da introdução do parâmetro .fator de não idealidade., ou n, que é compreendido no intervalo [0, 1]. Quanto mais n se aproxima da unidade, menores serão os elementos parasitas do filtro, facilitando a escolha dos capacitores e indutores no mercado. Adicionalmente, é proposta uma técnica de projeto do compensador em freqüência, aplicada em topologias realimentadas por tensão. Esta consiste na soma de sua tensão de saída com a diferença de potencial entre dois de seus nós internos, que ocorre apenas durante o transitório de carga, reduzindo o tempo de resposta do regulador. Simulações mostraram uma queda de mais de 25% na ondulação da tensão de carga utilizando esta técnica, em comparação com a solução convencional. O processo, simulador e modelos utilizados neste trabalho são, respectivamente, o AMS H35, PSPICE e Bsim3v3. O layout do regulador foi feito via Mentor Graphics e possui área efetiva de 0,444mm2. A fabricação na foundry AMS foi viabilizada pelo programa multi-usuário da FAPESP. A caracterização experimental compara o tempo de resposta do regulador nas mesmas condições da etapa de simulação. Resultados experimentais indicaram uma redução de 96,1% na ondulação da tensão de carga durante seu transitório de corrente utilizando a técnica proposta, em comparação a solução convencional, validando a nova técnica de projeto do compensador em freqüência. O presente trabalho é concluído enfatizando-se os objetivos alcançados e principais resultados experimentais obtidos, dificuldades de projeto e limitações da arquitetura do regulador chaveado estudada
Abstract: This work aims to study the topology of multi-phase voltage regulators applied to microprocessors, where only tiny variations in the supply voltage are allowed, even when facing aggressive current transients. This study consists in the analysis, which describes the advantages and disadvantages of switched voltage regulator topologies, design, simulation, layout and experimental characterization of the proposed regulator. In the design phase, a new approach in sizing the external LC filter is herein described, considering their stray elements, through the introduction of the .non ideality. parameter, or n, which is valid within interval [0,1]. As more as n approaches unity, less parasitic elements the filter will have, easing the choice of the capacitors and inductors commercially available. In addition to this, a new technique applied to voltage feedback topologies is proposed, which consists in adding the output voltage of the frequency compensator to a voltage between two of its internal nodes. With such an approach, the response time of the regulator to load transients decreases. Simulation results show a reduction over 25% in the output voltage ripple using this new approach, when comparing to the traditional solution. The process, simulator and models used in this work are, respectively, AMS H35, PSPICE and Bsim 3v3. The layout of the regulator was edited through Mentor Graphics, and it has an effective area of 0.444mm2. The fabrication in foundry AMS was done by multi-user program of FAPESP. The experimental characterization compares the response time of the regulator in the same conditions of simulation phase. Experimental results indicated a 96,1% reduction in load voltage ripple during transient, when comparing the purposed technique with the traditional solution, validating the excellent performance of the regulator with the new design technique. This work is concluded by emphasizing the reached objectives and main experimental results reached, design difficulties and limitations of the switched-regulator architecture studied
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica

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Kim, Cheongbu. "One-dimensional compaction strategy for VLSI symbolic layout system." Ohio : Ohio University, 1988. http://www.ohiolink.edu/etd/view.cgi?ohiou1182804901.

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Athikulwongse, Krit. "Placement for fast and reliable through-silicon-via (TSV) based 3D-IC layouts." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45783.

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The objective of this research is to explore the feasibility of addressing the major performance and reliability problems or issues, such as wirelength, stress-induced carrier mobility variation, temperature, and quality trade-offs, found in three-dimensional integrated circuits (3D ICs) that use through-silicon vias (TSVs) at placement stage. Four main works that support this goal are included. In the first work, wirelength of TSV-based 3D ICs is the main focus. In the second work, stress-induced carrier mobility variation in TSV-based 3D ICs is examined. In the third work, temperature inside TSV-based 3D ICs is investigated. In the final work, the quality trade-offs of TSV-based 3D-IC designs are explored. In the first work, a force-directed, 3D, and gate-level placement algorithm that efficiently handles TSVs is developed. The experiments based on synthesized benchmarks indicate that the developed algorithm helps generate GDSII layouts of 3D-IC designs that are optimized in terms of wirelength. In addition, the impact of TSVs on other physical aspects of 3D-IC designs is also studied by analyzing the GDSII layouts. In the second work, the model for carrier mobility variation caused by TSV and STI stresses is developed as well as the timing analysis flow considering the stresses. The impact of TSV and STI stresses on carrier mobility variation and performance of 3D ICs is studied. Furthermore, a TSV-stress-driven, force-directed, and 3D placement algorithm is developed. It exploits carrier mobility variation, caused by stress around TSVs after fabrication, to improve the timing and area objectives during placement. In addition, the impact of keep-out zone (KOZ) around TSVs on stress, carrier mobility variation, area, wirelength, and performance of 3D ICs is studied. In the third work, two temperature-aware global placement algorithms are developed. They exploit die-to-die thermal coupling in 3D ICs to improve temperature during placement. In addition, a framework used to evaluate the results from temperature-aware global placements is developed. The main component of the framework is a GDSII-level thermal analysis that considers all structures inside a TSV-based 3D IC while computing temperature. The developed placers are compared with several state-of-the-art placers published in recent literature. The experimental results indicate that the developed algorithms help improve the temperature of 3D ICs effectively. In the final work, three block-level design styles for TSV-based die-to-wafer bonded 3D ICs are discussed. Several 3D-IC layouts in the three styles are manually designed. The main difference among these layouts is the position of TSVs. Finally, the area, wirelength, timing, power, temperature, and mechanical stress of all layouts are compared to explore the trade-offs of layout quality.

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Aluru, Gunasekhar. "Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System." Thesis, University of North Texas, 2016. https://digital.library.unt.edu/ark:/67531/metadc849770/.

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The design of VLSI electronic circuits can be achieved at many different abstraction levels starting from system behavior to the most detailed, physical layout level. As the number of transistors in VLSI circuits is increasing, the complexity of the design is also increasing, and it is now beyond human ability to manage. Hence CAD (Computer Aided design) or EDA (Electronic Design Automation) tools are involved in the design. EDA or CAD tools automate the design, verification and testing of these VLSI circuits. In today’s market, there are many EDA tools available. However, they are very expensive and require high-performance platforms. One of the key challenges today is to select appropriate CAD or EDA tools which are open-source for academic purposes. This thesis provides a detailed examination of an open-source EDA tool called Electric VLSI Design system. An excellent and efficient CAD tool useful for students and teachers to implement ideas by modifying the source code, Electric fulfills these requirements. This thesis' primary objective is to explain the Electric software features and architecture and to provide various digital and analog designs that are implemented by this software for educational purposes. Since the choice of an EDA tool is based on the efficiency and functions that it can provide, this thesis explains all the analysis and synthesis tools that electric provides and how efficient they are. Hence, this thesis is of benefit for students and teachers that choose Electric as their open-source EDA tool for educational purposes.

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Al-Mahmood, Saiyid Jami Islah Ahmad. "A distributed design rule checker for VLSI layouts." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-11012008-063423/.

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Teichmann, Jürgen. "Untersuchung allgemeiner Eigenschaften, Optimierung und integrierte Realisierung logischer Schaltungen mit hystereseförmiger Übertragungskennlinie." Doctoral thesis, Universitätsbibliothek Chemnitz, 2014. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-132705.

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Zur Verbesserung der Störsicherheit bei der digitalen Signalübertragung wird eine Hysterese in die Übertragungskennlinie des Gatters eingefügt. Der Einfluss der Höhe der beiden Schwellwerte auf die Anzahl der auftretenden Fehler wird mittels eines Rechnerprogrammes untersucht. Ein Zufallsgenerator erzeugt Signale in verschiedenen Höhen und Breiten, die sich den ungestörten Signalen überlagern. Es erfolgt eine Umsetzung einer integrierten Schaltung auf einem TTL Master. Die Schaltung wird mittels eines eigens entwickelten Netzwerkanalyseprgrammes berechnet. Messergebnisse werden mitgeteilt
To enhance the noise immunity of digital signal transmission, a hysteresis is introduced to the transfer characteristic of integrated digital circuit. The influence of height of the two threshold values to the number of occurring errors is examined by a computer program. A random number generator generates signals of different heights and widths, which are superimposed on the undisturbed signals. There is an implementation of an integrated circuit on a TTL master. The DC performane is calculated by means of a specially developed circuit analysis program. Measurement results are presented

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Moraes, Fernando Gehm. "Synthese topologique de macro-cellules en technologie cmos." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 1994. http://hdl.handle.net/10183/17853.

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Les problèmes majeurs de la génération automatique du dessin des masques des circuits intégrés sont la dépendance vis-à-vis des règles de dessin et le dimensionnement correct des transistors. Les méthodes traditionnelles, telles que l'utilisation de cellules pré-caractérisées, manquent de flexibilité, car les portes des bibliothèques (en nombre limité) sont dessinées et dimensionnées (independarnment de l'application) pour une technologie donnée. Les méthodes de synthèse automatique du dessin des masques ont pour but de surmonter ces problèmes. Les techniques les plus couramment utilisées sont le "gate-matrix" et le "linear-matrix". L'indépendance vis-à-vis des règles de dessin est obtenue en utilisant la technique de description symbolique (dessin sous une grille unitaire), et les dimensions des transistors sont définies par le concepteur ou par un outil de dimensionnement. Nous proposons une méthode et un prototype logiciel pour la synthèse automatique des masques, en utilisant le style "linear-matrix multi-bander". La description d'entree du générateur est un fichier format SPICE (au niveau transistor), ce qui permet d'avoir un nombre très élevé de cellules, en particulier les portes complexes (A01), et ainsi avoir une meilleure optimisation lors de la phase d'assignation technologique. Les macro-cellules générées doivent être assemblées afin de réaliser un circuit complet. Deux contraintes supplémentaires sont ainsi imposées au générateur: malléabilité de la forme et position des broches d'entrées/sorties sur la périphérie de la macro-cellule. Les macro-cellules sont assemblées en utilisant un environnement de conception industriel. Les contributions de ce mémoire de doctorat sont d'une part le développement d'un générateur de macro-cellules flexible ayant les caracteristiques d'indépendance aux règles de dessin et d'intégration dans un environnement de macro-cellules, et d'autre part l'étude detailée des paramètres qui déterminent la surface occupée, les performances électriques et la puissance dissipée des macro-cellules générées automatiquement.
The main problems of the automatic layout synthesis are the design rules dependence and the transistor sizing. The traditional layout synthesis methods, like standard-cells, are not flexible, since the cells in the libraries are designed and sized for a specific technology. In this way, the designer must change his library at each technology improvement. The automatic layout synthesis methods overcomes these problems (design rules dependence and transistor sizing). Examples of layout styles are gate-matrix and linear-matrix. The technology independence is achieved by symbolic description (layout under an unitary grid), and the transistor sizes are defined by the designer or by a sizing tool. From these two constraints, we develop an automatic layout synthesis tool, using a linear-matrix multi-row layout style. The input description for our tool is a Spice file. This descriptions allows to define a greater number of cells (mainly AOIs gates), resulting a technology mapping with less constraints. The generated macro-cells must be assembled in order to construct a complete circuit. Two additional constraints are then imposed to the generator : variable aspect ratio and placement of the inputs/outputs pins in the macro-cell border. The macro-cells are assembled by an industrial CAD environment. The main contributions of this thesis are the development of a macro-cell generator (with the characteristics of technology independence and easy integration in a macro-cell environment) and the analysis of the parameters playing a role in the area, delay and power consumption.

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Clarke, Peter John. "Electromigration in integrated circuit interconnects." Thesis, London South Bank University, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.357205.

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Senthinathan, Ramesh 1961. "ELECTRICAL CHARACTERISTICS OF INTEGRATED CIRCUIT PACKAGES." Thesis, The University of Arizona, 1987. http://hdl.handle.net/10150/276425.

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Gibson, David. "Statistical prediction of integrated circuit performance based on circuit design and test structure evaluation." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/15781.

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Singh, D. "Integrated circuit elements for short millimeter wavelengths." Thesis, Cardiff University, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.372354.

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Miller, Ira 1943. "A CUSTOM BIPOLAR MICROPROCESSOR SUPPORT INTEGRATED CIRCUIT." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/276648.

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Morrow, I. L. "Investigation of radiation from active integrated circuit antennas." Thesis, Cranfield University, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.320638.

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Gustard, N. C. "Optimizes switched-capacitor filter circuits for integrated circuit realization." Thesis, University of Essex, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.294667.

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Hu, Bo. "Model compiler driven device modeling and circuit simulation /." Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/6054.

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Dissertations / Theses on the topic 'Integrated circuits Integrated circuit layout'

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