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Journal articles on the topic 'Integrated circuits Integrated circuit layout'

Author: Grafiati

Published: 4 June 2021

Last updated: 2 February 2022

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1

Guang, Yang, Bin Yu, and Huang Hai. "Design of a High Performance CMOS Bandgap Voltage Reference." Advanced Materials Research 981 (July 2014): 90–93. http://dx.doi.org/10.4028/www.scientific.net/amr.981.90.

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Bandgap voltage reference, to provide a temperature and power supply insensitive output voltage, is a very important module in the analog integrated circuits and mixed-signal integrated circuits. In this paper, a high performance CMOS bandgap with low-power consumption has been designed. It can get the PTAT (Proportional to absolute temperature) current, and then get the reference voltage. Based on 0.35μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that , when the temperature changes from -40 to 80 °C, the proposed circuit’s reference voltage achieve to 1.2V, temperature coefficient is 3.09ppm/°C. Adopt a series of measures, like ESD protection circuit, in layout design. The ultimately design through the DRC and LVS verification, and the final layout size is 700μm * 560μm.

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ALARCÓN, EDUARD, GERARD VILLAR, and ALBERTO POVEDA. "CMOS INTEGRATED CIRCUIT CONTROLLERS FOR SWITCHING POWER CONVERTERS." Journal of Circuits, Systems and Computers 13, no. 04 (August 2004): 789–811. http://dx.doi.org/10.1142/s0218126604001714.

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Two case examples of high-speed CMOS microelectronic implementations of high-performance controllers for switching power converters are presented. The design and implementation of a current-programmed controller and a general-purpose feedforward one-cycle controller are described. The integrated circuit controllers attain high-performance by means of using current-mode analog signal processing, hence allowing high switching frequencies that extend the operation margin compared to previous designs. Global layout-extracted transistor-level simulation results for 0.8 μm and 0.35 μm standard CMOS technologies confirm both the correct operation of the circuits in terms of bandwidth as well as their functionality for the control of switching power converters. The circuits may be used either as standalone IC controllers or as controller circuits that are technology-compatible with on-chip switching power converters and on-chip loads for future powered systems-on-chip.

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3

Indrusiak, Leandro Soares, and Ricardo Augusto da Luz Reis. "3D integrated circuit layout visualization using VRML." Future Generation Computer Systems 17, no. 5 (March 2001): 503–11. http://dx.doi.org/10.1016/s0167-739x(00)00036-4.

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4

Banu, Viorel, Josep Montserrat, Mihaela Alexandru, Xavier Jordá, José Millan, and Philippe Godignon. "Monolithic Integration of Power MESFET for High Temperature SiC Integrated Circuits." Materials Science Forum 778-780 (February 2014): 891–94. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.891.

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This work provides experimental result on fabricated 4H-SiC lateral power MESFET intended to be used in further development of high temperature integrated circuits for power application. The power SiC MESFET device was developed using a planar technology on silicon carbide and P implant isolation technique. Its destination to monolithic integration demands a lateral layout connection topology. The use of quite high doped N type epitaxial layer (1017cm-3) typical for the integrated circuits raises difficulties to keep the leakage current of the Schottky gate in a decent range. Therefore, a hexagonal close loop gate in conjunction with three metal interconnection levels was adopted, thus obtaining a compact lateral MESFET device and avoiding any drain to source parasitic leakage path. Using the tungsten gate MESFETS, the first generation of monolithic integrated lateral power MESFET device was integrated on the same wafer with digital circuits and a voltage reference analog circuit able to operate up to 250C. The temperature range can be next improved by using higher barrier for the gate contact.

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Cho, Minji, Heechul Lee, and Doohyung Woo. "Nonuniformity-Immune Read-In Integrated Circuit for Infrared Sensor Testing Systems." Electronics 9, no. 10 (October 1, 2020): 1603. http://dx.doi.org/10.3390/electronics9101603.

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In this study, a novel IR projector driver that can minimize nonuniformity in electric circuits, using a dual-current-programming structure, is proposed to generate high-quality infrared (IR) scenes for accurate sensor evaluation. Unlike the conventional current-mode structure, the proposed system reduces pixel-to-pixel nonuniformity by assigning two roles (data sampling and current driving) to a single transistor. A prototype of the proposed circuit was designed and fabricated using the SK-Hynix 0.18 µm CMOS process, and its performance was analyzed using post-layout simulation data. It was verified that nonuniformity, which is defined as the standard deviation divided by the mean radiance, could be reduced from 21% to less than 0.1%.

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VAHEDI, HALEH, STEFANO GREGORI, and RADU MURESAN. "ON-CHIP POWER-EFFICIENT CURRENT FLATTENING CIRCUIT." Journal of Circuits, Systems and Computers 18, no. 03 (May 2009): 565–79. http://dx.doi.org/10.1142/s0218126609005332.

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This paper presents a control circuit which regulates the current consumption of integrated circuits using current injection and voltage scaling techniques. The control circuit can be integrated with smart cards as a countermeasure against power analysis attacks and electromagnetic emanation analysis attacks. We have designed the proposed circuit in 0.18 μm CMOS technology at 1.8 V power supply. The simulation results show that the circuit controls the current through the power supply pin of a model of a smart card microcontroller and attenuates the peak-to-peak current variations by 95%. The power dissipation overhead of the control circuit is less than 20% of the original power dissipation of the smart card microcontroller. Comparing the layout area of the proposed circuit with that of an ASIC 3-DES algorithm in the same technology shows that the control circuit only constitutes 4% of the cryptographic processor. The proposed circuit proves to be especially useful for smart cards and small portable devices, where power dissipation and chip area are critical.

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7

Jabri, Marwan A. "Building Rectangular Floorplans–A Graph Theoretical Approach." VLSI Design 1, no. 2 (January 1, 1994): 99–111. http://dx.doi.org/10.1155/1994/46871.

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Rectangular dualisation is a technique used to generate rectangular topologies for use in top-down floorplanning of integrated circuits. In order for this technique to be used in a floorplanning system, its input, the connectivity graph representing an integrated circuit has to fulfill a number of conditions. This paper presents an efficient algorithm that transforms an arbitrary connected graph, representing an integrated circuit, into another graph that is guaranteed to fulfill these conditions and to admit rectangular duals. Effectively, the algorithm solves the global routing problem by using three techniques: passthrough, wiring blocks and collapsed wiring blocks. Resulting floorplans may be passed to a chip assembler and detailed router package to complete the layout. This paper also introduces a novel technique to transform a tree of biconnected sub-graphs into a block neighbourhood graph that is a path.

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8

Le Gouguec, Thierry, Najib Mahdi, Stéphane Cadiou, Cédric Quendo, Erich Schlaffer, Walter Pessl, and Alain Lefevre. "Modeling up to 45 GHz of coupling between microvias and PCB cavities considering several boundary conditions." International Journal of Microwave and Wireless Technologies 8, no. 3 (February 19, 2016): 421–30. http://dx.doi.org/10.1017/s1759078716000192.

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The recent developments in electronic cards such as the network equipment are characterized by the miniaturization of the board size and the increasing complexity of the layout. Because of these requirements, multi-layered printed circuit boards are commonly used and vias connecting signal lines on different layers, or integrated circuit devices to power and ground planes, are frequently used and often essential. However, a via is not an ideal transmission line. Besides, it creates discontinuities at high frequencies leading to high insertion loss degradation of signal which limits the performances of integrated circuit and systems. In this paper, the impacts of coupling between via and parallel-plates cavity on the response of microwave integrated devices are highlighted in the first part. Then, to describe the intrinsic interaction between the via transition and parallel-plate modes, the notion of parallel-plates matrix impedances is presented and new boundary conditions like open or plated through holes shielded boundaries of the cavities are introduced. Then, using this physics-based model, an intuitive equivalent circuit has been developed. Finally, the proposed approach and the equivalent circuits were validated by using comparisons with electromagnetic simulations and measurements in different scenarios.

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9

Ul Alam, Arif, Nishatul Majid, and SK Aditya. "Layout Design of a 2-bit Binary Parallel Ripple Carry Adder Using CMOS NAND Gates with Microwind." Dhaka University Journal of Science 60, no. 1 (April 15, 2012): 103–8. http://dx.doi.org/10.3329/dujs.v60i1.10346.

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A good deal of ingenuity can be exercised and a vast amount of time wasted exploring layout topologies to minimize the size of a gate or other circuitry such as an adder or memory element in an integrated circuit. This paper represents a simple and compact layout design for two bit binary parallel ripple carry adder using only CMOS NAND gates with the help of Microwind as a tool for design and simulation. Construction of this adder for fabricating involves the design of 2-input, 3-input, 4-input NAND gates and CMOS NAND inverters. The performance parameters are analyzed from the simulation responses and characteristics curves of the proposed design. The optimization of the design towards single P+ or N+ diffusion, single +Vdd and single Vdd supply contributed to lesser area and improved functionality of the adder circuits performance.DOI: http://dx.doi.org/10.3329/dujs.v60i1.10346 Dhaka Univ. J. Sci. 60(1): 103-108 2012 (January)

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WEATHERFORD, TODD R. "RADIATION EFFECTS IN HIGH SPEED III-V INTEGRATED CIRCUITS." International Journal of High Speed Electronics and Systems 13, no. 01 (March 2003): 277–92. http://dx.doi.org/10.1142/s0129156403001612.

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The types of applications affected by radiation effects in III-V devices have significantly changed over the last four decades. For most applications III-V ICs have provided sufficient radiation hardness. Some expectations for hardened soft error applications did not materialize until much later. Years of research defined that not only material properties, but device structures, layout practices and circuit design influenced how III-V devices were susceptible to certain radiation effects. The highest performance III-V ICs due to their low power-speed energy products will provide challenges in ionizing radiation environments from sea level to space.

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SENTHILPARI, C., K. DIWAKAR, and AJAY KUMAR SINGH. "LOW POWER, LOW LATENCY, HIGH THROUGHPUT 16-BIT CSA ADDER USING NONCLOCKED PASS-TRANSISTOR LOGIC." Journal of Circuits, Systems and Computers 18, no. 03 (May 2009): 581–96. http://dx.doi.org/10.1142/s0218126609005277.

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As the CMOS technology continues to scale to achieve higher performance, power dissipation and robustness to leakage and, process variations are becoming major obstacles for circuit design in the nanoscale technologies. Due to increased density of transistors in integrated circuits and higher frequencies of operation, power consumption, propagation delay, PDP, and area is reaching the lower limits. We have designed 16-bit adder circuit by Carry-Select Adder (CSA) using different pass-transistor logic. The adder cells are designed by DSCH3 CAD tools and layout are generated by Microwind 3 VLSI CAD tools. Using CSA technique, the power dissipation, PDP, area, transistor count, are calculated from the layout cell of proposed 16-bit adder for Ultra Deep Submicron feature size of 120, 90, 70, and 50 nm. The UDSM signal parameters are calculated such as signal to noise ratio (SNR), energy per instruction (EPI), Latency, and throughput using layout parameter analysis of BSIM 4. The simulated results show that the CPL is dominant in terms of power dissipation, propagation delay, PDP, and area among the other pass gate logics. Our CPL circuit dominates in terms of EPI, SNR, throughput, and latency in signal parameters analysis. The proposed CPL adder circuit is compared with reported results and found that our CPL circuit gives better performance.

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12

Vacula, Patrik, Vlastimil Kotě, Adam Kubačák, Milan Lžíčař, Radek Zelený, Miroslav Husák, and Jiří Jakovenko. "Incremental Control Techniques for Layout Modification of Integrated Circuits." Advances in Science, Technology and Engineering Systems Journal 2, no. 3 (July 2017): 1196–201. http://dx.doi.org/10.25046/aj0203151.

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13

Zhang, L., U. Kleine, R. Raut, and Y. Jiang. "Aladin: A Layout Synthesys Tool for Analog Integrated Circuits." Analog Integrated Circuits and Signal Processing 46, no. 3 (March 2006): 215–30. http://dx.doi.org/10.1007/s10470-006-1271-z.

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14

Martins, Ricardo, Nuno Lourenco, and Nuno Horta. "LAYGEN II—Automatic Layout Generation of Analog Integrated Circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, no. 11 (November 2013): 1641–54. http://dx.doi.org/10.1109/tcad.2013.2269050.

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15

Rabaey, J. M., S. P. Pope, and R. W. Brodersen. "An Integrated Automated Layout Generation System for DSP Circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 4, no. 3 (July 1985): 285–96. http://dx.doi.org/10.1109/tcad.1985.1270124.

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Jhoja, Jaspreet, Zeqin Lu, James Pond, and Lukas Chrostowski. "Efficient layout-aware statistical analysis for photonic integrated circuits." Optics Express 28, no. 6 (March 2, 2020): 7799. http://dx.doi.org/10.1364/oe.381921.

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17

Myderrizi, Indrit, and Ali Zeki. "A Tunable Swing-Reduced Driver in 0.13-μm MTCMOS Technology." Journal of Circuits, Systems and Computers 26, no. 11 (April 17, 2017): 1750182. http://dx.doi.org/10.1142/s0218126617501821.

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With the increase in demand for high-speed and low-power integrated circuits as technology scales down, low-swing signaling circuit techniques are critical for providing high-speed low-power communications. However, existing low-swing circuits comprise complex designs, power issues (static and dynamic), output voltage swing restrictions or nonadjustable voltage swing levels, leading to lower operation speeds and even larger area footprints. In this paper, a tunable swing-reduced driver (SRD) circuit featuring the mentioned design challenges is presented. The SRD enables low-swing signals with fully controllable output voltage swing that is useful to reduce the power dissipation and delay in the signaling paths. Implemented in UMC 0.13-[Formula: see text][Formula: see text]m multi-threshold CMOS process, the SRD achieves 26 ps propagation delay at 200[Formula: see text]mV output swing for a pulse signal input at 1[Formula: see text]GHz. Post-layout simulations of the proposed SRD and a DAC application circuit, incorporating the SRD, operating at 1[Formula: see text]GHz, validate the design.

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18

Atallah, Mikhail J., and Susanne E. Hambrusch. "An assignment algorithm with applications to integrated circuit layout." Discrete Applied Mathematics 13, no. 1 (January 1986): 9–22. http://dx.doi.org/10.1016/0166-218x(86)90064-8.

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19

Alimisis, Vassilis, Christos Dimas, Georgios Pappas, and Paul P. Sotiriadis. "Analog Realization of Fractional-Order Skin-Electrode Model for Tetrapolar Bio-Impedance Measurements." Technologies 8, no. 4 (November 2, 2020): 61. http://dx.doi.org/10.3390/technologies8040061.

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This work compares two design methodologies, emulating both AgCl electrode and skin tissue Cole models for testing and verification of electrical bio-impedance circuits and systems. The models are based on fractional-order elements, are implemented with active components, and capture bio-impedance behaviors up to 10 kHz. Contrary to passive-elements realizations, both architectures using analog filters coupled with adjustable transconductors offer tunability of the fractional capacitors’ parameters. The main objective is to build a tunable active integrated circuitry block that is able to approximate the models’ behavior and can be utilized as a Subject Under Test (SUT) and electrode equivalent in bio-impedance measurement applications. A tetrapolar impedance setup, typical in bio-impedance measurements, is used to demonstrate the performance and accuracy of the presented architectures via Spectre Monte-Carlo simulation. Circuit and post-layout simulations are carried out in 90-nm CMOS process, using the Cadence IC suite.

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Filippov, Ivan, Nikolay Duchenko, and Yuri Gimpilevich. "Particularities of complex-functional monolithic integrated circuits post-layout simulation." ITM Web of Conferences 30 (2019): 01003. http://dx.doi.org/10.1051/itmconf/20193001003.

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This paper presents a silicon-based complex-functional monolithic microwave integrated circuits (MMICs) design methodology. Post-layout simulation stage particularities are discussed. Pre-tapeout functionality verification results of the C-band phase and amplitude control MMIC based on 0.18 μm SiGe BiCMOS technology are also presented.

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Weaver, D. J., J. R. A. Cleaver, L. Avery, and H. Ahmed. "Substrate dopant imaging for layout reconstruction of integrated-circuit layers." Microelectronic Engineering 61-62 (July 2002): 1063–67. http://dx.doi.org/10.1016/s0167-9317(02)00583-x.

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22

Tsai, Hui-Wen, and Ming-Dou Ker. "Layout Consideration and Circuit Solution to Prevent EOS Failure Induced by Latchup Test in a High-Voltage Integrated Circuits." IEEE Transactions on Device and Materials Reliability 14, no. 1 (March 2014): 493–98. http://dx.doi.org/10.1109/tdmr.2012.2206391.

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23

Musa, Wahab, Sri Wahyuni Dali, and Ade Irawaty Tolago. "Design of Digital Parity Generator Layout Using 0.7 micron Technology." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 5 (October 1, 2018): 3550. http://dx.doi.org/10.11591/ijece.v8i5.pp3550-3559.

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The proposed digital parity generator circuit is an integrated circuit functions to detect data errors at the transmitter end, and check it at the receiving end. In digital communications, the digital messages are transmitted in the form of 1’s and 0’s between two points. It is an error free if both are the same. The purpose of this research is to implement a design method of digital parity generator layout with 0.7 micron process technology ECPD07 from Tanner Tools. Layout design starts from making schematic circuit, test function and make a layout. Next, check the layout results in terms of design rules and verify the desired functionality gradually. The results show that the circuit has functioned well as an odd parity generator. The simulation results obtained with loads CL = 25 fF, tpLH = 2nS and tpHL = 1.46 nS indicate that tp = 1.73nS or operating frequency of 578 MHz. The integrated digital parity generator circuit using transmission gate has a size of 14758 um2 (78.5 um x188 um), consisting of 74 gates.<br /><br />

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24

Su, Rong Jun. "Environmental Risk Evaluation on Integrated Circuit Industry." Applied Mechanics and Materials 209-211 (October 2012): 1203–6. http://dx.doi.org/10.4028/www.scientific.net/amm.209-211.1203.

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In order to evaluate the environmental risk of integrated circuit industry, a new integrated circuit chip project was taken as an example to be investigated and analyzed. Its engineering features, process flow, risk identification, risk source intensity and measures to prevent risks were proposed. Risk identification shows that main poisonous and harmful chemicals(PHC) are corrosives and antioxidants, flammable gases and liquids and poisonous gases. Transportation, production and storage risk of PHC and potential accidental risk caused by external factors were proposed. Risk source analysis indicates that the probability of damaging and leaking accidents on facilities is 10-1 times/year. In the case of cylinders leakage, leakage rates of SiF4, Cl2 and ClF3 will be 17 g/s, 8 g/s and 8 g/s respectively. Evaporation rates of isopropyl alcohol, HF and HCl acids are 0.09 g/s. 0.38 g/s and 55 g/s respectively. Finally, Overall layout and construction safety measures, safety precautions on dangerous chemical storage and transportation, technology design and automatic control design, and emergency plan to prevent risk accident were also proponed. This work will be helpful for environmental impact assessment on similar industries.

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Hsiao, Pei-Yung, S. F. Steven Chen, Chia-Chun Tsai, and Wu-Shiung Feng. "A knowledge-based program for compacting mask layout of integrated circuits." Computer-Aided Design 23, no. 3 (April 1991): 223–31. http://dx.doi.org/10.1016/0010-4485(91)90092-b.

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Wu, Anquan, Bin Liang, Yaqing Chi, and Zhenyu Wu. "Investigation of Heavy-Ion Induced Single-Event Transient in 28 nm Bulk Inverter Chain." Symmetry 12, no. 4 (April 15, 2020): 624. http://dx.doi.org/10.3390/sym12040624.

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The reliability of integrated circuits under advanced process nodes is facing more severe challenges. Single-event transients (SET) are an important cause of soft errors in space applications. The SET caused by heavy ions in the 28 nm bulk silicon inverter chains was studied. A test chip with good symmetry layout design was fabricated based on the 28 nm process, and the chip was struck by using 5 kinds of heavy ions with different linear energy transfer (LET) values on heavy-ion accelerator. The research results show that in advanced technology, smaller sensitive volume makes SET cross-section measured at 28 nm smaller than 65 nm by an order of magnitude, the lower critical charge required to generate SET will increase the reliability threat of low-energy ions to the circuit, and high-energy ions are more likely to cause single-event multiple transient (SEMT), which cannot be ignored in practical circuits. The transients pulse width data can be used as a reference for SET modeling in complex circuits.

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Saif, Sherif M., Mohamed Dessouky, M. Watheq El-Kharashi, Hazem Abbas, and Salwa Nassar. "A Platform for Placement of Analog Integrated Circuits Using Satisfiability Modulo Theories." Journal of Circuits, Systems and Computers 25, no. 05 (February 25, 2016): 1650047. http://dx.doi.org/10.1142/s021812661650047x.

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Satisfiability modulo theories (SMT) is an area concerned with checking the satisfiability of logical formulas over one or more theories. SMT can be well tuned to solve several of the most intriguing problems in electronic design automation (EDA). Analog placers use physical constraints to automatically generate small sections of layout. The work presented in this paper shows that SMT solvers can be used for the automation of analog placement, given some physical constraints. We propose a tool that uses Microsoft Z3 SMT solver to find valid placement solutions for the given analog blocks. Accordingly, it generates multiple layouts that fulfill some given constraints and provides a variety of alternative layouts. The user has the option to choose one of the feasible solutions. The proposed system uses the quantifier-free linear real arithmetic (QFLRA), which makes the problem decidable. The proposed system is able to generate valid placement solutions for benchmarks. For benchmarks that have many constraints and few geometries, the proposed system achieves a speedup that is 10 times faster than other recently used approaches.

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Ho, Hong Fa. "Reading Process of Integrated Circuit Layout Debugging: Evidence from Eye Movements." Advanced Materials Research 787 (September 2013): 855–60. http://dx.doi.org/10.4028/www.scientific.net/amr.787.855.

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Finding bugs in CMOS Integrated Circuit (IC) layouts is a basic skill for IC design engineers and students alike. The reading process of finding bugs is the basis for learning and teaching in electronic engineering. In this pilot study, eye-movement data was used in analyzing the reading process and nature of five participants (N=5) finding bugs in CMOS layouts. Data analysis of eye movements was based on nine types of ROI (Region of Interest). The ANOVA analysis of eye movements was analyzed. The findings of experimental results included that there were significant differences among the number of fixations of nine types of ROIs. The findings suggest how learners could read the bugged IC layouts effectively and efficiently.

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TAKAHASHI, Yuichiro. "No. 6: On “Act Concerning the Circuit Layout of a Semiconductor Integrated Circuit (Maskwork Law)”." Journal of Information Processing and Management 46, no. 8 (2003): 509–17. http://dx.doi.org/10.1241/johokanri.46.509.

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Cheng, Feng, and Junfa Mao. "IFDR: An Efficient Iterative Optimization Algorithm for Standard Cell Placement." Active and Passive Electronic Components 27, no. 4 (2004): 189–95. http://dx.doi.org/10.1080/08827510310001648915.

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In the automatic placement of integrated circuits, the force directed relaxation (FDR) method [Goto, S. (1981). An efficient algorithm for the two-dimensional placement problem in electrical circuit layout.IEEE Trans. on Circuits and Systems,CAS-28(1), 12-18] is a good iterative optimization algorithm. In this article, an improved force directed relaxation (IFDR) method for standard cell placement is presented, which provides a more flexible and efficient cell location adjustment scheme and a more extensive searching scale for better iterative placement optimization than the FDR method. A new heuristic algorithm based on local optimization is combined with the IFDR method to improve the placement. Experiments on the Microelectronics Center of North Carolina (MCNC) standard cell benchmarks [http://www.cbl.ncsu.edu/pub/Benchmark_ dirs/Layout Synth92/] have been done, and the results show that total wire length is reduced up to 25% and by an average of 16% in comparison with that from the placement algorithm of TimberWolf7.0.

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Wang, Xiao, and Zelin Shi. "A New CDS Structure for High Density FPA with Low Power." VLSI Design 2015 (February 1, 2015): 1–7. http://dx.doi.org/10.1155/2015/767161.

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Being an essential part of infrared readout integrated circuit, correlated double sampling (CDS) circuits play important roles in both depressing reset noise and conditioning integration signals. To adapt applications for focal planes of large format and high density, a new structure of CDS circuit occupying small layout area is proposed, whose power dissipation has been optimized by using MOSFETs in operation of subthreshold region, which leads to 720 nW. Then the noise calculation model is established, based on which the noise analysis has been carried out by the approaches of transfer function and numerical simulations using SIMULINK and Verilog-A. The results are in good agreement, demonstrating the validity of the present noise calculation model. Thermal noise plays a dominant role in the long wave situation while 1/f noise is the majority in the medium wave situation. The total noise of long wave is smaller than medium wave, both of which increase with the integration capacitor and integration time increasing.

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Cha, Hyouk-Kyu. "A Highly-Integrated Low-Noise MICS Band Receiver RF Front-End IC with AC-Coupled Current Mirror Amplifier." Journal of Circuits, Systems and Computers 28, no. 01 (October 15, 2018): 1950010. http://dx.doi.org/10.1142/s0218126619500105.

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This work presents a low-noise, low-power receiver RF front-end integrated circuit (IC) for 402–405[Formula: see text]MHz medical implant communications service (MICS) band applications using 0.18-[Formula: see text]m CMOS process. The proposed front-end employs an AC-coupled current mirroring amplifier in between the low-noise current-reuse transconductor amplifier and a single-balanced IQ mixer for improved gain and noise performance in comparison to previous works. The designed front-end IC achieves a simulated performance of 36.5[Formula: see text]dB conversion gain, 1.85[Formula: see text]dB noise figure, and IIP3 of [Formula: see text][Formula: see text]dBm while consuming 440[Formula: see text][Formula: see text]W from 1-V voltage supply. The consumed core layout area, including I/Q LO generation and current bias circuits, is only 0.29[Formula: see text]mm2.

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Ahn, Wonkee, Dereje Agonafer, and Shlomo Novotny. "Methodology for an Integrated (Electrical/Mechanical) Design of PWBA." Journal of Electronic Packaging 126, no. 4 (December 1, 2004): 524–27. http://dx.doi.org/10.1115/1.1827268.

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This paper describes a general methodology of how electrical circuit design data are mapped into an intermediate analyzable representation that supports the information requirement of several thermomechanical analyses, including product optimization/idealization. This paper describes other issues encountered, such as how to integrate product data that spans more than one tool, how to modify and add analysis data necessary during analysis, and how to use data stored in the analysis module from different programing environments. The advantage this process offers is also described by considering a PWBA (Printed Wiring Board Assembly) design, such as layout and layup in an electrical design system.

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Bogaerts, Wim, Yufei Xing, and Umar Khan. "Layout-Aware Variability Analysis, Yield Prediction, and Optimization in Photonic Integrated Circuits." IEEE Journal of Selected Topics in Quantum Electronics 25, no. 5 (September 2019): 1–13. http://dx.doi.org/10.1109/jstqe.2019.2906271.

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Pedram, Massoud, Narasimha Bhat, and Ernest S. Kuh. "Combining Technology Mapping With Layout." VLSI Design 5, no. 2 (January 1, 1997): 111–24. http://dx.doi.org/10.1155/1997/73654.

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Due to the significant contribution of interconnect to the area and speed of today's circuits and the technological trend toward smaller and faster gates which will make the effects of interconnect even more substantial, interconnect optimization must be performed during all phases of the design. The premise of this paper is that by increasing the interaction between logic synthesis and physical design, circuits with smaller area and interconnection length, and improved performance and routability can be obtained compared to when the two processes are done separately. In particular, this paper describes an integrated approach to technology mapping and physical design which finds solutions in both domains of design representation simultaneously and interactively. The two processes are performed in lockstep: technology mapping takes advantage of detailed information about the interconnect delays and the layout cost of various optimization alternatives; placement itself is guided by the evolving logic structure and accurate path-based delay traces. Using these techniques, circuits with smaller area and higher performance have been synthesized.

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Comer, Donald T. "Zener Zap Anti-Fuse Trim in VLSI Circuits." VLSI Design 5, no. 1 (January 1, 1996): 89–100. http://dx.doi.org/10.1155/1996/23706.

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This paper presents an overview of Zener zap anti-fuse trim as used to achieve improved accuracy in precision integrated circuits. Because this technology spans design and manufacturing, elements of design, layout, processing, and testing are included. The mechanism is defined and typical applications are discussed. Layout considerations of anti-fuse devices are summarized and complex trim networks and multiplexed control methods are presented. Both bipolar and CMOS process implementations are considered. The paper also contains a bibliography which includes U.S. patents, which make up a large part of the technical documentation of this technology.

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Mototaka, Kuribayashi. "Automatic layout design method of wirings in integrated circuit using hierarchical algorithm." Computer Integrated Manufacturing Systems 10, no. 2 (May 1997): 171. http://dx.doi.org/10.1016/s0951-5240(97)84321-2.

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Lee, Min Su, and Hee Chul Lee. "Dummy Gate-Assisted n-MOSFET Layout for a Radiation-Tolerant Integrated Circuit." IEEE Transactions on Nuclear Science 60, no. 4 (August 2013): 3084–91. http://dx.doi.org/10.1109/tns.2013.2268390.

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Zhang, Lihong, Rabin Raut, Yingtao Jiang, Ulrich Kleine, and Yoohwan Kim. "A hybrid evolutionary analogue module placement algorithm for integrated circuit layout designs." International Journal of Circuit Theory and Applications 33, no. 6 (2005): 487–501. http://dx.doi.org/10.1002/cta.332.

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Wang, Jun Ping, Su Yang Qi, and Dan Xu. "A Study on CIF-to-BMP Format Transformation Algorithm." Advanced Materials Research 712-715 (June 2013): 2510–13. http://dx.doi.org/10.4028/www.scientific.net/amr.712-715.2510.

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In the prediction and improvement of integrated circuit yield, it needs to convert CIF file to BMP file in order to calculate the critical area accurately and optimize the subsequent layout, at the same time, the image format of layout is the foundation of random defects hot spot detection. Firstly, the structures of CIF file and BMP file are studied, and various commands of CIF are deeply analyzed. Secondly, we design the algorithm that is based on the primitives are converted into BMP according to the representation of four basic primitives (rectangle, polygon, circularity, line with width) in CIF layout. Finally, we realize the algorithm of the whole CIF files is converted into BMP files. It is simple, conversion accuracy is high, more importantly, laid the foundation for the improvement of integrated circuit yield, and use C++ language to realize the CIF files conversion software based on the algorithm.

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Zhang, Lihong, and Zheng Liu. "Directly performance-constrained template-based layout retargeting and optimization for analog integrated circuits." Integration 44, no. 1 (January 2011): 1–11. http://dx.doi.org/10.1016/j.vlsi.2010.09.003.

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42

Lu, Zeqin, Jaspreet Jhoja, Jackson Klein, Xu Wang, Amy Liu, Jonas Flueckiger, James Pond, and Lukas Chrostowski. "Performance prediction for silicon photonics integrated circuits with layout-dependent correlated manufacturing variability." Optics Express 25, no. 9 (April 19, 2017): 9712. http://dx.doi.org/10.1364/oe.25.009712.

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Song, Y., J. S. Cable, K. N. Vu, and A. A. Witteles. "The Dependence of Latch-Up Sensitivity on Layout Features in CMOS Integrated Circuits." IEEE Transactions on Nuclear Science 33, no. 6 (1986): 1493–98. http://dx.doi.org/10.1109/tns.1986.4334629.

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44

Shakir, Muhammad, Shuoben Hou, Raheleh Hedayati, Bengt Gunnar Malm, Mikael Östling, and Carl-Mikael Zetterling. "Towards Silicon Carbide VLSI Circuits for Extreme Environment Applications." Electronics 8, no. 5 (May 3, 2019): 496. http://dx.doi.org/10.3390/electronics8050496.

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A Process Design Kit (PDK) has been developed to realize complex integrated circuits in Silicon Carbide (SiC) bipolar low-power technology. The PDK development process included basic device modeling, and design of gate library and parameterized cells. A transistor–transistor logic (TTL)-based PDK gate library design will also be discussed with delay, power, noise margin, and fan-out as main design criterion to tolerate the threshold voltage shift, beta ( β ) and collector current ( I C ) variation of SiC devices as temperature increases. The PDK-based complex digital ICs design flow based on layout, physical verification, and in-house fabrication process will also be demonstrated. Both combinational and sequential circuits have been designed, such as a 720-device ALU and a 520-device 4 bit counter. All the integrated circuits and devices are fully characterized up to 500 °C. The inverter and a D-type flip-flop (DFF) are characterized as benchmark standard cells. The proposed work is a key step towards SiC-based very large-scale integrated (VLSI) circuits implementation for high-temperature applications.

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Neudeck, Philip G., David J. Spry, Michael J. Krasowski, Liangyu Chen, Lawrence C. Greer, Carl W. Chang, Dorothy Lukco, Glenn M. Beheim, and Norman F. Prokop. "Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2021, HiTEC (April 1, 2021): 000064–68. http://dx.doi.org/10.4071/2380-4491.2021.hitec.000064.

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Abstract At HiTEC 2018, NASA Glenn Research Center reported the first demonstration of yearlong 500 °C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021 submission updates on-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11 and near 3000 transistors/chip for Gen. 12 are made possible by reductions in minimum layout feature sizes (including resistor width shrinkage from 6 μm to 2 μm) coupled with enlarged die size (from 3 × 3 mm to 5 × 5 mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM) and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequent Gen. 12 fabrication run currently in progress.

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CHAN, PHILIP C. "DESIGN AUTOMATION FOR MULTICHIP MODULE — ISSUES AND STATUS." International Journal of High Speed Electronics and Systems 02, no. 04 (December 1991): 263–85. http://dx.doi.org/10.1142/s0129156491000132.

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In this paper we will review the current state of commercial electronic design automation (EDA) tools for the design of multichip modules. MCM can be classified in terms of its substrate technology. The choice of substrate technology has important implications for the selection of design automation tools. A PCB EDA system seems more appropriate for MCMs with stacked via substrate which closely resembles the through-hole printed circuit board (PCB). A chip layout system may be more appropriate for MCMs with low-cost thin-film silicon substrate which typically uses staircase vias. The cofired ceramic substrate MCM which evolved from the hybrid integrated circuit technology may use the specialized hybrid EDA software packages available for the designing of hybrid integrated circuits. Historically, printed circuit board and integrated circuit design automation software evolved separately. There exists a boundary between the printed circuit board and integrated circuit design automation tools in the physical design hierarchy. This boundary can be an important limitation for the repartitioning of the physical design hierarchy within the MCM. We shall discuss in detail the impact of MCM on various aspects of EDA. In the area of physical design, we must face the traditional placement and routing problem for any high speed design. Problems such as system clock skew and tight timing requirements must be considered. As one push clock frequency higher, one also must consider discontinuities due to vias and bends besides the classical transmission line effect due to long wires. Other traditional physical design problems such as ground and power plane generation, physical design verification and mask tooling must be revisited in the context of various MCM substrate technologies. The thermal aspects of MCM design are strongly influenced by the placement of chips on the MCM substrate. Thermal design is especially important for high density MCMs using the flip-chip mounting technology. Here, the heat must be dissipated through the back of the substrate via thermal pillars or bumps. We still need to deal with the traditional coupled transmission line problems. Due to the small cross section, high performance MCM substrate interconnects are resistive and the transmission lines they form are lossy. Noise is another main problem for MCM design. For high speed MCM with many CMOS buffers, the ground bouncing noise resulting from simultaneous switching of a large number of CMOS drivers must be controlled through proper substrate and package design. We will conclude the paper by comparing existing VLSI and PCB EDA tools for MCM design.

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YUAN, SHOUCAI, and YAMEI LIU. "DUAL THRESHOLD VOLTAGE DOMINO ADDER DESIGN WITH PASS TRANSISTOR LOGIC USING STANDBY SWITCH FOR REDUCING SUB-THRESHOLD LEAKAGE CURRENT." Journal of Circuits, Systems and Computers 23, no. 03 (March 2014): 1450043. http://dx.doi.org/10.1142/s0218126614500431.

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Standby switch can strongly turn off all the high threshold voltage transistors, which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce sub-threshold leakage current. Sub-threshold leakage currents are especially important in burst mode type integrated circuits where the system is in an idle mode in the majority of the time. The standby switch allows a domino system to enter and leave a low leakage standby mode within a single clock cycle. In addition, we combine domino dynamic logic with pass transistor XNOR and pass transistor NAND gates to achieve logic 1 output during its precharge phase without affecting circuits operation in its evaluation and standby phase. The required process for dual threshold voltage circuit configuration involves only one additional ion implant step to provide an extra threshold voltage. SPICE simulation for our proposed circuits is made using a 0.18 μm CMOS processes from TSMC, with 10 fF capacitive loads in all output nodes, and parameters for typical process corner at 25°C. Layout is designed, wafer is fabricate and measured. The measurement results of fabricated chips are listed and verify that our designed 8-bit carry look-ahead adders (CLAs) reduced power consumption and propagation delay time by more than 15% and around 20%, respectively, when compared with the prior work.

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Yesil, Abdullah. "Floating Memristor Employing Single MO-OTA with Hard-Switching Behavior." Journal of Circuits, Systems and Computers 28, no. 02 (November 12, 2018): 1950026. http://dx.doi.org/10.1142/s0218126619500269.

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In this paper, we presented Multi-Output Operational Transconductance Amplifier (MO-OTA)-based floating memristor emulator circuit. The designed memristor circuit has only one MO-OTA and one grounded capacitor which is attractive for an integrated circuit. It does not consist of any multiplication circuit block to obtain nonlinear behavior of memristor. It is difficult to obtain the hard-switching voltage–current relationship than the smooth-switching voltage–current relationship of memristor but we obtained hard-switching voltage–current characteristics using single floating memristor circuit. The complete memristor circuit is laid by using Cadence Environment using TSMC 0.18[Formula: see text][Formula: see text]m process parameters. The layout area of MO-OTA occupies an area of 34[Formula: see text][Formula: see text]m [Formula: see text] 14[Formula: see text][Formula: see text]m. Its post-layout simulation results are given to demonstrate the performance of the presented memristor emulator in different operating frequencies, process corner and radical temperature changes. All post-layout simulations agree well with theoretical analyses. As application examples, different connections such as serial, parallel and single of memristor emulator are investigated to test its connectivity.

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Jun, Shi. "Deep sub-micron ESD GGNMOS layout design and optimization." MATEC Web of Conferences 198 (2018): 04009. http://dx.doi.org/10.1051/matecconf/201819804009.

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In the field of integrated circuits, ESD (Electro Static Discharge) has always been a rather serious problem of reliability. Enhanced ESD tolerance of IC chips became a focus of research on IC failure protection design. The thesis is better to solve the multi-fingered non-uniform conduction of ESD devices under electrostatic pulse. Layout parameters DCGS (Drain-Contact to Gate Spacing), SCGS (Source-Contact to Gate Spacing) and BS (Substrate-source spacing) size in the paper can be used as reference for ESD GGNMOS (Gated Ground NMOS) layout design. Also this paper provides setting the DRC (Design Rule Check) command to check the distance between the N+ diffusion regions of different potentials so that ESD failure is prevented effectively. TLP (Transmission Line Pulse) current pulse signal is adopted to measure characteristics of the GGNMOS. The thesis descripts a ESD Optimal layout design from five aspects of introduction, Key elements of ESD circuits layout design, ESD layout optimization, a ESD GGNMOS layout instance and conclusion.

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Kwon, Jimin, Sanghoon Baek, Yongwoo Lee, Shizuo Tokito, and Sungjune Jung. "Layout-to-Bitmap Conversion and Design Rules for Inkjet-Printed Large-Scale Integrated Circuits." Langmuir 37, no. 36 (September 1, 2021): 10692–701. http://dx.doi.org/10.1021/acs.langmuir.1c01296.

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