Log in

Relevant bibliographies by topics / Integrated circuits Junction transistors / Journal articles

To see the other types of publications on this topic, follow the link: Integrated circuits Junction transistors.

Journal articles on the topic 'Integrated circuits Junction transistors'

Author: Grafiati

Published: 4 June 2021

Last updated: 7 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'Integrated circuits Junction transistors.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Holmes, Jim, A. Matthew Francis, Ian Getreu, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Journal of Microelectronics and Electronic Packaging 13, no. 4 (2016): 143–54. http://dx.doi.org/10.4071/imaps.527.

Full text

Abstract:

In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circu

APA, Harvard, Vancouver, ISO, and other styles

2

Dvornikov, O. V., V. A. Tchekhovski, V. L. Dziatlau, A. V. Kunts, and N. N. Prokopenko. "Low temperature multi-differential operational amplifier." Doklady BGUIR 19, no. 5 (2021): 52–60. http://dx.doi.org/10.35596/1729-7648-2021-19-5-52-60.

Full text

Abstract:

A multi-differential operational amplifier, called OAmp3, designed for operation at temperatures up to minus 197 °С and developed on bipolar transistors and junction field-effect transistors of the master slice array МН2ХА030, is considered in the article. The circuitry features of the OAmp3 allow, due to the use of various negative feedback circuits, to implement a set of functions necessary for signal processing on a single amplifier: amplification (or current – voltage conversion), filtering, shift of the constant output voltage level. The performed measurements of OAmp3, connected as instr

APA, Harvard, Vancouver, ISO, and other styles

3

Kazior, Thomas E. "Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 372, no. 2012 (2014): 20130105. http://dx.doi.org/10.1098/rsta.2013.0105.

Full text

Abstract:

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices

APA, Harvard, Vancouver, ISO, and other styles

4

Neudeck, Philip G., David J. Spry, Michael J. Krasowski, et al. "Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2021, HiTEC (2021): 000064–68. http://dx.doi.org/10.4071/2380-4491.2021.hitec.000064.

Full text

Abstract:

Abstract At HiTEC 2018, NASA Glenn Research Center reported the first demonstration of yearlong 500 °C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021 submission updates on-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11 and near 3000 transistors/chip for Gen

APA, Harvard, Vancouver, ISO, and other styles

5

Spry, David J., Philip G. Neudeck, Dorothy Lukco, et al. "Prolonged 500°C Operation of 100+ Transistor Silicon Carbide Integrated Circuits." Materials Science Forum 924 (June 2018): 949–52. http://dx.doi.org/10.4028/www.scientific.net/msf.924.949.

Full text

Abstract:

This report describes more than 5000 hours of successful 500 °C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 °C. After 100 hours of 500 °C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 °C testing. We also describe the observation of important differences in IC materials durability when subjected to

APA, Harvard, Vancouver, ISO, and other styles

6

Francis, A. Matthew, Jim Holmes, Nick Chiolino, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (2016): 000242–48. http://dx.doi.org/10.4071/2016-hitec-242.

Full text

Abstract:

Abstract In the last decade, significant effort has been expended towards the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field effect transistors and metal-oxide-semiconductor field effect transistors have been pursued and demonstrated. More recently1,2, advances in low-power complementary MOS devices have enabled the development of highly-integrated digital, analog and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) for extended periods (up to 100

APA, Harvard, Vancouver, ISO, and other styles

7

Fu, Xiao An, Amita Patil, Philip G. Neudeck, Glenn M. Beheim, Steven Garverick, and Mehran Mehregany. "6H-SiC Lateral JFETs for Analog Integrated Circuits." Materials Science Forum 600-603 (September 2008): 1099–102. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.1099.

Full text

Abstract:

This paper reports fabrication and electrical characterization of 6H-SiC n-channel, depletion-mode, junction-field-effect transistors (JFETs) for use in high-temperature analog integrated circuits for sensing and control in propulsion, power systems, and geothermal exploration. Electrical characteristics of the resulting JFET devices have been measured across the wafer as a function of temperature, from room temperature to 450oC. The results indicate that the JFETs are suitable for high-gain amplifiers in high-temperature sensor signal processing circuits.

APA, Harvard, Vancouver, ISO, and other styles

8

Neudeck, Philip G., David J. Spry, Michael J. Krasowski, et al. "Yearlong 500 °C Operational Demonstration of Up-scaled 4H-SiC JFET Integrated Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2018, HiTEC (2018): 000071–78. http://dx.doi.org/10.4071/2380-4491-2018-hiten-000071.

Full text

Abstract:

Abstract This work describes recent progress in the design, processing, and testing of significantly up-scaled 500 °C durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for over one year at 500 °C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fo

APA, Harvard, Vancouver, ISO, and other styles

9

Neudeck, Philip G., David J. Spry, Liang Yu Chen, et al. "Prolonged 500 °C Operation of 6H-SiC JFET Integrated Circuitry." Materials Science Forum 615-617 (March 2009): 929–32. http://dx.doi.org/10.4028/www.scientific.net/msf.615-617.929.

Full text

Abstract:

This paper updates the long-term 500 °C electrical testing results from 6H-SiC junction field effect transistors (JFETs) and small integrated circuits that were introduced at ICSCRM-2007. Two packaged JFETs have now been operated in excess of 7000 hours at 500 °C with less than 10% degradation in linear I-V characteristics. Several simple digital and analog demonstration integrated circuits successfully operated for 2000-6500 hours at 500 °C before failure.

APA, Harvard, Vancouver, ISO, and other styles

10

Neudeck, Philip G., David J. Spry, Michael J. Krasowski, et al. "Year-long 500°C Operational Demonstration of Up-scaled 4H-SiC JFET Integrated Circuits." Journal of Microelectronics and Electronic Packaging 15, no. 4 (2018): 163–70. http://dx.doi.org/10.4071/imaps.729648.

Full text

Abstract:

Abstract This work describes recent progress in the design, processing, and testing of significantly up-scaled complex 500°C–durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for more than 1 y at 500°C in an air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more

APA, Harvard, Vancouver, ISO, and other styles

11

Gorbachuk, N. I., N. A. Poklonski, Ya N. Marochkina, and S. V. Shpakovski. "Effect of Hole Extraction from the Base Region of a Silicon p–n–p Transistor on its Reactive Impedance." Devices and Methods of Measurements 10, no. 4 (2019): 322–30. http://dx.doi.org/10.21122/2220-9506-2019-10-4-322-330.

Full text

Abstract:

Transistor structures are the basic elements of integrated circuitry and are often used to create not only transistors themselves, but also diodes, resistors, and capacitors. Determining the mechanism of the occurrence of inductive type impedance in semiconductor structures is an urgent task, the solution of which will create the prerequisites for the development of solid-state analogs of inductors. The purpose of the work is to establish the effect of extraction of non-equilibrium charge carriers from the base region on the reactive impedance of a bipolar p–n–p transistor.Using impedance spec

APA, Harvard, Vancouver, ISO, and other styles

12

Kaneko, Mitsuaki, Ulrike Grossner, and Tsunenobu Kimoto. "SiC Vertical-Channel n- and p-JFETs Fully Fabricated by Ion Implantation." Materials Science Forum 963 (July 2019): 841–44. http://dx.doi.org/10.4028/www.scientific.net/msf.963.841.

Full text

Abstract:

Silicon carbide (SiC) n-and p-channel junction field effect transistors (JFETs) with vertical channels were fabricated by direct ion implantation into a high-purity semi-insulating 4H-SiC substrate in order to further develop the path towards complementary JFET integrated circuits for applications in harsh environments. Compared with the conventional structure (lateral channel), the proposed structure is suitable for integration and inherently has a high transconductance owing to the double-gate configuration. The threshold voltage (Vth) can be controlled by mask design, while Vth in the conve

APA, Harvard, Vancouver, ISO, and other styles

13

RAUT, RABIN, VIJAY DEVABHAKTUNI, and NILADRI ROY. "AN EFFICIENT SPICE-BASED TECHNIQUE FOR PERFORMANCE CHARACTERIZATION OF BJT MIXERS." Journal of Circuits, Systems and Computers 19, no. 06 (2010): 1333–44. http://dx.doi.org/10.1142/s0218126610006700.

Full text

Abstract:

In this paper, we present a fast and simple SPICE-based technique for the performance characterization of BJT mixers. First, exploiting fundamental concepts, an AC equivalent circuit of a radio-frequency bipolar junction transistor mixer is derived. Second, this equivalent circuit is used to estimate the conversion gain, noise-figure, and nonlinearity characteristics of the mixer. The proposed technique has been validated using simulations on integrated and discrete transistor based mixer circuits.

APA, Harvard, Vancouver, ISO, and other styles

14

Flament, O., J. L. Autran, P. Roche, et al. "Enhanced total dose damage in junction field effect transistors and related linear integrated circuits." IEEE Transactions on Nuclear Science 43, no. 6 (1996): 3060–67. http://dx.doi.org/10.1109/23.556905.

Full text

APA, Harvard, Vancouver, ISO, and other styles

15

Fu, Xiao An, Amita Patil, Te Hao Lee, Steven Garverick, and Mehran Mehregany. "Fabrication of SiC JFET-Based Monolithic Integrated Circuits." Materials Science Forum 645-648 (April 2010): 1115–18. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.1115.

Full text

Abstract:

We report fabrication of lateral, n-channel, depletion-mode, junction-field-effect-transistor (JFET) monolithic analog integrated circuits (ICs) in 6H-SiC. Ti/TaSi2/Pt forms the contact metalization, Ti/Pt the interconnect metal, and the SiO2/Si3N4/SiO2 interlayer dielectric. The threshold voltage and pinch off current indicate that the actual channel doping and thickness is close to the nominal values specified. The wafer yield for good circuits of a single-stage differential amplifier is 54% out of 46 copies.

APA, Harvard, Vancouver, ISO, and other styles

16

Li, Shuxia, N. Garry Tarr, and Winnie N. Ye. "JFET Integration Using a Foundry SOI Photonics Platform." Applied Sciences 9, no. 19 (2019): 3964. http://dx.doi.org/10.3390/app9193964.

Full text

Abstract:

We explore the monolithic integration of conventional electronics with SOI photonics using the commercial silicon photonics foundry technology offered by A*STAR’s Institute of Microelectronics (IME). This process offers optical waveguide modulators and photodetectors, but was not intended to support transistors. We present the implementation of junction field effect transistors (JFETs) integrated with optical waveguides and photodetectors. A simple SPICE model is developed for the JFETs based on the available ion implant parameters, and the geometry feature size allowed by the technology’s lay

APA, Harvard, Vancouver, ISO, and other styles

17

Tsou, B. P. C., Kan M. Chu, and D. L. Pulfrey. "Series resistance calculations for polysilicon tunnel junction emitter transistors." Canadian Journal of Physics 67, no. 4 (1989): 218–20. http://dx.doi.org/10.1139/p89-038.

Full text

Abstract:

Calculations are reported of the series resistance caused by the thin insulating layer which separates the polycrystalline and monocrystalline regions of the emitter in certain types of polysilicon emitter transistors. It is demonstrated that the series resistance depends on the shape of the potential barrier which characterizes the thin insulator. For a triangular barrier the series resistance may be low enough for the transistors to be acceptable for very large scale integrated circuit applications.

APA, Harvard, Vancouver, ISO, and other styles

18

Spry, David J., Philip G. Neudeck, Liang-Yu Chen, et al. "Processing and Characterization of Thousand-Hour 500 °C Durable 4H-SiC JFET Integrated Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (2016): 000249–56. http://dx.doi.org/10.4071/2016-hitec-249.

Full text

Abstract:

Abstract This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 °C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over ~ 1-μm scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 °C operational testing. These results advance the technology

APA, Harvard, Vancouver, ISO, and other styles

19

AGARWAL, BIPUL, RAJASEKHAR PULLELA, UDDALAK BHATTACHARYA, et al. "ULTRAHIGH fmax AlInAs/GaInAs TRANSFERRED-SUBSTRATE HETEROJUNCTION BIPOLAR TRANSISTORS FOR INTEGRATED CIRCUITS APPLICATIONS." International Journal of High Speed Electronics and Systems 09, no. 02 (1998): 643–70. http://dx.doi.org/10.1142/s0129156498000270.

Full text

Abstract:

Transferred-substrate heterojunction bipolar transistors (HBTs) have demonstrated very high bandwidths and are potential candidates for very high speed integrated circuit (IC) applications. The transferred-substrate process permits fabrication of narrow and aligned emitter-base and collector-base junctions, reducing the collector-base capacitance and increasing the device f max . Unlike conventional double-mesa HBTs, transferred-substrate HBTs can be scaled to submicron dimensions with a consequent increase in bandwidth. This paper introduces the concept of transferred-substrate HBTs. Fabricat

APA, Harvard, Vancouver, ISO, and other styles

20

PANKRATOV, E. L. "LOCAL DOPING AND OPTIMAL ANNEALING OF A MESH MULTILAYER STRUCTURE TO DECREASE THE SPATIAL DIMENSIONS OF INTEGRATED p–n-JUNCTIONS." Nano 04, no. 05 (2009): 303–23. http://dx.doi.org/10.1142/s179329200900185x.

Full text

Abstract:

It has been recently shown that inhomogeneity of a multilayer structure and optimization of annealing time give us the possibility to decrease the depth of p–n-junctions, which were produced in the structures. The additional to the considered effect is increasing of homogeneity of dopant distribution in enriched by the dopant area of p–n-junction. In the present paper analysis of dopant redistribution in a multilayer structures during production a series of p–n-junctions, which was produced in the multilayer structures, has been done. We consider an approach to increase the sharpness of both d

APA, Harvard, Vancouver, ISO, and other styles

21

Li, Xingji, Hongbin Geng, Chaoming Liu, et al. "Radiation effects on bipolar junction transistors and integrated circuits produced by different energy Br ions." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 612, no. 1 (2009): 171–75. http://dx.doi.org/10.1016/j.nima.2009.10.165.

Full text

APA, Harvard, Vancouver, ISO, and other styles

22

WATANABE, MICHIO. "TECHNOLOGIES FOR THE FABRICATION OF NANOSCALE SUPERCONDUCTING CIRCUITS." Modern Physics Letters B 19, no. 09n10 (2005): 405–24. http://dx.doi.org/10.1142/s0217984905008529.

Full text

Abstract:

Researches on the fabrication of ~ 0.1 × 0.1 μ m 2 superconductor–insulator–superconductor (SIS) Josephson junctions are reviewed. Today, a typical dimension is 1–10 μm for Josephson junctions in superconducting integrated circuits. These Josephson junctions are defined by well-established photolithographic technology with reactive ion etching (RIE), and for the superconductor, Nb is almost always used. The merits of Nb include the facts that the superconducting transition temperature Tc of Nb (9.2 K ) is higher than the boiling point of He (4.2 K ), and that Nb has excellent stability against

APA, Harvard, Vancouver, ISO, and other styles

23

Rajaei, Ramin. "A Reliable, Low Power and Nonvolatile MTJ-Based Flip-Flop for Advanced Nanoelectronics." Journal of Circuits, Systems and Computers 27, no. 13 (2018): 1850205. http://dx.doi.org/10.1142/s0218126618502055.

Full text

Abstract:

Very large-scale integrated circuit (VLSI) design faces many challenges with today’s nanometer CMOS technology, including leakage current and reliability issues. Magnetic tunnel junction (MTJ) hybrid with CMOS transistors can offer many advantages for future VLSI design such as high performance, low power consumption, easy integration with CMOS and also nonvolatility. However, MTJ-based logic circuits suffer from a reliability challenge that is the read disturbance issue. This paper proposes a new nonvolatile magnetic flip-flop (MFF) that offers a disturbance-free sensing and a low power write

APA, Harvard, Vancouver, ISO, and other styles

24

Odzhaev, V. B., A. K. Panfilenko, A. N. Pyatlitski, et al. "INVESTIGATION OF INFLUENCE OF TECHNOLOGICAL IMPURITIES ON THE I–V CHARACTERISTICS OF THE BIPOLAR n–p–n-TRANSISTOR." Proceedings of the National Academy of Sciences of Belarus, Physical-Technical Series 63, no. 2 (2018): 244–49. http://dx.doi.org/10.29235/1561-8358-2018-63-2-244-249.

Full text

Abstract:

Contamination of the monocrystal silicon with technological impurities in the devices fabrication process exerts a considerable influence on the electro-physical characteristics of the bipolar n–p–n-transistors. Revelation of the causes of the labile reproducibility of the basic characteristics of the bipolar planar n–p–n-transistors is vital for the purpose of establishing the factors, determining reliability and stability of the operational parameters of the integrated circuits. There were investigated I–V characteristics of the various lots of the bipolar n–p–n-transistors, fabricated under

APA, Harvard, Vancouver, ISO, and other styles

25

Comizzoli, Robert B. "Failure Analysis of Junction Field Effect Transistor Integrated Circuits by Corona Charging." Journal of The Electrochemical Society 138, no. 4 (1991): 1098–100. http://dx.doi.org/10.1149/1.2085722.

Full text

APA, Harvard, Vancouver, ISO, and other styles

26

Yen, J. C., Q. Zhang, M. J. Mondry, et al. "Monolithic integrated resonant tunneling diode and heterostructure junction field effect transistor circuits." Solid-State Electronics 39, no. 10 (1996): 1449–55. http://dx.doi.org/10.1016/0038-1101(96)00065-2.

Full text

APA, Harvard, Vancouver, ISO, and other styles

27

Lovshenko, Ivan, Veranika Khanko, and Viktor Stempitsky. "Physic-topological (electrical) model of a junction field effect transistor, taking into account the degradation of operational characteristics under the influence of penetrating radiation." ITM Web of Conferences 30 (2019): 10002. http://dx.doi.org/10.1051/itmconf/20193010002.

Full text

Abstract:

The results of applying the compact model of junction field effect transistors developed and integrated into the Cadence software product for control to evaluate the hardness of a two-stage differential amplifier circuit under the combined or separate exposure to fluences of electrons, protons and neutrons are presented.

APA, Harvard, Vancouver, ISO, and other styles

28

Ачкасов, V. Achkasov, Чевычелов, et al. "Modelling of ionization effects and the effects of displacement in digital chips for CAD." Forestry Engineering Journal 4, no. 4 (2015): 280–90. http://dx.doi.org/10.12737/8491.

Full text

Abstract:

The methods of design of digital fault-tolerant bipolar integrated circuits to exposure to radiations such as gamma, x-ray and neutron radiation are considered, as well as the impact of the neutron pulse, which af-fect largely on the gain of the transistor. The operating mode of integrated circuits with change in the ini-tial values of voltages, as well as currents of the emitter and of the base is presented. Numerical calcula-tions of the ionization current in the base-collector junction are considered which allow pre-calculate dose rate of gamma, x-ray and neutron radiation.

APA, Harvard, Vancouver, ISO, and other styles

29

Spry, David J., Philip G. Neudeck, Liang Yu Chen, et al. "Processing and Prolonged 500 °C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect." Materials Science Forum 858 (May 2016): 908–12. http://dx.doi.org/10.4028/www.scientific.net/msf.858.908.

Full text

Abstract:

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC’s with two levels of metal interconnect capable of prolonged operation at 500 °C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 °C. A 3-stage oscillator functioned for over 3000 hours at 500 °C in ai

APA, Harvard, Vancouver, ISO, and other styles

30

Neudeck, Philip G., David J. Spry, and Liang-Yu Chen. "First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (2016): 000263–71. http://dx.doi.org/10.4071/2016-hitec-263.

Full text

Abstract:

Abstract A separate submission to this conference reports that 4H-SiC Junction Field Effect Transistor (JFET) digital and analog Integrated Circuits (ICs) with two levels of metal interconnect have reproducibly demonstrated electrical operation at 500 °C in excess of 1000 hours. While this progress expands the complexity and durability envelope of high temperature ICs, one important area for further technology maturation is the development of reasonably accurate and accessible computer-aided modeling and simulation tools for circuit design of these ICs. Towards this end, we report on developme

APA, Harvard, Vancouver, ISO, and other styles

31

Spry, David J., Philip G. Neudeck, Liang Yu Chen, et al. "Fabrication and Testing of 6H-SiC JFETs for Prolonged 500 °C Operation in Air Ambient." Materials Science Forum 600-603 (September 2008): 1079–82. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.1079.

Full text

Abstract:

This paper reports on the fabrication and testing of 6H-SiC junction field effect transistors (JFETs) and a simple differential amplifier integrated circuit that have demonstrated 2000 hours of electrical operation at 500 °C without degradation. The high-temperature ohmic contacts, dielectric passivation, and packaging technology that enabled such 500 °C durability are briefly described. Key JFET parameters of threshold voltage, on-state resistance, transconductance, and on-state current, as well as the gain of the differential amplifier integrated circuit, exhibited less than 7% change over t

APA, Harvard, Vancouver, ISO, and other styles

32

Gnana Prakash, A. P., and N. Pushpa. "Application of Pelletron Accelerator to Study High Total Dose Radiation Effects on Semiconductor Devices." Solid State Phenomena 239 (August 2015): 37–71. http://dx.doi.org/10.4028/www.scientific.net/ssp.239.37.

Full text

Abstract:

Silicon bipolar junction transistors (BJTs), Silicon-germanium heterojunction bipolar transistors (SiGe HBTs) and metal oxide semiconductor (MOS) devices are the key components of BiCMOS integrated circuits. The semiconductor devices need to withstand very high total doses (100’s of Mrad) for reliable operation of electronic circuits for 8-10 years of LHC operation. The study of radiation tolerance of semiconductor devices up to 100 Mrad of total dose takes longer time with conventional 60Co gamma, proton and electron irradiation facilities and the effects due to these radiations are well unde

APA, Harvard, Vancouver, ISO, and other styles

33

Spry, David J., Philip G. Neudeck, Liang Yu Chen, et al. "Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect." Materials Science Forum 858 (May 2016): 1112–16. http://dx.doi.org/10.4028/www.scientific.net/msf.858.1112.

Full text

Abstract:

The fabrication and prolonged 500 °C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 °C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 °C operating time. Evidence is pres

APA, Harvard, Vancouver, ISO, and other styles

34

Bargieł, Kamil, Damian Bisewski, and Janusz Zarębski. "Modelling of Dynamic Properties of Silicon Carbide Junction Field-Effect Transistors (JFETs)." Energies 13, no. 1 (2020): 187. http://dx.doi.org/10.3390/en13010187.

Full text

Abstract:

The paper deals with the problem of modelling and analyzing the dynamic properties of a Junction Field Effect Transistor (JFET) made of silicon carbide. An examination of the usefulness of the built-in JFET Simulation Program with Integrated Circuit Emphasis (SPICE) model was performed. A modified model of silicon carbide JFET was proposed to increase modelling accuracy. An evaluation of the accuracy of the modified model was performed by comparison of the measured and calculated capacitance–voltage characteristics as well as the switching characteristics of JFETs.

APA, Harvard, Vancouver, ISO, and other styles

35

Maralani, Ayden, Levent Beker, and Albert P. Pisano. "Toward Integrated Pressure Sensors for Temperatures up to 600°C." Journal of Microelectronics and Electronic Packaging 13, no. 4 (2016): 163–68. http://dx.doi.org/10.4071/imaps.522.

Full text

Abstract:

The main objective of this study is to develop pressure-sensing systems by integrating pressure transducers with the interface circuitry in one package that can withstand harsh environments, particularly high temperatures up to 600°C. To achieve that, both pressure transducer and interface circuitry are individually required to operate and survive up to 600°C with acceptable degrees of reliability. This article reports performance evaluation of fabricated 4H-SiC Junction Field Effect Transistors along with differential pairs for use in the interface circuitry. The test results are very promisi

APA, Harvard, Vancouver, ISO, and other styles

36

Ahlgren, D. C., S. J. Jeng, D. Nguyen-Ngoc, et al. "Si-Ge heterojunction bipolar technology for high-speed integrated circuits." Canadian Journal of Physics 74, S1 (1996): 159–66. http://dx.doi.org/10.1139/p96-851.

Full text

Abstract:

This review discusses the fundamentals of SiGe epitaxial base heterojunction bipolar transistor (HBT) technology that have been developed for use in analog and mixed-signal applications in the 1–20 GHz range. The basic principles of operation of the graded base SiGe HBT are reviewed. These principles are then used to explore the design optimization for analog applications. Device results are presented that illustrate some important trade-offs in device design. A discussion of the use of UHV/CVD for the deposition of the epitaxial base profile is followed by an overview of the integrated proces

APA, Harvard, Vancouver, ISO, and other styles

37

Holyaka, R. L., T. A. Marusenkova, and D. V. Fedasyuk. "LOGARITHMIC AMPLIFIERS FOR SOFTWARE HARDWARE MAGNETIC TRACKING SYSTEMS." ELECTRICAL AND COMPUTER SYSTEMS 33, no. 109 (2020): 33–45. http://dx.doi.org/10.15276/eltecs.33.109.2020.4.

Full text

Abstract:

The work deals with the problem of signal conversion in magnetic tracking devices. Magnetic tracking technology is based on computing the spatial position of an object being tracked upon measuring reference magnetic fields in low-frequency electromagnetic radiation spectrum. Magnetic tracking devices are key components of navigation sensors for virtual and augmented reality. It has been shown that the main problem one faces when developing sensory devices for magnetic tracking is the fact that signals should be measured in a wide measurement range. We have analyzed possible ways to solve the s

APA, Harvard, Vancouver, ISO, and other styles

38

Marcoux, J., J. Orchard-Webb, and J. F. Currie. "Complementary metal oxide semiconductor-compatible junction field-effect transistor characterization." Canadian Journal of Physics 65, no. 8 (1987): 982–86. http://dx.doi.org/10.1139/p87-156.

Full text

Abstract:

We report on the fabrication and electrical characterization of a vertical junction-gate field-effect transistor (JFET) that is compatible with all complementary metal oxide semiconductor (CMOS) technologies. It can be used as a buried load for an enhancement n-channel metal oxide semiconductor field-effect transistor (n-MOSFET), replacing the p-MOSFET within the standard CMOS inverter configuration and resulting in a 40% net area economy in standard cells. To be entirely CMOS process compatible, this JFET device differs from others in the literature in that dopant concentrations in the n subs

APA, Harvard, Vancouver, ISO, and other styles

39

Perez, S., A. M. Francis, J. Holmes, and T. Vrotsos. "Silicon Carbide Junction Field Effect Transistor Compact Model for Extreme Environment Integrated Circuit Design." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2021, HiTEC (2021): 000118–22. http://dx.doi.org/10.4071/2380-4491.2021.hitec.000118.

Full text

Abstract:

Abstract Presented is a temperature and geometry scalable 800°C Silicon Carbide (SiC) Junction Field Effect Transistor (JFET) compact device model designed to simulate the small signal effects of the SiC JFET-R process developed by NASA Glenn Research Center. With the JFET-R process pushing the temperature limits of integrated circuits, a high-fidelity device model capable of predicting the performance over temperature and geometry is required to realize the thermal ruggedness this process provides. A high temperature (HT) packaging system was utilized to characterize a SiC JFET device up to 8

APA, Harvard, Vancouver, ISO, and other styles

40

Neudeck, Philip G., David J. Spry, Liang Yu Chen, Dorothy Lukco, Carl W. Chang, and Glenn M. Beheim. "Experimentally Observed Electrical Durability of 4H-SiC JFET ICs Operating from 500 °C to 700 °C." Materials Science Forum 897 (May 2017): 567–70. http://dx.doi.org/10.4028/www.scientific.net/msf.897.567.

Full text

Abstract:

Prolonged 500 °C to 700 °C electrical testing data from 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) are combined with post-testing microscopic studies in order to gain more comprehensive understanding of the durability limits of the present version of NASA Glenn's extreme temperature microelectronics technology. The results of this study support the hypothesis that T ≥ 500 °C durability-limiting IC failure initiates with thermal stress-related crack formation where dielectric passivation layers overcoat micron-scale vertical features including patterned metal trace

APA, Harvard, Vancouver, ISO, and other styles

41

Kelley, Robin L., Michael S. Mazzola, and William L. Draper. "Improved Efficiency in Power Factor Correction Circuits with a pn-Gated SiC FET." Materials Science Forum 556-557 (September 2007): 995–98. http://dx.doi.org/10.4028/www.scientific.net/msf.556-557.995.

Full text

Abstract:

The purpose of this paper is to present an all-SiC switched AC-DC converter using active power factor correction. The typical boost-converter approach is employed using continuous conduction mode. A SiC Schottky barrier diode performs the free-wheeling diode function, and a 600 V, 0.12 % SiC vertical junction field effect transistor performs the switching function under the control of a Fairchild ML4821 integrated circuit. The converter is operable off-line over the full universal voltage range (85-260 VAC), but it was optimized for a 400-600 W application operating at 208 VAC. Results are pre

APA, Harvard, Vancouver, ISO, and other styles

42

Pisarenko, Ivan, and Eugeny Ryndin. "Photodetector with Controlled Relocation of Carrier Density Peaks: Concept and Numerical Simulation." Photonics 7, no. 1 (2020): 21. http://dx.doi.org/10.3390/photonics7010021.

Full text

Abstract:

Modern electronics faces the degradation of metal interconnection performance in integrated circuits with nanoscale feature dimensions of transistors. The application of constructively and technologically integrated optical links instead of metal wires is a promising way of the problem solution. Previously, we proposed the advanced design of an on-chip injection laser with an AIIIBV nanoheterostructure, and a functionally integrated optical modulator. To implement the efficient laser-modulator-based optical interconnections, technologically compatible photodetectors with subpicosecond response

APA, Harvard, Vancouver, ISO, and other styles

43

Lo, D. C. W., and S. R. Forrest. "Performance of In/sub 0.53/Ga/sub 0.47/As and InP junction field-effect transistors for optoelectronic integrated circuits. I. Device analysis." Journal of Lightwave Technology 7, no. 6 (1989): 957–65. http://dx.doi.org/10.1109/50.32364.

Full text

APA, Harvard, Vancouver, ISO, and other styles

44

Jia, Chuancheng, Marjan Famili, Marco Carlotti, et al. "Quantum interference mediated vertical molecular tunneling transistors." Science Advances 4, no. 10 (2018): eaat8237. http://dx.doi.org/10.1126/sciadv.aat8237.

Full text

Abstract:

Molecular transistors operating in the quantum tunneling regime represent potential electronic building blocks for future integrated circuits. However, due to their complex fabrication processes and poor stability, traditional molecular transistors can only operate stably at cryogenic temperatures. Here, through a combined experimental and theoretical investigation, we demonstrate a new design of vertical molecular tunneling transistors, with stable switching operations up to room temperature, formed from cross-plane graphene/self-assembled monolayer (SAM)/gold heterostructures. We show that v

APA, Harvard, Vancouver, ISO, and other styles

45

Lo, D. C. W., and S. R. Forrest. "Performance of In/sub 0.53/Ga/sub 0.47/As and InP junction field-effect transistors for optoelectronic integrated circuits. II. Optical receiver analysis." Journal of Lightwave Technology 7, no. 6 (1989): 966–71. http://dx.doi.org/10.1109/50.32365.

Full text

APA, Harvard, Vancouver, ISO, and other styles

46

Nadjet, Mokeddem, and Ghaffour Kheireddine. "Characterization and modeling the effect of temperature on power HBTs InGaP/GaAs." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 1 (2020): 581. http://dx.doi.org/10.11591/ijece.v10i1.pp581-588.

Full text

Abstract:

The variation and stability of HBT’s parameters at different temperatures are important for utilizing these devices in high-power integrated circuits. The temperature dependence of the DC current gain of bipolar transistors, as a key device parameter, has been extensively investigated. A major issue of the power HBT’s is that the current gain is decreased with junction temperature due to self-heating effect. Hence, how to stabilize the DC current gain and RF performances is important issue to develop the power HBTs. This work describes the DC and high-frequency temperature dependence of InGaP/

APA, Harvard, Vancouver, ISO, and other styles

47

Sverdlov, Viktor, and Siegfried Selberherr. "Demands for spin-based nonvolatility in emerging digital logic and memory devices for low power computing." Facta universitatis - series: Electronics and Energetics 31, no. 4 (2018): 529–45. http://dx.doi.org/10.2298/fuee1804529s.

Full text

Abstract:

Miniaturization of semiconductor devices is the main driving force to achieve an outstanding performance of modern integrated circuits. As the industry is focusing on the development of the 3nm technology node, it is apparent that transistor scaling shows signs of saturation. At the same time, the critically high power consumption becomes incompatible with the global demands of sustaining and accelerating the vital industrial growth, prompting an introduction of new solutions for energy efficient computations. Probably the only radically new option to reduce power consumption in novel integrat

APA, Harvard, Vancouver, ISO, and other styles

48

Chen, Yiyi, Yuying Yan, and Bo Li. "Thermal Analyses of Power Electronics Integrated with Vapour Chamber Cooling." Automotive Innovation 3, no. 4 (2020): 328–35. http://dx.doi.org/10.1007/s42154-020-00123-z.

Full text

Abstract:

AbstractInsulated gate bipolar transistor (IGBT) power module is used for power switching transistor devices in the power supply and motor control circuits in both hybrid electric vehicles and electric vehicles. The target of heat flux of IGBT is continuously increasing due to the demand for power rating improvements and miniaturisation. Without suitable efficient cooling technologies, excessively high temperature and uneven temperature distribution can cause high thermal stress, eventually leading to severe module failures. Therefore, highly efficient cooling solutions are highly required. Va

APA, Harvard, Vancouver, ISO, and other styles

49

Alexandru, Mihaela, Viorel Banu, Phillippe Godignon, Miguel Vellvehi, and José Millan. "4H-SiC Digital Logic Circuitry Based on P+ Implanted Isolation Walls MESFET Technology." Materials Science Forum 740-742 (January 2013): 1048–51. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.1048.

Full text

Abstract:

The design and development of SiC integrated circuits (ICs) nowadays is a necessity due to the increasing demand for high temperature intelligent power applications and intelligent sensors. Due to the superior electrical, mechanical and chemical proprieties of 4H-SiC poly-type, 4H-SiC MESFET transistor is a good compromise for ICs on SiC able to work at higher temperatures (HT) than on Si. This paper presents new experimental results of approaching embedded logic gates with SiC MESFETs and resistors, built in junction-isolated tubs. The P+ implantation isolation technology offers important per

APA, Harvard, Vancouver, ISO, and other styles

50

Spry, David J., Philip G. Neudeck, and Carl W. Chang. "Experimental Study on Mitigation of Lifetime-Limiting Dielectric Cracking in Extreme Temperature 4H-SiC JFET Integrated Circuits." Materials Science Forum 1004 (July 2020): 1148–55. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.1148.

Full text

Abstract:

While NASA Glenn Research Center’s “Generation 10” 4H-SiC Junction Field Effect Transistor (JFET) integrated circuits (ICs) have uniquely demonstrated 500 °C electrical operation for durations of over a year, this experimental work has also revealed that physical cracking of chip dielectric passivation layers ultimately limits extreme-environment operating lifetime [1-3]. The prevention of such dielectric passivation cracks should therefore improve IC high temperature durability and yield, leading to more beneficial technology adoption into aerospace, automotive, and energy systems. This repor

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!