To see the other types of publications on this topic, follow the link: Integrated circuits – Ultra large scale integration.

Journal articles on the topic 'Integrated circuits – Ultra large scale integration'

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'Integrated circuits – Ultra large scale integration.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

HASEGAWA, HIDEKI, SEIYA KASAI, and TAKETOMO SATO. "TOWARD ULTRA-LOW POWER III-V QUANTUM LARGE SCALE INTEGRATED CIRCUITS FOR UBIQUITOUS NETWORK ERA." International Journal of High Speed Electronics and Systems 16, no. 02 (2006): 421–36. http://dx.doi.org/10.1142/s0129156406003758.

Full text
Abstract:
In an attempt to realize tiny "knowledge vehicles" called intelligent quantum (IQ) chips for use in the coming ubiquitous network society, this paper presents the present status and future prospects of ultra-small-size and ultra-low-power III-V quantum logic large scale integrated circuits based on a novel hexagonal binary-decision diagram (BDD) quantum circuit architecture. Here, quantum transport in path switching node devices formed on III-V semiconductor-based hexagonal nanowire networks is controlled by nanometer scale Schottky wrap gates (WPGs) to realize arbitrary combinational logic function. Feasibility of the approach is shown through fabrication of basic node devices and various small-scale circuits, and approaches for higher density integration and larger scale circuits are discussed.
APA, Harvard, Vancouver, ISO, and other styles
2

Iwai, Hiroshi, Kuniyuki Kakushima, and Hei Wong. "CHALLENGES FOR FUTURE SEMICONDUCTOR MANUFACTURING." International Journal of High Speed Electronics and Systems 16, no. 01 (2006): 43–81. http://dx.doi.org/10.1142/s0129156406003539.

Full text
Abstract:
The downsizing of CMOS devices has been accelerated very aggressively in both production and research in recent years. Sub-100 nm gate length CMOS large-scale integrated circuits (LSIs) have been used for many applications and five nanometer gate length MOS transistor was even reported. However, many serious problems emerged when such small geometry MOSFETs are used to realize a large-scale integrated circuit. Even at the 'commercial 45 nm (HP65nm) technology node', the skyrocketing rise of the production cost becomes the greatest concern for maintaining the downsizing trend towards 10 nm. In this paper, future semiconductor manufacturing challenges for nano-sized devices and ultra large scale circuits are analyzed. The portraits of future integration circuit fabrication and the distribution of semiconductor manufacturing centers in next decade are sketched. The possible limits for the scaling will also be elaborated.
APA, Harvard, Vancouver, ISO, and other styles
3

Yao, Yuhan, Yanxian Wei, Jianji Dong, Ming Li, and Xinliang Zhang. "Large-Scale Reconfigurable Integrated Circuits for Wideband Analog Photonic Computing." Photonics 10, no. 3 (2023): 300. http://dx.doi.org/10.3390/photonics10030300.

Full text
Abstract:
Photonic integrated circuits (PICs) have been a research hotspot in recent years. Programmable PICs that have the advantages of versatility and reconfigurability that can realize multiple functions through a common structure have been especially popular. Leveraging on-chip couplers and phase shifters, general-purpose waveguide meshes connected in different topologies can be manipulated at run-time and support a variety of applications. However, current waveguide meshes suffer from relatively a low cell amount and limited bandwidth. Here, we demonstrate a reconfigurable photonic integrated computing chip based on a quadrilateral topology network, where typical analog computing functions, including temporal differentiation, integration, and Hilbert transformation, are implemented with a processing bandwidth of up to 40 GHz. By configuring an optical path and changing the splitting ratio of the optical switches in the network, the functions can be switched and the operation order can be tuned. This approach enables wideband analog computing of large-scale PICs in a cost-effective, ultra-compact architecture.
APA, Harvard, Vancouver, ISO, and other styles
4

Sathyakam, P. Uma, and Partha S. Mallick. "Future Dielectric Materials for CNT Interconnects - Possibilities and Challenges." Journal of Nano Research 52 (May 2018): 21–42. http://dx.doi.org/10.4028/www.scientific.net/jnanor.52.21.

Full text
Abstract:
Carbon nanotube (CNT) interconnects are emerging as the ultimate choice for next generation ultra large scale integrated (ULSI) circuits. Significant progress in precise growth of aligned CNTs and integration of multiwalled CNT interconnects into a test chip make them promising candidates for future nanoelectronic chips. Tremendous research efforts were made on silicon based ultra-low-k dielectrics for Cu interconnects, but, the most recent advancements in polymer based composites as dielectric materials open up fresh challenges in the use of low-k dielectrics for CNT interconnects. This paper reviews the emerging polymer composites like Boron Nitride Nanotubes, Graphene/Polyimide composites, Metal Organic Frameworks and small diameter CNTs. Many reviews are already exists on the synthesis, fabrication, dielectric, mechanical, chemical and thermal properties of these materials. In this review, we have explained the specific properties of these materials and the necessities for integrating them into CNT interconnects to meet the requirements of future IC designers.Keywords: low-k dielectric materials, ultra low-k dielectrics, carbon nanotubes, interconnects, dielectric constant,
APA, Harvard, Vancouver, ISO, and other styles
5

Chen, Xiangyu, Takeaki Yajima, Isao H. Inoue, and Tetsuya Iizuka. "An ultra-compact leaky integrate-and-fire neuron with long and tunable time constant utilizing pseudo resistors for spiking neural networks." Japanese Journal of Applied Physics 61, SC (2022): SC1051. http://dx.doi.org/10.35848/1347-4065/ac43e4.

Full text
Abstract:
Abstract Spiking neural networks (SNNs) inspired by biological neurons enable a more realistic mimicry of the human brain. To realize SNNs similar to large-scale biological networks, neuron circuits with high area efficiency are essential. In this paper, we propose a compact leaky integrate-and-fire (LIF) neuron circuit with a long and tunable time constant, which consists of a capacitor and two pseudo resistors (PRs). The prototype chip was fabricated with TSMC 65 nm CMOS technology, and it occupies a die area of 1392 μm2. The fabricated LIF neuron has a power consumption of 6 μW and a leak time constant of up to 1.2 ms (the resistance of PR is up to 600 MΩ). In addition, the time constants are tunable by changing the bias voltage of PRs. Overall, this proposed neuron circuit facilitates the very-large-scale integration of adaptive SNNs, which is crucial for the implementation of bio-scale brain-inspired computing.
APA, Harvard, Vancouver, ISO, and other styles
6

Zeng, Xiang, Jin Jiang He, Xuan Jiang, Hao Zeng, Xiao Yong Wan, and Zai Yan Shang. "Research on Grain Refinement Process and Microstructure of Ultra-High Purity Copper Used for Integrated Circuit." Materials Science Forum 852 (April 2016): 601–6. http://dx.doi.org/10.4028/www.scientific.net/msf.852.601.

Full text
Abstract:
In this paper, the deformation and annealing process of ultra-high purity copper used for Ultra large-scale integration (ULSI) have been investigated. The evolution of grain size and texture during deforming and annealing were analyzed. The results show that the coarse cast structure can be efficiently eliminated by multiple forging and the grain size can be refined initially. Ultra-high purity copper with cold rolling begins to recrystallize at a temperature of 150°C. Especially, when the cold rolling deformation is 80%, the average grain size is about 17.9μm after optimized annealing. The typical rolling textures after deformation are not strong and a large number of low-angle grain boundaries are found. After annealing, the rolling texture and recrystallization texture come to co-existence. The texture distribution is uniform without strong grain orientation and high-angle boundaries demonstrate in the microstructure.
APA, Harvard, Vancouver, ISO, and other styles
7

Chen, Mengwen, Chenyu Wang, Xiao-Hui Tian, et al. "Wafer-Scale Periodic Poling of Thin-Film Lithium Niobate." Materials 17, no. 8 (2024): 1720. http://dx.doi.org/10.3390/ma17081720.

Full text
Abstract:
Periodically poled lithium niobate on insulator (PPLNOI) offers an admirably promising platform for the advancement of nonlinear photonic integrated circuits (PICs). In this context, domain inversion engineering emerges as a key process to achieve efficient nonlinear conversion. However, periodic poling processing of thin-film lithium niobate has only been realized on the chip level, which significantly limits its applications in large-scale nonlinear photonic systems that necessitate the integration of multiple nonlinear components on a single chip with uniform performances. Here, we demonstrate a wafer-scale periodic poling technique on a 4-inch LNOI wafer with high fidelity. The reversal lengths span from 0.5 to 10.17 mm, encompassing an area of ~1 cm2 with periods ranging from 4.38 to 5.51 μm. Efficient poling was achieved with a single manipulation, benefiting from the targeted grouped electrode pads and adaptable comb line widths in our experiment. As a result, domain inversion is ultimately implemented across the entire wafer with a 100% success rate and 98% high-quality rate on average, showcasing high throughput and stability, which is fundamentally scalable and highly cost-effective in contrast to traditional size-restricted chiplet-level poling. Our study holds significant promise to dramatically promote ultra-high performance to a broad spectrum of applications, including optical communications, photonic neural networks, and quantum photonics.
APA, Harvard, Vancouver, ISO, and other styles
8

Kaloyeros, Alain E., and Michael A. Fury. "Chemical Vapor Deposition of Copper for Multilevel Metallization." MRS Bulletin 18, no. 6 (1993): 22–29. http://dx.doi.org/10.1557/s0883769400047291.

Full text
Abstract:
Since the birth of integrated circuitry about thirty five years ago, microelectronics design and manufacturing technologies have evolved toward higher integration density with smaller design rules. As the semiconductor industry moves into ultra-large-scale integration (ULSI), device geometries continue to shrink into the sub-half-micron region while circuit densities increase to optimize reliability and improve performance. The resulting demands on interconnect technologies necessitate the exploitation of all development avenues: design, materials, and manufacturing.Emerging sub-half-micron technologies require multilevel metallization (MLM) design schemes that reduce interconnection lengths and lead to lower signal transmission delays and enhanced device speeds. MLM schemes also permit increased device density, due to the ability to use the third (vertical) dimension, and easier signal routing because of higher flexibility in architectural design. These schemes, in turn, demand interconnect metals that can handle the higher current densities resulting from the decreasing size of device features, without the loss of electrical and structural integrity, and deliver the sheet resistance needed to meet performance demands. They also require reliable deposition techniques to successfully fabricate the increasingly complex architectures as lateral feature sizes are scaled down more rapidly than conductor or insulator thicknesses.
APA, Harvard, Vancouver, ISO, and other styles
9

Gong, Xiao, Kaizhen Han, Chen Sun, et al. "Beol-Compatible Ingazno-Based Devices for 3D Integrated Circuits." ECS Meeting Abstracts MA2022-02, no. 32 (2022): 1186. http://dx.doi.org/10.1149/ma2022-02321186mtgabs.

Full text
Abstract:
Due to its attractive materials and electrical properties, indium-gallium-zinc-oxide (IGZO) has been extensively researched in many emerging technologies, especially for three-dimensional (3D) monolithic integration and back-end-of-line (BEOL) compatible applications [1]. On the pathway toward the realization of high-performance 3D monolithic integrated chips (ICs), a wide range of building blocks with different functionalities are required. 3D monolithic ICs also demand optimization in device performance and circuit architecture design. In this paper, we discuss our recent research development in IGZO-based techniques at both device and circuit levels. This includes nanowire structure for IGZO-based transistors, as well as the BEOL-compatible ferroelectric ternary content-addressable memory (TCAM) and embedded dynamic random-access-memory (eDRAM) for compute-in-memory (CiM) using IGZO-based transistors. A novel digital etch technique for amorphous IGZO (α-IGZO) material as well as the formation of α-IGZO nanowires were realized, enabling high performance α-IGZO nanowire field-effect transistors (NWFETs) with ultra-scaled nanowire width (W NW) [2]. The scanning electron microscopy (SEM) images of α-IGZO nanowire before and after the digital etch show that the nanowire structure as well as W NW reduction after digital etch can be clearly observed. The smallest α-IGZO nanowire after digital etch has a W NW of ~20 nm. By leveraging the ultra-scaled nanowire structure, the NWFET with the smallest W NW achieves decent subthreshold swing of 80 mV/decade as well as high peak extrinsic transconductance (G m,ext) of 612 μS/μm at a drain to source voltage (V DS) = 2 V (456 μS/μm at V DS = 1 V). As compared with previous works in literature, our IGZO NWFET achieves one of the highest peak G m among all IGZO-based FETs. α-IGZO ferroelectric FETs (Fe-FETs) with a metal-ferroelectric-metal-oxide-semiconductor (MFMIS) structure were further realized based on the α-IGZO transistor process modules. The smallest L CH is as small as 40 nm. The cross-sectional transmission electron microscopy (TEM) image of the device shows sharp interface. The α-IGZO Fe-FETs achieve a large memory window of 2.9 V, high endurance of 108 cycles, high conductance ratio, and small cycle-to-cycle variation. By leveraging the low temperature processed α-IGZO Fe-FETs with good electrical characteristics, a BEOL-compatible ferroelectric TCAM circuit with 2 Fe-FETs connected in parallel was realized [3], showing an extremely large sensing margin. In addition, such α-IGZO Fe-FET TCAM reduces the transistor number from 16 to 2 as compared to traditional SRAM-based TCAM. Smaller cell size and higher energy efficiency can also be obtained. IGZO transistors can play an important role in in-memory computing as well. SEM image of the eDRAM CiM cell shows utilization of IGZO transistors. The smallest device has L CH of 45 nm [4]. The IGZO transistor-based eDRAM CiM with differential cell structure achieves low leakage current, low variation, low charge loss sensitivity, and the control-friendly charge-domain computing without DC power. By evaluating the key figure-of-merits, including precision, power efficiency, computing density, retention time, and robustness, it can be concluded that our IGZO transistor-based eDRAM CiM is promising for low-power and scalable compute-in-eDRAM design. Acknowledgments: This work is supported by Singapore Ministry of Education (Tier 2: MOE2018-T2-2-154, Tier 1: R-263-000-D65-114). References: [1] K. Normura et al., Nature, 432 (7016), 488-492, 2004. [2] K. Han et al., VLSI, 2021, p. T10-1. [3] C. Sun et al., VLSI, 2021, p. T7-4. [4] J. Liu et al., IEDM, 2021, p. 462.
APA, Harvard, Vancouver, ISO, and other styles
10

Tucker, J. R., and T. C. Shen. "Fabricating an all-epitaxial silicon quantum computer." Quantum Information and Computation 1, Special (2001): 129–33. http://dx.doi.org/10.26421/qic1.s-14.

Full text
Abstract:
Scalable silicon quantum computers will require a material perfection that has never been attempted. Ground state wavefunctions for conduction electrons orbiting individual phosphorous donors must be polarized electronically and coupled to nearest neighbors with great precision. Elimination of all randomizing influences can be achieved only with a fully epitaxial structure; and we believe that output circuitry must also be integrated into the qubit arrays in order to achieve the uniformity needed for large-scale integration. A process that could potentially accomplish this will be outlined, based on scanning tunneling microscope (STM) removal of individual hydrogen atoms from the H-terminated silicon surface followed by phosphine dosing and ultra-low-temperature overgrowth. Self-ordering of PH3 molecules onto extended areas of bare silicon should permit patterning of planar single-electron transistors along with P-donor qubits in the same lithographic step. Initial plans for an experiment to characterize exchange coupling under gate control will be described.
APA, Harvard, Vancouver, ISO, and other styles
11

Fair, R. B. "Challenges to manufacturing submicron, ultra-large scale integrated circuits." Proceedings of the IEEE 78, no. 11 (1990): 1687–705. http://dx.doi.org/10.1109/5.63298.

Full text
APA, Harvard, Vancouver, ISO, and other styles
12

Gamra, D., F. Ouerghi, W. Belhadj, F. Abdelmalek, M. Mejatty, and H. Bouchriha. "Analysis of ultra-small photonic large scale integrated circuits." Optical and Quantum Electronics 36, no. 12 (2004): 1105–15. http://dx.doi.org/10.1007/s11082-004-3549-7.

Full text
APA, Harvard, Vancouver, ISO, and other styles
13

Garth, Simon C. J. "Electron beam testing of ultra large scale integrated circuits." Microelectronic Engineering 4, no. 2 (1986): 121–38. http://dx.doi.org/10.1016/0167-9317(86)90099-7.

Full text
APA, Harvard, Vancouver, ISO, and other styles
14

NAWAFUNE, Hidemi. "New Technologies for Scaled-down Cu Interconnection in Ultra-Large Scale Integrated Circuits. Prospects on Copper Plating Systems for Ultra-large Scale Integrated Circuits." Journal of the Surface Finishing Society of Japan 49, no. 11 (1998): 1180–84. http://dx.doi.org/10.4139/sfj.49.1180.

Full text
APA, Harvard, Vancouver, ISO, and other styles
15

Chen, Xiangfei. "Precision photonic integration for future large-scale photonic integrated circuits." Journal of Semiconductors 40, no. 5 (2019): 050301. http://dx.doi.org/10.1088/1674-4926/40/5/050301.

Full text
APA, Harvard, Vancouver, ISO, and other styles
16

Han, Juyeon, Seokgyu Ryu, Harim Seo, et al. "Monolithic Self-Charging Storage Device with Stable 3 V Operation." ECS Meeting Abstracts MA2023-02, no. 1 (2023): 43. http://dx.doi.org/10.1149/ma2023-02143mtgabs.

Full text
Abstract:
Monolithic self-charging storage device with Stable 3 V Operation The energy paradigm has been changing from the traditional power plant system to micro-gride system based on renewable energy. However, renewable energy including wind, solar, and vibration, is intermittent and influenced by time, weather, and location. Thus, the suitable storage device is required for efficient utilization of renewable energy. The representative combination of renewable energy and energy storage device is an energy storage system (EES) consisting of photovoltaic systems and Lithium-ion batteries. The EES is mainly applied to social infrastructure system that generate large amounts of energy. As the Fourth Industrial Revolution progresses, the rechargeable power supply including Lithium-ion batteries is widely applied to wireless system such as sensor network, wearable device, and electric vehicles. However, the batteries have only storage function, so periodic charging is required. Thus, it is necessary to develop technologies for portable and small energy generation/storage as standalone power sources that can continuously supply power to various electronic devices. Large-scale energy production/storage system has entered the maturity stage, but the development of portable and small energy generation/storage systems based on IoT is in its early stages. To date, research on this system is conducted by simply connecting energy harvesting and energy storage device to external wires after manufacturing them independently. However, the introduction of additional wires is complicated in system design and manufacturing and has difficulty in miniaturization. These problems have motivated the integration of both functions into one device. The integrated device is fabricated by sharing one electrode, called a common electrode between the energy harvesting and storage components. Currently, research on a monolithic photo-charging storage device that integrates solar cells and energy storage devices into one device has been developed. This structure can miniaturization and flexible design, thereby it is suitable for the wearable and smart device. Although the importance of an integrated device is emphasized, the current research of monolithic device is limited to the fabrication of an integrated device without considering their practicability. In other words, most studies focus on simply connecting two devices to achieve the highest overall efficiency. In this case, since the open circuit voltage of single solar cell is under 1 V, the operation of photo-charging storage device is limited to 1 V. Thus, we proposed the monolithic photo-charging storage device operating at 3 V. We fabricated the multiple series-connected perovskite solar cell to increase the operating voltage. Since the secondary batteries are difficult to be charged by the high current density of 20 mA cm−2 solar cell owing to their storage mechanism, we choose the supercapacitor with the rapid response to an applied electric field change. We select the silver paste as the common electrode owing to its strong adhesion, high electric conductivity, and lack of chemical/mechanical damage to the solar cell and supercapacitor. Based on density functional theory (DFT) calculation, we prove the common electrode exhibits good compatibility with our supercapacitor and solar cell. For this reason, the proposed photo-charging storage device exhibits an ultra-fast charging time of less than 3 sec under AM 1.5 G illumination and high overall efficiency of 13.17 % at 1 mA cm−2 and 9.87 % at 20 mA cm−2. For electric double layer supercapacitors integrated with a solar cell, higher discharging current densities that 20 mA cm−2 have not been reported so far. We firstly demonstrate the behavior of photo-charging storage device under light/dark state by the impedance analysis. By the impedance analysis, we demonstrated that the solar cell provides a stable power supply to the supercapacitor under light condition. Further, the additional encapsulation ensures the long-term stability of photo-charging storage device and demonstrate the indoor cycling performance. We prove the photo-charging storage device has high potential as an IoT sensor power source. Figure 1
APA, Harvard, Vancouver, ISO, and other styles
17

NAWAFUNE, Hidemi, Seiichiro NAKAO, Shozo MIZUMOTO, Yoshiki MURAKAMI, and Shin HASHIMOTO. "Fabrication of Ultra-large Scale Integrated Circuits by Electroless Copper Plating System." Journal of the Surface Finishing Society of Japan 49, no. 12 (1998): 1360–61. http://dx.doi.org/10.4139/sfj.49.1360.

Full text
APA, Harvard, Vancouver, ISO, and other styles
18

Yang, Boyu. "Very Large-Scale Integration Circuit and Its Current Status Analysis." Highlights in Science, Engineering and Technology 71 (November 28, 2023): 421–27. http://dx.doi.org/10.54097/hset.v71i.14627.

Full text
Abstract:
The development of Very Large Scale Integration (VLSI) has become very relevant to our lives, and although many of the technologies have matured, scientists are still actively exploring and innovating them. This article is a basic introduction to the composition and advanced technology of large-scale integrated circuits, focusing on transistors and the basic components it consists of, as well as the design of integrated circuits, manufacturing and measurement technology. Very Large Scale Integration Circuit, the transistor is the most basic component of the original, to the low-power CMOS tube is the most widely used, they form a logic gate and storage elements, to achieve a variety of basic functions of the circuit, while the circuit also exists to provide signal distribution and interconnection of the clock network, the optimization of the design of the contemporary research is also a hot spot. In recent years, the progress of the chip can not be separated from the development of new technologies, SOC technology, low-power technology and detection technology plays an important role in the promotion.
APA, Harvard, Vancouver, ISO, and other styles
19

Harris, Nicholas C., Darius Bunandar, Mihir Pant, et al. "Large-scale quantum photonic circuits in silicon." Nanophotonics 5, no. 3 (2016): 456–68. http://dx.doi.org/10.1515/nanoph-2015-0146.

Full text
Abstract:
AbstractQuantum information science offers inherently more powerful methods for communication, computation, and precision measurement that take advantage of quantum superposition and entanglement. In recent years, theoretical and experimental advances in quantum computing and simulation with photons have spurred great interest in developing large photonic entangled states that challenge today’s classical computers. As experiments have increased in complexity, there has been an increasing need to transition bulk optics experiments to integrated photonics platforms to control more spatial modes with higher fidelity and phase stability. The silicon-on-insulator (SOI) nanophotonics platform offers new possibilities for quantum optics, including the integration of bright, nonclassical light sources, based on the large third-order nonlinearity (χ(3)) of silicon, alongside quantum state manipulation circuits with thousands of optical elements, all on a single phase-stable chip. How large do these photonic systems need to be? Recent theoretical work on Boson Sampling suggests that even the problem of sampling from e30 identical photons, having passed through an interferometer of hundreds of modes, becomes challenging for classical computers. While experiments of this size are still challenging, the SOI platform has the required component density to enable low-loss and programmable interferometers for manipulating hundreds of spatial modes.Here, we discuss the SOI nanophotonics platform for quantum photonic circuits with hundreds-to-thousands of optical elements and the associated challenges. We compare SOI to competing technologies in terms of requirements for quantum optical systems. We review recent results on large-scale quantum state evolution circuits and strategies for realizing high-fidelity heralded gates with imperfect, practical systems. Next, we review recent results on silicon photonics-based photon-pair sources and device architectures, and we discuss a path towards large-scale source integration. Finally, we review monolithic integration strategies for single-photon detectors and their essential role in on-chip feed forward operations.
APA, Harvard, Vancouver, ISO, and other styles
20

Patel, Ambresh, and Ritesh Sadiwala. "Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 15, no. 01 (2023): 91–95. http://dx.doi.org/10.18090/10.18090/samriddhi.v15i01.13.

Full text
Abstract:
The demand for VLSI low voltage high-performance low power systems are increasing significantly. Today's deviceapplications necessitate a system that consumes little power and conserves performance. Recent battery-powered lowvoltagedevices optimize power and high-speed constraints. Aside from that, there is a design constraint with burst-modetype integrated circuits for small devices to scale down. Low voltage low power static CMOS logic integrated circuitsoperate at a slower rate and cannot be used in high performance circuits. As a result, dynamic CMOS logic is used inintegrated circuits because it requires fewer transistors, has lower parasitic capacitance, is faster, and enables pipelinedsystem architecture with glitch-free circuits. It has, however, increased power dissipation. Both types of CMOS circuits withlow power dissipation overcome their own shortcomings.This paper discusses dynamic CMOS logic circuits and their structures. Various logics are also discussed and on the basisof the results obtained, logic which is best suited for designing CMOS logic circuit will be found out. The logic on the basisof structure layout and design which gives best results for high-speed VLSI circuits, is found out.
APA, Harvard, Vancouver, ISO, and other styles
21

Zhang, Chuang, Chang-Ling Zou, Yan Zhao, et al. "Organic printed photonics: From microring lasers to integrated circuits." Science Advances 1, no. 8 (2015): e1500257. http://dx.doi.org/10.1126/sciadv.1500257.

Full text
Abstract:
A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 105, which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices.
APA, Harvard, Vancouver, ISO, and other styles
22

Kalra, Shruti, та A. B. Bhattacharyya. "An Analytical Study Of Temperature Dependence of Scaled CMOS Digital Circuits Using α-Power MOSFET Model". Journal of Integrated Circuits and Systems 11, № 1 (2016): 57–68. http://dx.doi.org/10.29292/jics.v11i1.430.

Full text
Abstract:
Aggressive technological scaling continues to drive ultra-large-scale-integrated chips to higher clock speed. This causes large power consumption leading to considerable thermal generation and on-chip temperature gradient. Though much of the research has been focused on low power design, thermal issues still persist and need attention for enhanced integrated circuit reliability. The present paper outlines a methodology for a first hand estimating effect of temperature on basic CMOS building blocks at ultra deep submicron technology nodes utilizing modified α-power law based MOSFET model. The generalized α-power model is further applied for calculating Zero Temperature Coefficient (ZTC) point that provides temperature-independent operation of high performance and low power digital circuits without the use of conditioning circuits. The performance of basic digital circuits such as Inverter, NAND, NOR and XOR gate has been analyzed and results are compared with BSIM4 with respect to temperature up to 32nm technology node. The error lies within an acceptable range of 5-10%.
APA, Harvard, Vancouver, ISO, and other styles
23

Kanazawa, Yusuke, Tetsuya Asai, and Yoshihito Amemiya. "Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses." Journal of Robotics and Mechatronics 15, no. 2 (2003): 208–18. http://dx.doi.org/10.20965/jrm.2003.p0208.

Full text
Abstract:
We discuss the integration architecture of spiking neurons, predicted to be next-generation basic circuits of neural processor and dynamic synapse circuits. A key to development of a brain-like processor is to learn from the brain. Learning from the brain, we try to develop circuits implementing neuron and synapse functions while enabling large-scale integration, so large-scale integrated circuits (LSIs) realize functional behavior of neural networks. With such VLSI, we try to construct a large-scale neural network on a single semiconductor chip. With circuit integration now reaching micron levels, however, problems have arisen in dispersion of device performance in analog IC and in the influence of electromagnetic noise. A genuine brain computer should solve such problems on the network level rather than the element level. To achieve such a target, we must develop an architecture that learns brain functions sufficiently and works correctly even in a noisy environment. As the first step, we propose an analog circuit architecture of spiking neurons and dynamic synapses representing the model of artificial neurons and synapses in a form closer to that of the brain. With the proposed circuit, the model of neurons and synapses can be integrated on a silicon chip with metal-oxide-semiconductor (MOS) devices. In the sections that follow, we discuss the dynamic performance of the proposed circuit by using a circuit simulator, HSPICE. As examples of networks using these circuits, we introduce a competitive neural network and an active pattern recognition network by extracting firing frequency information from input information. We also show simulation results of the operation of networks constructed with the proposed circuits.
APA, Harvard, Vancouver, ISO, and other styles
24

Chen, Jia He, Xiang Yang Ma, and De Ren Yang. "Impurity Engineering of Czochralski Silicon." Solid State Phenomena 156-158 (October 2009): 261–67. http://dx.doi.org/10.4028/www.scientific.net/ssp.156-158.261.

Full text
Abstract:
The novel concept of “impurity engineering in CZochralski (CZ) silicon ” for large scaled integrated circuits has been reviewed. By doping with a certain impurities into CZ silicon materials intentionally, such as nitrogen (N), germanium (Ge) and even carbon (C, with high concentration), internal gettering ability of CZ silicon wafers could be improved. Meanwhile, void defects in CZ silicon wafer could be easily eliminated during annealing at higher temperatures. Furthermore, it was also found that the mechanical strength could be increased, so that breakage of wafers decreased. Thus, it is believed that by impurity engineering CZ silicon wafers can satisfy the requirment of ultra large scale integrated circuits.
APA, Harvard, Vancouver, ISO, and other styles
25

M, Thillai Rani, Rajkumar R, Sai Pradeep K.P, Jaishree M, and Rahul S.G. "Integrated extreme gradient boost with c4.5 classifier for high level synthesis in very large scale integration circuits." ITM Web of Conferences 56 (2023): 01005. http://dx.doi.org/10.1051/itmconf/20235601005.

Full text
Abstract:
High-level synthesis (HLS) is utilized for high-performance and energy-efficient heterogeneous systems designing. HLS is assist in field-programmable gate array circuits designing where hardware implementations are refined and replaced in target device. However, the power-process-voltage-temperature-delay (PPVTD) variation in VLSI circuits undergoes many problems and reduced the performance. In order to address these problems, C4.5 with eXtreme Gradient Boosting Classification based High Level Synthesis (C4.5-XGBCHLS) Method is designed for afford better runtime adaptability (RA) with minimal error rate. VLSI circuits are designed using the behavioral input and results are measured at running condition. When VLSI circuit’s results get reduced, the language description of the circuit is considered as an input. Then, compilation process convert high level specification into Intermediate Representation (IR) in control/data flow graph (CDFG). CDFG computes data and control dependencies among operations. eXtreme Gradient Boosting (XGBoost) Classifier is exploited in C4.5-XGBCHLS method to classify the error causing functional unit (FU) with minimal error rate. XGBoost Classifier exploited C4.5 decision tree as base classifier to enhance classification of error causing FU in VLSI circuits. After that, FU gets allocated in place of error causing FU from functional library based on the design objectives and PPVTD variations. Finally, operation scheduling and binding process is executed for register transfer level (RTL) generation to form VLSI circuits with improved RA. The simulation results shows that the C4.5-XGBCHLS method enhances the performance of functional unit selection accuracy (FUSA) with minimal error rate (ER) and circuit adaptability time (CAT).
APA, Harvard, Vancouver, ISO, and other styles
26

Uchikoga, Shuichi. "Low-Temperature Polycrystalline Silicon Thin-Film Transist or Technologies for System-on-Glass Displays." MRS Bulletin 27, no. 11 (2002): 881–86. http://dx.doi.org/10.1557/mrs2002.277.

Full text
Abstract:
AbstractThe elimination of conventional peripheral LSI (large-scale integration) drivers is considered essential to the development of future low-cost, energy-efficient, lightweight, and thin displays. System-on-glass (SOG) displays are a type of display with various functional circuits integrated on a glass substrate. Low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) make the integration of circuits possible because they can be assembled into complex, high-current driver circuits. Furthermore, LTPS TFTs are attracting attention for driving organic light-emitting devices (OLEDs). This article introduces present and future LTPS TFT technologies for SOG displays.
APA, Harvard, Vancouver, ISO, and other styles
27

Wang, Zhicheng, Junbo Feng, Haitang Li, et al. "Ultra-Compact and Broadband Nano-Integration Optical Phased Array." Nanomaterials 13, no. 18 (2023): 2516. http://dx.doi.org/10.3390/nano13182516.

Full text
Abstract:
The on-chip nano-integration of large-scale optical phased arrays (OPAs) is a development trend. However, the current scale of integrated OPAs is not large because of the limitations imposed by the lateral dimensions of beam-splitting structures. Here, we propose an ultra-compact and broadband OPA beam-splitting scheme with a nano-inverse design. We employed a staged design to obtain a T-branch with a wavelength bandwidth of 500 nm (1300–1800 nm) and an insertion loss of −0.2 dB. Owing to the high scalability and width-preserving characteristics, the cascaded T-branch configuration can significantly reduce the lateral dimensions of an OPA, offering a potential solution for the on-chip integration of a large-scale OPA. Based on three-dimensional finite-difference time-domain (3D FDTD) simulations, we demonstrated a 1 × 16 OPA beam-splitter structure composed entirely of inverse-designed elements with a lateral dimension of only 27.3 μm. Additionally, based on the constructed grating couplers, we simulated the range of the diffraction angle θ for the OPA, which varied by 0.6°–41.6° within the wavelength range of 1370–1600 nm.
APA, Harvard, Vancouver, ISO, and other styles
28

Im, James S., and Robert S. Sposili. "Crystalline Si Films for Integrated Active-Matrix Liquid-Crystal Displays." MRS Bulletin 21, no. 3 (1996): 39–48. http://dx.doi.org/10.1557/s0883769400036125.

Full text
Abstract:
The fabrication of thin-film-transistor (TFT) devices on a transparent substrate lies at the heart of active-matrix-liquid-crystal-display (AMLCD) technology. This is both good and bad. On one hand it is a difficult task to manufacture millions of intricate semiconductor devices reliably over such large display substrates. On the positive side, AMLCD technology can aspire to become much more than a “display” technology. The idea is as follows: It is possible for one to readily fabricate additional transistors to execute various electronic functions—those that would otherwise be handled by separate large-scale-integration (LSI) and very large-scale-integration (VLSI) circuits—on the periphery of the display. Since this can be done, in principle, with no—or a minimal number of—additional processing steps, substantial cost reduction is possible and significant value can be added to the final product.Doing so and doing it well can ultimately lead to “system-on-glass” products in which the entire electronic circuitry needed for a product is incorporated directly onto a glass substrate. This means that integrated active-matrix liquid-crystal displays (IAMLCDs) have the potential to bypass conventional Si-wafer-based products and may lead TFT technology to compete directly against Si-wafer-based monolithic integrated circuits.
APA, Harvard, Vancouver, ISO, and other styles
29

Shuto, Takanori, Keiichiro Iwanabe, Kazuhiro Noda, Seiya Nakai, and Tanemasa Asano. "Ultrasonic Bonding of Cone Bump for Integration of Large-Scale Integrated Circuits in Flexible Electronics." Japanese Journal of Applied Physics 52, no. 5S1 (2013): 05DB10. http://dx.doi.org/10.7567/jjap.52.05db10.

Full text
APA, Harvard, Vancouver, ISO, and other styles
30

Alharbi, Mohammed, Gerard Edwards, and Richard Stocker. "An Ultra-Energy-Efficient Reversible Quantum-Dot Cellular Automata 8:1 Multiplexer Circuit." Quantum Reports 6, no. 1 (2024): 41–57. http://dx.doi.org/10.3390/quantum6010004.

Full text
Abstract:
Energy efficiency considerations in terms of reduced power dissipation are a significant issue in the design of digital circuits for very large-scale integration (VLSI) systems. Quantum-dot cellular automata (QCA) is an emerging ultralow power dissipation approach, distinct from traditional, complementary metal-oxide semiconductor (CMOS) technology, for building digital computing circuits. Developing fully reversible QCA circuits has the potential to significantly reduce energy dissipation. Multiplexers are fundamental elements in the construction of useful digital circuits. In this paper, a novel, multilayer, fully reversible QCA 8:1 multiplexer circuit with ultralow energy dissipation is introduced. The power dissipation of the proposed multiplexer is simulated using the QCADesigner-E version 2.2 tool, describing the microscopic physical mechanisms underlying the QCA operation. The results show that the proposed reversible QCA 8:1 multiplexer consumes 89% less energy than the most energy-efficient 8:1 multiplexer circuit previously presented in the literature.
APA, Harvard, Vancouver, ISO, and other styles
31

Dai, Xiao, Jiang Wu, Zhicheng Qian, et al. "Ultra-smooth glassy graphene thin films for flexible transparent circuits." Science Advances 2, no. 11 (2016): e1601574. http://dx.doi.org/10.1126/sciadv.1601574.

Full text
Abstract:
Large-area graphene thin films are prized in flexible and transparent devices. We report on a type of glassy graphene that is in an intermediate state between glassy carbon and graphene and that has high crystallinity but curly lattice planes. A polymer-assisted approach is introduced to grow an ultra-smooth (roughness, <0.7 nm) glassy graphene thin film at the inch scale. Owing to the advantages inherited by the glassy graphene thin film from graphene and glassy carbon, the glassy graphene thin film exhibits conductivity, transparency, and flexibility comparable to those of graphene, as well as glassy carbon–like mechanical and chemical stability. Moreover, glassy graphene–based circuits are fabricated using a laser direct writing approach. The circuits are transferred to flexible substrates and are shown to perform reliably. The glassy graphene thin film should stimulate the application of flexible transparent conductive materials in integrated circuits.
APA, Harvard, Vancouver, ISO, and other styles
32

Dwivedi, V. K. "A Bird's‐Beak‐Free Sealed‐Interface Local Oxidation Technology for Submicron Ultra‐Large‐Scale Integrated Circuits." Journal of The Electrochemical Society 137, no. 8 (1990): 2586–88. http://dx.doi.org/10.1149/1.2086991.

Full text
APA, Harvard, Vancouver, ISO, and other styles
33

Pang, Zhenjiang, Hengchao Sun, Yan Guo, et al. "Research Advances of Porous Polyimide—Based Composites with Low Dielectric Constant." Polymers 15, no. 16 (2023): 3341. http://dx.doi.org/10.3390/polym15163341.

Full text
Abstract:
With the burgeoning of the microelectronics industry, in order to improve the transmission speed between chips in large-scale integrated circuits to meet the demands of high integration, it is necessary for interlayer insulation materials to possess a lower dielectric constant (k). Polyimide (PI) has been widely used as interlayer insulation materials for large-scale integrated circuits, and the exploration on reducing their dielectric constant has attracted extensive attention in recent years. In this work, porous PI-based composites with a low dielectric constant are mainly reviewed. The application of porous SiO2, graphene derivatives, polyoxometalates, polyhedral oligomeric silsesquioxane and hyperbranched polysiloxane in reducing the dielectric constant of PI is emphatically introduced. The key technical problems and challenges in the current research of porous polyimide materials are summarized, and the development prospect of low k polyimide is also expounded.
APA, Harvard, Vancouver, ISO, and other styles
34

Fan, Ya Ping. "Research of Ultra Precision Machining Technology." Applied Mechanics and Materials 687-691 (November 2014): 476–79. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.476.

Full text
Abstract:
Ultra-precision machining technology is adapt to the development of modern technology a new technology of mechanical processing, the new achievement of the development of the integrated application of the mechanical technology and modern electronic technology, measurement technology and computer technology in advanced control, testing method, etc., makes a further improve the precision of machining. At present the increasing maturity of the ultra precision machining, has formed a series, it include ultra precision cutting, super precision grinding and super precision grinding and super precision special processing, etc. Ultra-precision machining to high precision, high efficiency, large-scale, miniaturization, intelligent, process integration, the integration of online processing detection, such as green direction.
APA, Harvard, Vancouver, ISO, and other styles
35

Baklanov, Mikhail R., and Karen Maex. "Porous low dielectric constant materials for microelectronics." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 364, no. 1838 (2005): 201–15. http://dx.doi.org/10.1098/rsta.2005.1679.

Full text
Abstract:
Materials with a low dielectric constant are required as interlayer dielectrics for the on-chip interconnection of ultra-large-scale integration devices to provide high speed, low dynamic power dissipation and low cross-talk noise. The selection of chemical compounds with low polarizability and the introduction of porosity result in a reduced dielectric constant. Integration of such materials into microelectronic circuits, however, poses a number of challenges, as the materials must meet strict requirements in terms of properties and reliability. These issues are the subject of the present paper.
APA, Harvard, Vancouver, ISO, and other styles
36

TAKAO, Hidekuni, Nobuhiro TANAKA, Masanori SUGIURA, Kazuaki SAWADA, and Makoto ISHIDA. "423 Formation and Evaluation of Micro Fluidic Integrated Circuits by Surface Micromachining for Large Scale Integration." Proceedings of the JSME annual meeting 2008.8 (2008): 147–48. http://dx.doi.org/10.1299/jsmemecjo.2008.8.0_147.

Full text
APA, Harvard, Vancouver, ISO, and other styles
37

Chen, Zhifeng, Jiming Chen, Wenli Liao, Yuan Zhao, Jianhua Jiang, and Chengying Chen. "Progress on a Carbon Nanotube Field-Effect Transistor Integrated Circuit: State of the Art, Challenges, and Evolution." Micromachines 15, no. 7 (2024): 817. http://dx.doi.org/10.3390/mi15070817.

Full text
Abstract:
As the traditional silicon-based CMOS technology advances into the nanoscale stage, approaching its physical limits, the Carbon Nanotube Field-effect Transistor (CNTFET) is considered to be the most significant transistor technology beyond Moore’s era. The CNTFET has a quasi-one-dimensional structure so that the carrier can realize ballistic transport and has very high mobility. At the same time, a single CNTFET can integrate hundreds of nanowires as the conductive channels, enabling significant current transport capabilities even in low supply voltage, thereby providing a foundational basis for achieving nanoscale ultra-large-scale analog/logic circuits. This paper summarizes the development status of the CNTFET compact model and digital/analog/RF integrated circuits. The challenges faced by SPICE modeling and circuit design are analyzed. Meanwhile, solutions to these challenges and development trends of carbon-based transistors are discussed. Finally, the future application prospects of carbon-based integrated circuits are presented.
APA, Harvard, Vancouver, ISO, and other styles
38

Jeon, Yunchae, Donghyun Lee, and Hocheon Yoo. "Recent Advances in Metal-Oxide Thin-Film Transistors: Flexible/Stretchable Devices, Integrated Circuits, Biosensors, and Neuromorphic Applications." Coatings 12, no. 2 (2022): 204. http://dx.doi.org/10.3390/coatings12020204.

Full text
Abstract:
Thin-film transistors using metal oxides have been investigated extensively because of their high transparency, large area, and mass production of metal oxide semiconductors. Compatibility with conventional semiconductor processes, such as photolithography of the metal oxide offers the possibility to develop integrated circuits on a larger scale. In addition, combinations with other materials have enabled the development of sensor applications or neuromorphic devices in recent years. Here, this paper provides a timely overview of metal-oxide-based thin-film transistors focusing on emerging applications, including flexible/stretchable devices, integrated circuits, biosensors, and neuromorphic devices. This overview also revisits recent efforts on metal oxide-based thin-film transistors developed with high compatibility for integration to newly reported applications.
APA, Harvard, Vancouver, ISO, and other styles
39

Guo, Shan Shan, Yuan Yuan Jiang, Hao Zeng, Xiao Yong Wan, and Yong Jun Li. "Diffusion Bonding Performance of Copper Target for 300mm Integrated Circuit." Materials Science Forum 1035 (June 22, 2021): 692–97. http://dx.doi.org/10.4028/www.scientific.net/msf.1035.692.

Full text
Abstract:
Ultra-pure copper sputtering target is a key material widely used in large-scale integrated circuits with 90-28 nm feature size. The copper target for 300 mm integrated circuit requires a reliable diffusion bonding between the ultra-pure copper target and the copper alloy backplate. The bonding ratio and bonding strength of diffusion bonding should reach over 99% and 80 MPa respectively. In this paper, the ascendant structure of electron beam welding united diffusion bonding with high quality was designed. The ultra-pure copper target and the C18000 copper alloy backplate were machined to coordinating size, meanwhile the backplate underwent surface treatment of toothed/smooth, ion cleaning, magnetron sputtering coating, then the combination of target and the backplate was proceeded electron beam welding and diffusion bonding. Metallographic microscope, scanning electron microscope (SEM), mechanical tensile machine, C-scan flaw detector were used to analyze the bonding properties including interface microstructure, bonding strength and bonding ratio. The results show that the bonding ratio of copper target was above 99%, and the bonding strength was up to 80-160 MPa.
APA, Harvard, Vancouver, ISO, and other styles
40

Diao, Zhu, Vincent T. K. Sauer, and Wayne K. Hiebert. "Integrated On-Chip Nano-Optomechanical Systems." International Journal of High Speed Electronics and Systems 26, no. 01n02 (2017): 1740005. http://dx.doi.org/10.1142/s0129156417400055.

Full text
Abstract:
Recent developments in integrated on-chip nano-optomechanical systems are reviewed. Silicon-based nano-optomechanical devices are fabricated by a two-step process, where the first step is a foundry-enabled photonic circuits patterning and the second step involves in-house mechanical device release. We show theoretically that the enhanced responsivity of near-field optical transduction of mechanical displacement in on-chip nano-optomechanical systems originates from the finesse of the optical cavity to which the mechanical device couples. An enhancement in responsivity of more than two orders of magnitude has been observed when compared side-by-side with free-space interferometry readout. We further demonstrate two approaches to facilitate large-scale device integration, namely, wavelength-division multiplexing and frequency-division multiplexing. They are capable of significantly simplifying the design complexity for addressing individual nano-optomechanical devices embedded in a large array.
APA, Harvard, Vancouver, ISO, and other styles
41

Boychenko, Dmitry, Oleg Kalashnikov, Alexander Nikiforov, Anastasija Ulanova, Dmitry Bobrovsky, and Pavel Nekrasov. "Total ionizing dose effects and radiation testing of complex multifunctional VLSI devices." Facta universitatis - series: Electronics and Energetics 28, no. 1 (2015): 153–64. http://dx.doi.org/10.2298/fuee1501153b.

Full text
Abstract:
Total ionizing dose (TID) effects and radiation tests of complex multifunctional Very-large-scale integration (VLSI) integrated circuits (ICs) rise up some particularities as compared to conventional ?simple? ICs. The main difficulty is to organize informative and quick functional tests directly under irradiation. Functional tests approach specified for complex multifunctional VLSI devices is presented and the basic radiation test procedure is discussed in application to some typical examples.
APA, Harvard, Vancouver, ISO, and other styles
42

Madhura, S. "A Review on Low Power VLSI Design Models in Various Circuits." Journal of Electronics and Informatics 4, no. 2 (2022): 74–81. http://dx.doi.org/10.36548/jei.2022.2.002.

Full text
Abstract:
Low power design is one of the primary goals for any integrated circuits. Very Large-Scale Integration (VLSI) is a kind of Integrated Circuit (IC) that consists of hundreds and hundreds of transistor connection into a small chip. The communication and computer applications have grown very faster in the past decade due to the development of VLSI circuit design as microcontroller and microprocessors. However, still the research on VLSI are moving faster towards the scope of power and area minimization. The paper gives an overview about the recent methodologies that have been developed for the performance improvement of VLSI design and it shows the future directions of the areas that are to be concentrated on VLSI circuit design.
APA, Harvard, Vancouver, ISO, and other styles
43

Sharma, Vijay Kumar. "Design of Low Leakage PVT Variations Aware CMOS Bootstrapped Driver Circuit." Journal of Circuits, Systems and Computers 26, no. 09 (2017): 1750137. http://dx.doi.org/10.1142/s0218126617501377.

Full text
Abstract:
This paper describes a novel complementary metal oxide semiconductor (CMOS) bootstrapped driver circuit for driving large resistive capacitive (RC) loads. The proposed bootstrapped driver reduces the leakage as well as process, voltage and temperature (PVT) variations from the boosted nodes with higher switching speed. Very large scale integration (VLSI) designers need boosted output for the logic circuits which are operating in ultra-deep submicron regime under widespread use of low voltage. Proposed CMOS bootstrapped driver circuit is easy in design; built with minimum number of transistors and have high boosting efficiency with sharp output performance. Comparative evaluations with existing bootstrapped driver circuits are reported. Simulation results are derived by HSPICE tool with predictive technology model (PTM) bulk CMOS process fabrication at 32 nm technology node. The ability of large leakage reduction makes this driver superior as compared to active drivers. An average of 96.97% leakage current is saved at nominal ultra-low voltage of 0.15 V. Monte-Carlo analysis indicates that the proposed bootstrapped driver has less sensitivity of PVT variations. The power consumption and delay sensitivities are reduced by 10 × and 4.12 × as compared to conventional circuit.
APA, Harvard, Vancouver, ISO, and other styles
44

Beck, Anthony, Franziska Obst, Mathias Busek, et al. "Hydrogel Patterns in Microfluidic Devices by Do-It-Yourself UV-Photolithography Suitable for Very Large-Scale Integration." Micromachines 11, no. 5 (2020): 479. http://dx.doi.org/10.3390/mi11050479.

Full text
Abstract:
The interest in large-scale integrated (LSI) microfluidic systems that perform high-throughput biological and chemical laboratory investigations on a single chip is steadily growing. Such highly integrated Labs-on-a-Chip (LoC) provide fast analysis, high functionality, outstanding reproducibility at low cost per sample, and small demand of reagents. One LoC platform technology capable of LSI relies on specific intrinsically active polymers, the so-called stimuli-responsive hydrogels. Analogous to microelectronics, the active components of the chips can be realized by photolithographic micro-patterning of functional layers. The miniaturization potential and the integration degree of the microfluidic circuits depend on the capability of the photolithographic process to pattern hydrogel layers with high resolution, and they typically require expensive cleanroom equipment. Here, we propose, compare, and discuss a cost-efficient do-it-yourself (DIY) photolithographic set-up suitable to micro-pattern hydrogel-layers with a resolution as needed for very large-scale integrated (VLSI) microfluidics. The achievable structure dimensions are in the lower micrometer scale, down to a feature size of 20 µm with aspect ratios of 1:5 and maximum integration densities of 20,000 hydrogel patterns per cm². Furthermore, we demonstrate the effects of miniaturization on the efficiency of a hydrogel-based microreactor system by increasing the surface area to volume (SA:V) ratio of integrated bioactive hydrogels. We then determine and discuss a correlation between ultraviolet (UV) exposure time, cross-linking density of polymers, and the degree of immobilization of bioactive components.
APA, Harvard, Vancouver, ISO, and other styles
45

Asif, A., H. Richter, and J. N. Burghartz. "High-voltage (100 V) Chipfilm<sup>TM</sup> single-crystal silicon LDMOS transistor for integrated driver circuits in flexible displays." Advances in Radio Science 7 (May 19, 2009): 237–42. http://dx.doi.org/10.5194/ars-7-237-2009.

Full text
Abstract:
Abstract. System-in-Foil (SiF) is an emerging field of large-area polymer electronics that employs new materials such as conductive polymers and electrophoretic micro-capsules (E-Ink) along with ultra-thin and thus flexible chips. In flexible displays, the integration of gate and source drivers onto the flexible part increases the yield and enhances the reliability of the system. In this work we propose a high-voltage ChipfilmTM lateral diffused MOS transistor (LDMOS) structure on ultra-thin single-crystalline silicon chips. The fabrication process is compatible with CMOS standard processing. This LDMOS structure proves to be well suited for providing adequately large switching voltages in spite of the thin (&lt;10 μm) substrate. A breakdown voltage of more than 100 volts with drain-to-source saturation current Ids(sat)≈85 μA/μm for N-LDMOS and Ids(sat)≈20 μA/μm for P-LDMOS is predicted through process and device simulations.
APA, Harvard, Vancouver, ISO, and other styles
46

Mishra, Brijendra, Vivek Singh Kushwah, and Rishi Sharma. "MODELING OF HYBRID MOS FOR THE IMPLEMENTATION OF SWITCHED CAPACITOR FILTER USING SINGLE ELECTRON TRANSISTOR." International Journal of Engineering Technologies and Management Research 5, no. 2 (2020): 294–300. http://dx.doi.org/10.29121/ijetmr.v5.i2.2018.659.

Full text
Abstract:
In digital integrated circuit architectures, transistors serve as circuit switches to charge and discharge capacitors to the required logic voltage levels. A transistor is a three terminal semiconductor device used to amplify and switch electronic signals and electrical power. It has been observed that the Scaling down of electronic device sizes has been the fundamental strategy for improving the performance of ultra-large-scale integrated circuits (ULSIs). Metaloxide-semiconductor field-effect transistors (MOSFETs) have been the most prevalent electron devices for ULSI applications. A better device will be formed with the help of new technology, with high operating speed low and power consumption, which can be the future of electronics industry. A methodology for the electric simulation of MOS/SET hybrid circuits will be developed. As a result of this, a functional model for the single-electron transistor will obtain and Implement Switched Capacitor Filter with the help of designed hybrid MOS. The SET model can be easily coded in any hardware description language.
APA, Harvard, Vancouver, ISO, and other styles
47

Marsan-Loyer, C., D. Danovitch, and N. Boyer. "Addressing Flux Dip Challenges for 3D Integrated Large Die, Ultra-fine Pitch Interconnect." International Symposium on Microelectronics 2016, no. 1 (2016): 000054–59. http://dx.doi.org/10.4071/isom-2016-tp25.

Full text
Abstract:
Abstract The requirement for closely coupled, highly integrated circuits in the semiconductor industry has spawned alternative packaging innovations such as 2.5D/3D integration. The incredible potential of this alternative comes with great challenges, not the least of which is the unprecedented reduction in package interconnection pitch. Market acceptance of new fine-pitch microelectronic products is strongly dependent upon the development of flawless assembly processes that align with the traditional Moore-like expectation of higher performance without cost penalty. One such process is the application of flux to the interconnect surfaces in order to achieve effective joining. Insufficient flux quantity or flux activity can impede the formation of solid, reliable joints, while excessive quantities or activity can cause solder bridging or difficulties with downstream operations such as residue cleaning or underfill reinforcement. This delicate balance, already complex for traditional chip joining, is further challenged by the geometrical and spatial reductions imposed by pitch miniaturization, especially where large die, with over 100,000 interconnects, are concerned. This paper presents an overall development protocol to evolving a flux dipping operation to production-level thermocompression assembly of large die with ultra-fine pitch (60 μm) copper pillar interconnections. After reviewing the state of the art for fluxing technology and detailing the specific technical issues, we present and defend the chosen flux application approach with its corresponding parameters of interest. Physical and chemical characterization results for selected flux material candidates are reported in conjunction with an analysis of how their properties correlate to the flux dip application parameters. As part of this fundamental understanding, we investigate and report on flux dip coating behaviour and how it compares to other industrial dip coating applications. Finally, the results of process assembly experiments in a production-type environment are reviewed and discussed with respect to the previous characterizations. These experiments span downstream assembly process compatibility (i.e. cleaning and underfill) as well as product reliability.
APA, Harvard, Vancouver, ISO, and other styles
48

Castro, J. E., T. J. Steiner, L. Thiel, et al. "Expanding the quantum photonic toolbox in AlGaAsOI." APL Photonics 7, no. 9 (2022): 096103. http://dx.doi.org/10.1063/5.0098984.

Full text
Abstract:
Aluminum gallium arsenide-on-insulator (AlGaAsOI) exhibits large [Formula: see text] and [Formula: see text] optical nonlinearities, a wide tunable bandgap, low waveguide propagation loss, and a large thermo-optic coefficient, making it an exciting platform for integrated quantum photonics. With ultrabright sources of quantum light established in AlGaAsOI, the next step is to develop the critical building blocks for chip-scale quantum photonic circuits. Here we expand the quantum photonic toolbox for AlGaAsOI by demonstrating edge couplers, 3 dB splitters, tunable interferometers, and waveguide crossings with performance comparable to or exceeding silicon and silicon-nitride quantum photonic platforms. As a demonstration, we de-multiplex photonic qubits through an unbalanced interferometer, paving the route toward ultra-efficient and high-rate chip-scale demonstrations of photonic quantum computation and information applications.
APA, Harvard, Vancouver, ISO, and other styles
49

Sun, Chongjun, and Chao Ding. "Study on Calibration Method for Testing During Burn In equipment of integrated circuits." Journal of Physics: Conference Series 2029, no. 1 (2021): 012035. http://dx.doi.org/10.1088/1742-6596/2029/1/012035.

Full text
Abstract:
Abstract In order to implement Method 1015 of GJB 548B, TDBI(Testing During Burn In) technology of integrated circuit is widely used in the aging process of core VLSI(Very Large Scale Integration) which is included of FPGA, DSP, CPU and dedicated chips. Many models of TDBI equipment at home or abroad have been come into use. It is an important task to calibrate TDBI equipment in system level and ensure the traceability of its measurement value. At present, the calibration device of TDBI equipment has been successfully finalized and put into production, which has the advantages of convenient use and high cost performance. This paper mainly introduces the calibration method for TDBI equipment of integrated circuit from the aspects of the overall architecture design, signal adaptation design and calibration software design.
APA, Harvard, Vancouver, ISO, and other styles
50

IKEDA, SHOJI, HIDEO SATO, MICHIHIKO YAMANOUCHI, et al. "RECENT PROGRESS OF PERPENDICULAR ANISOTROPY MAGNETIC TUNNEL JUNCTIONS FOR NONVOLATILE VLSI." SPIN 02, no. 03 (2012): 1240003. http://dx.doi.org/10.1142/s2010324712400036.

Full text
Abstract:
We review recent developments in magnetic tunnel junctions with perpendicular easy axis (p-MTJs) for nonvolatile very large scale integrated circuits (VLSIs). So far, a number of material systems such as rare-earth/transition metal alloys, L10-ordered ( Co, Fe )– Pt alloys, Co /( Pd, Pt ) multilayers, and ferromagnetic-alloy/oxide stacks have been proposed as electrodes in p-MTJs. Among them, p-MTJs with single or double ferromagnetic-alloy/oxide stacks, particularly CoFeB–MgO , were shown to have high potential to satisfy major requirements for integration.
APA, Harvard, Vancouver, ISO, and other styles
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!