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Dissertations / Theses on the topic 'Integrated circuits Very large scale integration Design and construction Testing'

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Published: 4 June 2021

Last updated: 19 February 2022

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1

Ivanov, André. "Dynamic testibility measures and their use in ATPG." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63324.

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2

Draier, Benny. "Test vector generation and compaction for easily testable PLAs." Thesis, McGill University, 1988. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63970.

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3

Kim, Kwanghyun. "An expert system for self-testable hardware design." Diss., Virginia Polytechnic Institute and State University, 1989. http://hdl.handle.net/10919/54216.

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BIDES (A BIST Design Expert System) is an expert system for incorporating BIST into a digital circuit described with VHDL. BIDES modifies a circuit to produce a self-testable circuit by inserting BIST hardware such as pseudorandom pattern generators and signature analysis registers. In inserting BIST hardware, BIDES not only makes a circuit self-testable, but also incorporates the appropriate type of BIST structure so that a set of user-specified constraints on hardware overhead and testing time can be satisfied. This flexibility comes from the formulation of the BIST design problem as a searc

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4

Panda, Uma R. "An efficient single-latch scan-design scheme/." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63266.

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5

Venkatesan, Raguraman. "Multilevel interconnect architectures for gigascale integration (GSI)." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/13370.

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6

Chen, Ing-yi 1962. "Efficient reconfiguration by degradation in defect-tolerant VLSI arrays." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277195.

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This thesis addresses the problem of constructing a flawless subarray from a defective VLSI/WSI array consists of identical cells such as memory cells or processors. In contrast to the redundancy approach in which some cells are dedicated as spares, all the cells in the degradation approach are treated in a uniform way. Each cell can be either fault-free or defective and a subarray which contains no faulty cell is derived under constraints of switching and routing mechanisms. Although extensive literatures exist concerning spare allocation and reconfiguration in arrays with redundancy, little

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7

高雲龍 and Wan-lung Ko. "A new optimization model for VLSI placement." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1998. http://hub.hku.hk/bib/B29812938.

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8

Bishop, Gregory Raymond H. ""On stochastic modelling of very large scale integrated circuits : an investigation into the timing behaviour of microelectronic systems" /." Title page, contents and abstract only, 1993. http://web4.library.adelaide.edu.au/theses/09PH/09phb6222.pdf.

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9

Whipple, Thomas Driggs 1961. "Design and implementation of an integrated VLSI packaging support software environment." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277105.

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An interactive software shell has been developed which integrates several packaging simulation tools developed at the University of Arizona which are used to analyze electro-magnetic coupling between interconnects in an integrated circuit. This software shell uses experimental frames to manage this simulation process. Through the experimental frames, the model descriptions and the model inputs are separated, and input data is verified for correctness. This model/input separation allows several model variations to be tested based on several input variations. The results of these simulations are

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10

Haddadin, Baker. "Time domain space mapping optimization of digital interconnect circuits." Thesis, McGill University, 2009. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=116004.

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Microwave circuit design including the design of Interconnect circuits are proving to be a very hard and complex process where the use of CAD tools is becoming more essential to the reduction in design time and in providing more accurate results. Space mapping methods, the relatively new and very efficient way of optimization which are used in microwave filters and structures will be investigated in this thesis and applied to the time domain optimization of digital interconnects. The main advantage is that the optimization is driven using simpler models called coarse models that would approxim

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11

Boudreault, Yves 1959. "Design of a VLSI convolver for a robot vision system." Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=65342.

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12

袁志勤 and Chi-kan Yuen. "A double-track greedy algorithm for VLSI channel routing." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1997. http://hub.hku.hk/bib/B31220241.

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13

Dickinson, Alex. "Complexity management and modelling of VLSI systems." Title page, contents and abstract only, 1988. http://web4.library.adelaide.edu.au/theses/09PH/09phd553.pdf.

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14

Kim, Kwanghyun. "An interactive design rule checker for integrated circuit layout." Thesis, Virginia Polytechnic Institute and State University, 1985. http://hdl.handle.net/10919/50034.

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An implementation of an interactive design rule checker is described in this thesis. Corner-based design rule checking algorithm is used for the implementation. Due to the locality of checking mechanism of the corner-based algorithm, it is suitable for hierarchical and interactive local design rule checking. It also allows the various design rules to be specified very easily. Interactive operations are devised so that the design rule checker can be invoked from inside the layout editor. All the information about the violation, such as position, type of violation, and symbol definition name ar

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15

Morton, Shannon V. "Fast asynchronous VSLI circuit design techniques and their application to microprocessor design /." Title page, contents and abstract only, 1997. http://web4.library.adelaide.edu.au/theses/09PH/09phm891.pdf.

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16

Bagchi, Tanuj. "An Efficient Hybrid Heuristic and Probabilistic Model for the Gate Matrix Layout Problem in VLSI Design." Thesis, University of North Texas, 1993. https://digital.library.unt.edu/ark:/67531/metadc500878/.

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In this thesis, the gate matrix layout problem in VLSI design is considered where the goal is to minimize the number of tracks required to layout a given circuit and a taxonomy of approaches to its solution is presented. An efficient hybrid heuristic is also proposed for this combinatorial optimization problem, which is based on the combination of probabilistic hill-climbing technique and greedy method. This heuristic is tested experimentally with respect to four existing algorithms. As test cases, five benchmark problems from the literature as well as randomly generated problem instances are

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17

Park, Hoon. "Formal Modeling and Verification of Delay-Insensitive Circuits." PDXScholar, 2015. https://pdxscholar.library.pdx.edu/open_access_etds/2639.

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Einstein's relativity theory tells us that the notion of simultaneity can only be approximated for events distributed over space. As a result, the use of asynchronous techniques is unavoidable in systems larger than a certain physical size. Traditional design techniques that use global clocks face this barrier of scale already within the space of a modern microprocessor chip. The most common response by the chip industry for overcoming this barrier is to use Globally Asynchronous Locally Synchronous (GALS) design techniques. The circuits investigated in this thesis can be viewed as examples of

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18

Moon, Gyo Sik. "An Algorithm for the PLA Equivalence Problem." Thesis, University of North Texas, 1995. https://digital.library.unt.edu/ark:/67531/metadc278922/.

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The Programmable Logic Array (PLA) has been widely used in the design of VLSI circuits and systems because of its regularity, flexibility, and simplicity. The equivalence problem is typically to verify that the final description of a circuit is functionally equivalent to its initial description. Verifying the functional equivalence of two descriptions is equivalent to proving their logical equivalence. This problem of pure logic is essential to circuit design. The most widely used technique to solve the problem is based on Binary Decision Diagram or BDD, proposed by Bryant in 1986. Unfortunate

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19

Nain, Rajeev Kumar. "Floorplan Design and Yield Enhancement of 3-D Integrated Circuits." PDXScholar, 2011. https://pdxscholar.library.pdx.edu/open_access_etds/2810.

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We have developed a placement-aware 3-D floorplanning algorithm that enables additional wirelength reduction by planning for 3-D placement of logic gates in selected circuit modules during the floorplanning stage. Thus it also bridges the existing gap between 3-D floorplanning and 3-D placement. To reduce the solution space of 3-D floorplanning which is known to be an NP-hard problem, we derive a set of feasibility conditions on the topological representation of a floorplan. In addition, we have designed a fast module packing algorithm that satisfies a set of constraints for placement-aware 3-

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20

Johnson, Timothy E. "MOSSTAT An interactive static rule checker for MOS VLSI designs." Full text open access at:, 1986. http://content.ohsu.edu/u?/etd,109.

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21

Cooke, Bradly James. "S-parameter VLSI transmission line analysis." Diss., The University of Arizona, 1989. http://hdl.handle.net/10150/184876.

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This dissertation investigates the implementation of S-parameter based network techniques for the analysis of multiconductor, high speed VLSI integrated circuit and packaging interconnects. The S-parameters can be derived from three categories of input parameters: (1) lossy quasi-static R,L,C and G, (2) lossy frequency dependent (dispersive) R,L,C,G and (3) the propagation constants, Γ, the characteristic impedance, Z(c) and the conductor eigencurrents, I, derived from full wave analysis. The S-parameter network techniques developed allow for: the analysis of periodic waveform excitation, the

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22

Appleton, Samuel Scott. "Performance-directed design of asynchronous VLSI systems /." Title page, contents and abstract only, 1997. http://web4.library.adelaide.edu.au/theses/09PH/09pha651.pdf.

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23

Ale, Anil Kumar. "Comparison and Evaluation of Existing Analog Circuit Simulator using Sigma-Delta Modulator." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5422/.

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In the world of VLSI (very large scale integration) technology, there are many different types of circuit simulators that are used to design and predict the circuit behavior before actual fabrication of the circuit. In this thesis, I compared and evaluated existing circuit simulators by considering standard benchmark circuits. The circuit simulators which I evaluated and explored are Ngspice, Tclspice, Winspice (open source) and Spectre® (commercial). I also tested standard benchmarks using these circuit simulators and compared their outputs. The simulators are evaluated using design metrics i

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24

Battina, Brahmasree. "An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design." Thesis, University of North Texas, 2014. https://digital.library.unt.edu/ark:/67531/metadc799495/.

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Integrated Circuits (ICs) have a broad range of applications in healthcare, military, consumer electronics etc. The acronym VLSI stands for Very Large Scale Integration and is a process of making ICs by placing millions of transistors on a single chip. Because of advancements in VLSI design technologies, ICs are getting smaller, faster in speed and more efficient, making personal devices handy, and with more features. In this thesis work an interactive framework is designed in which the fundamental concepts of digital logic design and VLSI design such as logic gates, MOS transistors, combinati

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25

Ryu, Kyeong Keol. "Automated Bus Generation for Multi-processor SoC Design." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5076.

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In the design of a multi-processor System-on-a-Chip (SoC), the bus architecture typically comes to the forefront because the system performance is not dependent only on the speed of the Processing Elements (PEs) but also on the bus architecture in the system. An efficient bus architecture with effective arbitration for reducing contention on the bus plays an important role in maximizing performance. Therefore, among many issues of multi-processor SoC research, we focus on two issues related to the bus architecture in this dissertation. One issue is how to quickly and easily design an effici

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26

Zhang, Mingyang 1981. "Macromodeling and simulation of linear components characterized by measured parameters." Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=112589.

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Recently, microelectronics designs have reached extremely high operating frequencies as well as very small die and package sizes. This has made signal integrity an important bottleneck in the design process, and resulted in the inclusion of signal integrity simulation in the computer aided design flow. However, such simulations are often difficult because in many cases it is impossible to derive analytical models for certain passive elements, and the only available data are frequency-domain measurements or full-wave simulations. Furthermore, at such high frequencies these components are distri

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27

Nugent, Steven Paul. "A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC)." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6885.

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Future opportunities for gigascale integration will be governed by a hierarchy of theoretical and practical limits that can be codified as follows: fundamental, material, device, circuit, and system. An exponential increase in on-chip integration is driving System-on-Chip (SoC) methodologies as a dominant design solution for gigascale ICs. Therefore, a second generation generic systems simulator (GENESYS) is developed to address a need for rapid assessment of technology/architecture tradeoffs for multi-billion transistor SoCs while maintaining the depth of core modeling codified in the hiera

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28

Yang, Yun Ju 1980. "Impacto de técnicas de redução do consumo de energia no projeto de SoCs Multimedia." [s.n.], 2011. http://repositorio.unicamp.br/jspui/handle/REPOSIP/275743.

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Orientador: Guido Costa Souza de Araújo<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação<br>Made available in DSpace on 2018-08-19T00:08:02Z (GMT). No. of bitstreams: 1 Yang_YunJu_M.pdf: 3101962 bytes, checksum: 3711cbf9c4db60e5d2938d566db0d87c (MD5) Previous issue date: 2011<br>Resumo: A indústria de semicondutores sempre enfrentou fortes demandas em resolver problema de dissipação de calor e reduzir o consumo de energia em dispositivos. Esta tendência tem sido intensificada nos últimos anos com o movimento de sustentabilidade ambiental. A concepção cor

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29

Goshi, Sudheer. "Digital Fabric." PDXScholar, 2012. https://pdxscholar.library.pdx.edu/open_access_etds/115.

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Continuing advances with VLSI have enabled engineers to build high performance computer systems to solve complex problems. The real-world problems and tasks like pattern recognition, speech recognition, etc. still remain elusive to the most advanced computer systems today. Many advances in the science of computer design and technology are coming together to enable the creation of the next-generation computing machines to solve real-world problems, which the human brain does with ease. One such engineering advance is the field of neuromorphic engineering, which tries to establish closer links t

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30

Inampudi, Sivateja. "Teaching Fundamentals of Digital Logic Design and VLSI Design Using Computational Textiles." Thesis, University of North Texas, 2014. https://digital.library.unt.edu/ark:/67531/metadc699874/.

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This thesis presents teaching fundamentals of digital logic design and VLSI design for freshmen and even for high school students using e-textiles. This easily grabs attention of students as it is creative and interesting. Using e-textiles to project these concepts would be easily understood by students at young age. This involves stitching electronic circuits on a fabric using basic components like LEDs, push buttons and so on. The functioning of these circuits is programmed in Lilypad Arduino. By using this method, students get exposed to basic electronic concepts at early stage which eventu

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31

Rockliff, John E. (John Edward). "The implementation of testability strategies in a VLSI circuit." 1986. http://web4.library.adelaide.edu.au/theses/09ENS/09ensr683.pdf.

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32

"Design and test for timing uncertainty in VLSI circuits." 2012. http://library.cuhk.edu.hk/record=b5549444.

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由於特徵尺寸不斷縮小，集成電路在生產過程中的工藝偏差在運行環境中溫度和電壓等參數的波動以及在使用過程中的老化等效應越來越嚴重，導致芯片的時序行為出現很大的不確定性。多數情況下，芯片的關鍵路徑會不時出現時序錯誤。加入更多的時序餘量不是一種很好的解決方案，因為這種保守的設計方法會抵消工藝進步帶來的性能上的好處。這就為設計一個時序可靠的系統提出了極大的挑戰，其中的一些關鍵問題包括：(一)如何有效地分配有限的功率預算去優化那些正爆炸式增加的關鍵路徑的時序性能；(二)如何產生能夠捕捉準確的最壞情況時延的高品質測試向量；(三)為了能夠取得更好的功耗和性能上的平衡，我們將不得不允許芯片在使用過程中出現一些頻率很低的時序錯誤。隨之而來的問題是如何做到在線的檢錯和糾錯。<br>為了解決上述問題，我們首先發明了一種新的技術用於識別所謂的虛假路徑，該方法使我們能夠發現比傳統方法更多的虛假路徑。當將所提取的虛假路徑集成到靜態時序分析工具里以後，我們可以得到更為準確的時序分析結果，同時也能節省本來用於優化這些路徑的成本。接著，考慮到現有的延時自動向量生成(ATPG) 方法會產生功能模式下無法出現的測試向量，這種向量可能會造成測試過程中在被激活的路徑周圍出現過多(或過少)的電源噪聲(PSN) ，從而導致測試過度或者測試不足情況。為此，我們提出了一種新的偽功能ATPG工具。通過同時考慮功能約束以及電路的物理佈局

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33

Ramalingam, Anand 1979. "Analysis techniques for nanometer digital integrated circuits." Thesis, 2007. http://hdl.handle.net/2152/3661.

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As technology has scaled into nanometer regime, manufacturing variations have emerged as a major limiter of performance (timing) in VLSI circuits. Issues related to timing are addressed in the first part of the dissertation. Statistical Static Timing Analysis (SSTA) has been proposed to perform full-chip analysis of timing under uncertainty such as manufacturing variations. In this dissertation, we propose an efficient sparse-matrix framework for a path-based SSTA. In addition to an efficient framework for doing timing analysis, to improve the accuracy of the timing analysis one needs to addre

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34

Lai, Minghorng. "New algorithms for physical design of VLSI circuits." 2002. http://wwwlib.umi.com/cr/utexas/fullcit?p3099471.

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35

Choi, Youngmoon. "Parallel prefix adder design." Thesis, 2004. http://hdl.handle.net/2152/1300.

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36

"An incremental alternation placement algorithm for macrocell array design." Chinese University of Hong Kong, 1990. http://library.cuhk.edu.hk/record=b5886910.

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by Tsz Shing Cheung.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 1990.<br>Includes bibliographical references.<br>Chapter Section 1 --- Introduction --- p.2<br>Chapter 1.1 --- The Affinity Clustering Phase --- p.2<br>Chapter 1.2 --- The Alteration Phase --- p.3<br>Chapter 1.3 --- Floorplan of Macrocell Array --- p.3<br>Chapter 1.4 --- Chip Model --- p.4<br>Chapter 1.4.1 --- Location Representation --- p.4<br>Chapter 1.4.2 --- Interconnection Length Estimation --- p.6<br>Chapter 1.5 --- Cost Function Evaluation --- p.6<br>Chapter 1.5.1 --- Net-length Calculation --- p.6<br>Ch

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37

Croix, John Francis 1963. "Cell and interconnect timing analysis using waveforms." 2002. http://hdl.handle.net/2152/11193.

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38

Luo, Tao Ph D. "Nanometer VLSI placement and optimization for multi-objective design closure." Thesis, 2007. http://hdl.handle.net/2152/3688.

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39

Ren, Haoxing. "Incremental placement for modern VLSI design closure." Thesis, 2006. http://hdl.handle.net/2152/2626.

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40

"A novel asynchronous cell library for self-timed system design." Chinese University of Hong Kong, 1995. http://library.cuhk.edu.hk/record=b5888603.

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by Eva Yuk-Wah Pang.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 1995.<br>Includes bibliographical references (leaves 88-89).<br>ACKNOWLEDGEMETS<br>ABSTRACT<br>LIST OF FIGURES<br>LIST OF TABLES<br>Chapter CHAPTER1 --- INTRODUCTION<br>Chapter 1.1 --- Motivation --- p.1-1<br>Chapter 1.1.1 --- Problems with Synchronous Systems --- p.1-1<br>Chapter 1.1.2 --- The Advantages of Self-timed Systems --- p.1-2<br>Chapter 1.1.3 --- Self-Timed Cell Library --- p.1-3<br>Chapter 1.2 --- Overview of the Thesis --- p.1-5<br>Chapter CHAPTER2 --- BACKGROUND<br>Chapter 2.1 --- Introduction --- p.

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41

"Scalability and interconnection issues in floorplan design and floorplan representations." 2001. http://library.cuhk.edu.hk/record=b5890773.

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Yuen Wing-seung.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2001.<br>Includes bibliographical references (leaves [116]-[122]).<br>Abstracts in English and Chinese.<br>Abstract --- p.i<br>Acknowledgments --- p.iii<br>List of Figures --- p.viii<br>List of Tables --- p.xii<br>Chapter 1 --- Introduction --- p.1<br>Chapter 1.1 --- Motivations and Aims --- p.1<br>Chapter 1.2 --- Contributions --- p.3<br>Chapter 1.3 --- Dissertation Overview --- p.4<br>Chapter 2 --- Physical Design and Floorplanning in VLSI Circuits --- p.6<br>Chapter 2.1 --- VLSI Design Flow --- p.6<br>Chapter 2

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42

Rajaram, Anand Kumar. "Synthesis of variation tolerant clock distribution networks." 2008. http://hdl.handle.net/2152/18098.

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In the sub-65nm VLSI technology, the variation effects like manufacturing variation, power supply noise and temperature variation become very significant. As one of the most vital components in any synchronous VLSI chip, the Clock Distribution Network (CDN) is especially sensitive to these variations. The unwanted clock skews caused by the variation effects consume increasing proportion of the clock cycle, thereby limiting chip performance and yield. Thus, making the clock network variation-tolerant is a key objective in the chip designs of today. In this dissertation, we propose several techn

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43

"Reticle floorplanning and voltage island partitioning." 2006. http://library.cuhk.edu.hk/record=b5892947.

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Ching Lap Sze.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2006.<br>Includes bibliographical references (leaves 69-71).<br>Abstracts in English and Chinese.<br>Abstract --- p.i<br>Acknowledgement --- p.iv<br>Chapter 1 --- Introduction --- p.1<br>Chapter 1.1 --- Shuttle Mask --- p.2<br>Chapter 1.2 --- Voltage Island --- p.6<br>Chapter 1.3 --- Structure of the Thesis --- p.8<br>Chapter 2 --- Literature Review on Shuttle Mask Floorplanning --- p.9<br>Chapter 2.1 --- Introduction --- p.9<br>Chapter 2.1.1 --- Problem formulation --- p.10<br>Chapter 2.2 --- Slicing Floorplan ---

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44

Xu, Gang 1974. "Layout optimization algorithms vor VLSI design and manufacturing." Thesis, 2007. http://hdl.handle.net/2152/3362.

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As the feature size of the transistor shrinks into nanometer scale, it becomes a grand challenge for semiconductor manufacturers to achieve good manufacturability of integrated circuits cost-effectively. In this dissertation, we aim at layout optimization algorithms from both manufacturing and design perspectives to address problems in this grand challenge. Our work covers three topics in this research area: a redundant via enhanced maze routing algorithm for yield improvement, a shuttle mask floorplanner, and optimization of post-CMP topography variation. Existing methods for redundant via i

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45

"Optimal geometric design of VLSI interconnect networks by simulated annealing." Chinese University of Hong Kong, 1995. http://library.cuhk.edu.hk/record=b5888582.

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by Sau-yuen Wong.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 1995.<br>Includes bibliographical references (leaves 77-82).<br>Acknowledgement --- p.i<br>Abstract --- p.ii<br>List of Tables --- p.ii<br>List of Figures --- p.iv<br>Chapter 1 --- Introduction --- p.1<br>Chapter 2 --- Review of Previous Work --- p.4<br>Chapter 2.1 --- Optimization of Delay and Layout Design --- p.4<br>Chapter 2.2 --- Simulated Annealing --- p.8<br>Chapter 3 --- Definition of Circuit Model --- p.12<br>Chapter 4 --- Evaluation of Delay --- p.16<br>Chapter 4.1 --- RC-tree and Elmore Delay --- p.16

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46

Noonan, J. A. (John Anthony). "Investigations into methods and analysis of computer aided design of VLSI circuits." 1986. http://web4.library.adelaide.edu.au/theses/09ENS/09ensn817.pdf.

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47

"Clock routing for high performance microprocessor designs." 2011. http://library.cuhk.edu.hk/record=b5894819.

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Tian, Haitong.<br>Chinese abstract is on unnumbered page.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2011.<br>Includes bibliographical references (p. 65-74).<br>Abstracts in English and Chinese.<br>Abstract --- p.i<br>Acknowledgement --- p.iii<br>Chapter 1 --- Introduction --- p.1<br>Chapter 1.1 --- Motivations --- p.1<br>Chapter 1.2 --- Our Contributions --- p.2<br>Chapter 1.3 --- Organization of the Thesis --- p.3<br>Chapter 2 --- Background Study --- p.4<br>Chapter 2.1 --- Traditional Clock Routing Problem --- p.4<br>Chapter 2.2 --- Tree-Based Clock Routing Algorithms ---

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48

"Obstacle-avoiding rectilinear Steiner tree." 2009. http://library.cuhk.edu.hk/record=b5894012.

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Li, Liang.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2009.<br>Includes bibliographical references (leaves 57-61).<br>Abstract also in Chinese.<br>Abstract --- p.i<br>Acknowledgement --- p.iv<br>Chapter 1 --- Introduction --- p.1<br>Chapter 1.1 --- Background --- p.1<br>Chapter 1.1.1 --- Partitioning --- p.1<br>Chapter 1.1.2 --- Floorplanning and Placement --- p.2<br>Chapter 1.1.3 --- Routing --- p.2<br>Chapter 1.1.4 --- Compaction --- p.3<br>Chapter 1.2 --- Motivations --- p.3<br>Chapter 1.3 --- Problem Formulation --- p.4<br>Chapter 1.3.1 --- Properties of OARSMT --- p.

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49

"Delay driven multi-way circuit partitioning." 2003. http://library.cuhk.edu.hk/record=b5891508.

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Wong Sze Hon.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2003.<br>Includes bibliographical references (leaves 88-91).<br>Abstracts in English and Chinese.<br>Chapter 1 --- Introduction --- p.1<br>Chapter 1.1 --- Preliminaries --- p.1<br>Chapter 1.2 --- Motivations --- p.1<br>Chapter 1.3 --- Contributions --- p.3<br>Chapter 1.4 --- Organization of the Thesis --- p.4<br>Chapter 2 --- VLSI Physical Design Automation --- p.5<br>Chapter 2.1 --- Preliminaries --- p.5<br>Chapter 2.2 --- VLSI Design Cycle [1] --- p.6<br>Chapter 2.2.1 --- System Specification --- p.6<br>Chapter 2.2.

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50

"VLSI implementation of discrete cosine transform using a new asynchronous pipelined architecture." 2002. http://library.cuhk.edu.hk/record=b5891233.

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Lee Chi-wai.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.<br>Includes bibliographical references (leaves 191-196).<br>Abstracts in English and Chinese.<br>Abstract of this thesis entitled: --- p.i<br>摘要 --- p.iii<br>Acknowledgements --- p.v<br>Table of Contents --- p.vii<br>List of Tables --- p.x<br>List of Figures --- p.xi<br>Chapter Chapter1 --- Introduction --- p.1<br>Chapter 1.1 --- Synchronous Design --- p.1<br>Chapter 1.2 --- Asynchronous Design --- p.2<br>Chapter 1.3 --- Discrete Cosine Transform --- p.4<br>Chapter 1.4 --- Motivation --- p.5<br>Chapter 1.5 ---

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