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Dissertations / Theses on the topic 'Integrated circuits'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Загулов, Станіслав Русланович. "Flexible integrated circuits." Thesis, Київський національний університет технологій та дизайну, 2020. https://er.knutd.edu.ua/handle/123456789/15297.

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2

Pettazzi, Federico. "Integrated soliton circuits." Besançon, 2008. http://www.theses.fr/2008BESA2001.

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Dans ce travail de thèse nous abordons le développement de circuits optiques intégrés tri-dimensionnels (3-D), la technique pour induire ces guides est basée sur les solitons spatiaux photorefractifs. Les démonstrations expérimentales sont réalisées dans le niobate de lithum (LiNbO3) ce qui permet de bénéficier de l'excellente qualité optique de ce matériau associée à une forte réponse photoréfractive, Dans un premier chapitre, les principaus problèmes liés aux interconnections optiques sont identifiés et une solution exploitant les solitons spatiaux photorefractifs est proposée. Dans un deuxi

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3

Gustard, N. C. "Optimizes switched-capacitor filter circuits for integrated circuit realization." Thesis, University of Essex, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.294667.

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4

Kapur, Kishen Narain. "Mechanical and electrical characterization of IC leads during fatigue cycling." Diss., Online access via UMI:, 2009.

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Thesis (Ph. D.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Electrical and Computer Engineering, 2009.<br>Includes bibliographical references.

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5

Lee, Kyung Tek. "Crosstalk fault test generation and hierarchical timing verification in VLSI digital circuits /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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6

Fayed, Ayman Adel. "Adaptive techniques for analog and mixed signal integrated circuits." Connect to this title online, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1097519730.

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Thesis (Ph. D.)--Ohio State University, 2004.<br>Title from first page of PDF file. Document formatted into pages; contains xix, 232 p.; also includes graphics (some col.). Includes bibliographical references (p. 222-230).

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7

Bakir, Muhannad S. "Sea of Leads electrical-optical polymer pillar chip I/O interconnections for gigascale integration." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04082004-180010/unrestricted/bakir%5Fmuhannad%5Fs%5F200312%5Fphd.pdf.

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8

Qazi, Masood. "Circuit design for embedded memory in low-power integrated circuits." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/75645.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (p. 141-152).<br>This thesis explores the challenges for integrating embedded static random access memory (SRAM) and non-volatile memory-based on ferroelectric capacitor technology-into lowpower integrated circuits. First considered is the impact of process variation in deep-submicron technologies on SRAM, which must exhibit higher density and performance at increased levels of integration with every

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9

Paroski, Andrew John. "Deform a new approach for redistributing placements /." Diss., Online access via UMI:, 2006.

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10

Agnihotri, Ameya Ramesh. "Combinatorial optimization techniques for VLSI placement." Diss., Online access via UMI:, 2007.

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11

Micallef, Steven P. "Hierarchical testing of integrated circuits." Thesis, University of Oxford, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.291399.

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12

Dixon, James Edward. "Towards integrated scalable nanophotonic circuits." Thesis, University of Sheffield, 2017. http://etheses.whiterose.ac.uk/18282/.

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This thesis presents optical measurements used to explore nanophotonic circuits composed of III-V semiconductors with embedded quantum dots. The focus of this work is to investigate issues related to the scalability and performance of these structures. A technique to register the position of a quantum dot, relative to pre-fabricated registration markers, with the aid of a solid immersion lens, is developed. The variance in the repeatedly registered position of the quantum dot is shown to be significantly reduced as a result of the solid immersion lens, compared with positions registered withou

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13

Al, Bastami Anas Ibrahim. "Power monitoring in integrated circuits." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/92973.

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Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged from student-submitted PDF version of thesis.<br>Includes bibliographical references (pages 201-203).<br>Power monitoring is needed in most electrical systems, and is crucial for ensuring reliability in everything from industrial and telecom applications, to automotive and consumer electronics. Power monitoring of int

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14

Neto, Hugo Daniel Barbosa. "Packaging of photonic integrated circuits." Master's thesis, Universidade de Aveiro, 2017. http://hdl.handle.net/10773/23552.

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Mestrado em Engenharia Eletrónica e Telecomunicações<br>With the continuous evolution of optical communication systems, emerged a need for high-performance optoelectronic elements at lower costs. Photonic packaging plays a key role for the next-generation of optical devices. In this work a standard packaging design rules is described, covering both the electrical and optical-packaging exploring both active and passive adjusting techniques, as well as the thermal management of the photonic integrated circuit (PIC). First a process for fiber-to-chip coupling with custom made ball-lensed fibers

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15

Yang, Gang. "Compact Photonic Integrated Passive Circuits." Thesis, The University of Sydney, 2021. https://hdl.handle.net/2123/26958.

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Photonic Integrated Circuits (PICs) based on silicon photonics have received great interest due to the low loss caused by the high-refractive-index contrast and the complementary metal-oxide semiconductor compatibility. The need for high-density, high-yield, low-cost, low-power consumption, and large-scale on-chip photonic integration requires the technologies to further minimize the size while exhibiting high performance. Moreover, the fast development and expansion of silicon photonics devices for different applications and functionalities require effective design approaches to optimize the

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16

Leung, Lydia Lap Wai. "Low-loss on-chip interconnects for silicon integrated radio-frequency and microwave systems /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20LEUNG.

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17

Sekar, Deepak Chandra. "Optimal signal, power, clock and thermal interconnect networks for high-performance 2d and 3d integrated circuits." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26562.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Meindl, James; Committee Co-Chair: Davis, Jeffrey; Committee Member: Callen, Russell; Committee Member: Gaylord, Thomas; Committee Member: Kohl, Paul; Committee Member: Mukhopadhyay, Saibal. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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18

Chomicz, Thecla F. "A methodology for NMOS VLSI manufacturing : from design to test at the Rochester Institute of Technology /." Online version of thesis, 1990. http://hdl.handle.net/1850/11314.

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19

Saxena, Nina. "Scalable solutions to specification and verification of large designs /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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20

Lee, Man. "Design, fabrication and characterization of an integrated micro heat pipe system /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?MECH%202002%20LEE.

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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002.<br>Includes bibliographical references (leaves 74-77). Also available in electronic version. Access restricted to campus users.

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21

Shi, Shichang. "Lithography : friendly routing via forbidden pitch avoidance /." View the Table of Contents & Abstract, 2004. http://sunzi.lib.hku.hk/hkuto/record/B30469636.

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22

Huang, Kuan Hsiang Nick, and 黃冠翔. "Electromagnetic compatibility modeling for integrated circuits." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2014. http://hdl.handle.net/10722/206335.

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The integrated circuit (IC) packaging electromagnetic compatibility (EMC)/signal integrity (SI)/power integrity (PI) problems have been broadly attested. But IC packaging electromagnetic interference (EMI) was seldom addressed. Because the electromagnetic emission from IC packagings becomes more critical as the data rate of digital system continues increasing. Its working mechanism and modeling technology are very important. In this thesis, EM emission behaviors of IC packaging are systematically studied for the first time. It was never seen from other literatures. The fundamental principle

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23

Senthinathan, Ramesh 1961. "ELECTRICAL CHARACTERISTICS OF INTEGRATED CIRCUIT PACKAGES." Thesis, The University of Arizona, 1987. http://hdl.handle.net/10150/276425.

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24

Marinins, Aleksandrs. "Polymer Components for Photonic Integrated Circuits." Doctoral thesis, KTH, Skolan för teknikvetenskap (SCI), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-219556.

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Optical polymers are a subject of research and industry implementation for many decades. Optical polymers are inexpensive, easy to process and flexible enough to meet a broad range of application-specific requirements. These advantages allow a development of cost-efficient polymer photonic integrated circuits for on-chip optical communications. However, low refractive index contrast between core and cladding limits light confinement in a core and, consequently, integrated polymer device miniaturization. Also, polymers lack active functionality like light emission, amplification, modulation, et

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25

Lötter, Pierre. "Parameter extraction of superconducting integrated circuits /." Link to online version, 2006. http://hdl.handle.net/10019/569.

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26

Smith, Nathan. "Substrate integrated waveguide circuits and systems." Thesis, McGill University, 2010. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=92388.

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This thesis investigates substrate integrated waveguide (SIW) based interconnects, components, and systems. SIWs are high performance broadband interconnects with excellent immunity to electromagnetic interference and suitable for use in microwave and millimetre-wave electronics, as well as wideband systems. They are very low-cost in comparison to the classic milled metallic waveguides as they may be developed using inexpensive printed circuit board (PCB) fabrication techniques. In this thesis, the interconnect design is studied by investigating the modes supported by SIW using fullwave simula

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27

Ward, Elizabeth May. "Advanced technologies for optoelectronic integrated circuits." Thesis, Imperial College London, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.404887.

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28

Alipour, Motaallem Seyed Payam. "Reconfigurable integrated photonic circuits on silicon." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51792.

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Integrated optics as a platform for signal processing offers significant benefits such as large bandwidth, low loss, and a potentially high degree of reconfigurability. Silicon (Si) has unique advantages as a material platform for integration, as well as properties such as a strong thermo-optic mechanism that allows for the realization of highly reconfigurable photonic systems. Chapter 1 is devoted to the discussion of these advantages, and Chapter 2 provides the theoretical background for the analysis of integrated Si-photonic devices. The thermo-optic property of Si, while proving extremely

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29

ITALO, ADRIANA MARIA RAPOSO. "ART & NATURE: PHILOSOPHICAL INTEGRATED CIRCUITS." PONTIFÍCIA UNIVERSIDADE CATÓLICA DO RIO DE JANEIRO, 2004. http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=5262@1.

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CONSELHO NACIONAL DE DESENVOLVIMENTO CIENTÍFICO E TECNOLÓGICO<br>Minha pesquisa tem por objetivo examinar a suposta distinção entre arte e natureza no interior de uma análise crítica da chamada crise de fundamentos. Isto é, a crise do projeto fundacionista moderno, a rejeição pós-moderna à metafísica em geral e à idéia de fundamento em particular, suas relações com as rupturas impostas pelas novas tecnologias e suas conseqüências na visão de mundo e de humanidade. Arte e natureza não constituem domínios fundamentalmente distintos, ou ainda, não há heterogeneidade ontológica entre aqui

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30

Parish, Simon James. "Behavioural synthesis of analogue integrated circuits." Thesis, University of Birmingham, 2010. http://etheses.bham.ac.uk//id/eprint/549/.

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Automatic synthesis of analogue circuits remains a very manually intensive task despite huge strides in the field of Electronic Design Automation (EDA) in recent decades. Genetic Algorithms (GAs) are biologically inspired search algorithms which have previously shown some promise in this field. Their ability to form the basis of a practically useful synthesis system is investigated. A GA-based experimental synthesis system is implemented, which employs a Genetic Programming (GP) style encoding scheme based on tree structures, and a novel fitness function based on pole-zero analysis. The system

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31

Lim, Daihyun 1976. "Extracting secret keys from integrated circuits." Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/18059.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.<br>Includes bibliographical references (p. 117-119).<br>Modern cryptographic protocols are based on the premise that only authorized participants can obtain secret keys and access to information systems. However, various kinds of tampering methods have been devised to extract secret keys from widely fielded conditional access systems such as smartcards and ATMs. As a solution, Arbiter-based Physical Unclonable Functions (PUFs) are proposed. This technique exploits statistical delay

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32

Hoang, Lan H. (Lan Hoang). "Improving mechanical reliability of integrated circuits." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/41344.

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33

Mumtaz, Asim. "Power integrated circuits for photovoltaic applications." Thesis, University of Cambridge, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.616250.

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34

Lam, S. C. K. "Gallium arsenide bit-serial integrated circuits." Thesis, University of Edinburgh, 1990. http://hdl.handle.net/1842/11027.

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Bit-Serial architecture and Gallium Arsenide have essentially been mutually exclusive fields in the past. Digital Gallium Arsenide integrated circuits have increasingly adopted the conventional approach of bit-parallel structures that do not always suit the properties and problems of the technology. This thesis proposes an alternative by using a least significant bit first bit-serial architecture, and presents a group of 'cells' designed for signal processing applications. The main features of the cells include the extensive use of pseudo-dynamic latches for pipelining, modularity, and program

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35

Lotter, Pierre. "Parameter extraction of superconducting integrated circuits." Thesis, Stellenbosch : University of Stellenbosch, 2006. http://hdl.handle.net/10019.1/1652.

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Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2006.<br>Integrated circuits are expensive to manufacture and it is important to verify the correct operation of a circuit before fabrication. Efficient, though accurate, parameter extraction of post-layout designs are required for estimation of circuit success rates. This thesis discusses electrical netlist and fast parameter extraction techniques suited for both intraand inter-gate connections. This includes the use of extraction windows and look-up tables (LUTs) for accurate inductance and capacitance

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36

Gohil, Nikhil N. "Design of DPA-Resistant Integrated Circuits." University of Cincinnati / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1516622822794541.

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37

Figueiredo, Mónica Jorge Carvalho de. "Synchronisation in high-performance integrated circuits." Doctoral thesis, Universidade de Aveiro, 2012. http://hdl.handle.net/10773/8798.

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Doutoramento em Engenharia Electrotécnica<br>A distribui ção de um sinal relógio, com elevada precisão espacial (baixo skew) e temporal (baixo jitter ), em sistemas sí ncronos de alta velocidade tem-se revelado uma tarefa cada vez mais demorada e complexa devido ao escalonamento da tecnologia. Com a diminuição das dimensões dos dispositivos e a integração crescente de mais funcionalidades nos Circuitos Integrados (CIs), a precisão associada as transições do sinal de relógio tem sido cada vez mais afectada por varia ções de processo, tensão e temperatura. Esta tese aborda o problema da inc

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38

Rodrigues, Carla Iolanda Costa. "Photonic integrated circuits for NG-EPON." Master's thesis, Universidade de Aveiro, 2016. http://hdl.handle.net/10773/22732.

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Mestrado em Engenharia Electrónica e Telecomunicações<br>Along with privacy and security, the growth of demand from the consumer for higher bandwidth presents one of the most important modern challenges in telecommunications infrastructures. The researchers were encouraged to nd not only e cient but also the economically viable solutions capable of meeting the growing needs of the consumer. Optical communications are the way that can accompany this growth. The Passive Optical Network (PON) is an architecture that shares the ber bandwidth among several users. There has been a constant

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39

Smuk, Jeffrey William Carleton University Dissertation Engineering Electrical. "Hybrid semiconductive/superconductive microwave integrated circuits." Ottawa, 1991.

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40

Bernard, Martino. "Lightwave circuits for integrated Silicon Photonics." Doctoral thesis, Università degli studi di Trento, 2017. https://hdl.handle.net/11572/368818.

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This thesis work covers scientific and technological advancements in integrated silicon photonics circuits aimed at developing an All-On-Chip device for quantum photonics experiments. The work has been carried out within the framework of project SiQuro, where the Silicon-On-Insulator platform is chosen to integrate all the components of an optical bench necessary for a quantum experiment into a single chip. The problem of generating photon pairs have been addressed by studying second order polarisation effects in strained silicon with the aim to realize a bright photon pairs source based on Sp

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41

Bernard, Martino. "Lightwave circuits for integrated Silicon Photonics." Doctoral thesis, University of Trento, 2017. http://eprints-phd.biblio.unitn.it/2067/1/Disclaimer_thesis_signed.pdf.

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This thesis work covers scientific and technological advancements in integrated silicon photonics circuits aimed at developing an All-On-Chip device for quantum photonics experiments. The work has been carried out within the framework of project SiQuro, where the Silicon-On-Insulator platform is chosen to integrate all the components of an optical bench necessary for a quantum experiment into a single chip. The problem of generating photon pairs have been addressed by studying second order polarisation effects in strained silicon with the aim to realize a bright photon pairs source based on Sp

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42

Gope, Dipanjan. "Integral equation based fast electromagnetic solvers for circuit applications /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6116.

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43

Hamanaka, Cristian Otsuka. "Projeto de circuitos para geração de tensão de referência em sistemas receptores/transmissores RF." Universidade de São Paulo, 2007. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-09012008-164614/.

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Este trabalho consiste no projeto de uma Fonte de Tensão de Referência CMOS com coeficiente de temperatura inferior a 50 ppm/ºC. Esta fonte deve ser aplicada em receptores/transmissores de radio freqüência mas pode também ser utilizada em qualquer sistema analógico. A tecnologia utilizada foi a CMOS 0,35 µm da AMS (Austria Micro Systems) com quatro níveis de metal e dois de silício policristalino. A fonte de tensão implementada é do tipo Bandgap e utiliza dispositivos MOS em inversão fraca, um transistor bipolar parasitário e resistores de silício policristalino de alta resistividade. No circ

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44

Rahimi, Kambiz. "Adaptive-delay sequential circuits /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/5907.

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45

Ahmed, Mohammad Abrar. "Early Layout Design Exploration in TSV-based 3D Integrated Circuits." PDXScholar, 2017. https://pdxscholar.library.pdx.edu/open_access_etds/3617.

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Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realizatio

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46

Kantipudi, Kalyana R. "Minimizing N-detect tests for combinational circuits." Auburn, Ala., 2007. http://repo.lib.auburn.edu/2007%20Spring%20Theses/KANTIPUDI_KALYANA_27.pdf.

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47

Özkaramanli, Hüseyin Mehmet. "Distributed circuits in integrated circuits : signal integrity, crosstalk and delay in VLSI /." Thesis, Connect to Dissertations & Theses @ Tufts University, 1995.

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Thesis (Ph.D.)--Tufts University, 1995.<br>Submitted to the Dept. of Electrical Engineering. Includes bibliographical references (leaves 237-253). Access restricted to members of the Tufts University community. Also available via the World Wide Web;

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48

Cronquist, Darren C. "Reconfigurable pipelined datapaths /." Thesis, Connect to this title online; UW restricted, 1999. http://hdl.handle.net/1773/6988.

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49

Hu, Fei. "Process variation-resistant dynamic power optimization of VLSI circuits." Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Fall/Dissertation/HU_FEI_35.pdf.

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50

Gore, Kapil Suhling J. C. Jaeger Richard C. "Vibration analysis of test chips with integrated piezoresistive stress sensors." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Summer/Theses/GORE_KAPIL_36.pdf.

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