Dissertations / Theses on the topic 'Integrated front-ends'

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.<br>Committee Chair: Laskar, Joy; Committee Member: Chakraborty, Sudipto; Committee Member: Chang, Jae Joon; Committee Member: Divan, Deepakraj; Committee Member: Kornegay, Kevin; Committee Member: Tentzeris, Emmanouil. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.<br>Includes bibliographical references (p. 177-186).<br>SiGe wideband 77-GHz and 94-GHz front end receivers with integrated antennas for passive imaging have been designed and characterized. These front end systems exhibit wideband performance with the highest gain and lowest noise figures reported thus far for silicon-based systems in the 77-GHz and 94-GHz frequency regimes, to the best of the author's knowledge. These systems each comprise a fully differential integrated antenna, LNA, and a double-balanced mixer. A separate 77-GHz front end also features an on-chip 72-GHz cross-coupled VCO. The 77-GHz front end receiver achieves 46 dB max conversion gain, 6.5-10 dB noise figure (NF), output-referred 1dB compression point of +2 dBm and DC power dissipation (PDc) of 122 mW. The 94-GHz receiver achieves 47 dB max conversion gain, 7-12.5 dB NF, and PDC of 120 mW. The antenna performance yields gains of 10-13 dB over 70-100 GHz, with greater than 90% efficiency. The integrated antenna exhibits a typical loss of 0.5-1 dB, or 80-90% efficiency, and a worst-case radiation loss of _ -2 dB (efficiency = 63%). These reported results exceed published on-chip antenna performance, which typically achieve < 10% efficiency. Antenna loss degrades receiver noise figure and gain, yielding a less viable receiver. The individual design, co-design and integration of each element making up the RF front end collectively contribute to the overall high performance of these front end receivers. The 77-GHz LNA achieves 4.9-6.0 dB NF, 18-26 dB gain, and S11, S22 of -13.0 and -12.8 dB, respectively. The mixer achieves 12-14 dB NF, 20-26 dB conversion gain and -26dBm IP1dB (input-referred). The VCO achieves output power from -2 to 0 dBm with phase noise of -93 dBc/Hz at 72 GHz. The 94-GHz LNA achieves 22-dB max gain, 7.0 dB NF, -25 dB and -10 dB S11 and S22, respectively. This LNA also exhibits very wideband performance, achieving >10 dB gain from 40-100 GHz.<br>by Johnna Dawn Powell.<br>Ph.D.

The objective of the research presented in this dissertation is to explore the achievable dynamic range limits in high-performance RF front-ends designed using SiGe HBTs, with a focus on complementary (npn + pnp) SiGe technologies. The performance requirements of RF front-ends are high gain, high linearity, low dc power consumption, very low noise figure, and compactness. The research presented in this dissertation shows that all of these requirements can easily be met by using complementary SiGe HBTs. Thus, a strong case is made in favor of using SiGe technologies for designing high dynamic range RF front-ends. The contributions from this research are summarized as follows: 1. The first-ever comparison study and comprehensive analysis of small-signal linearity (IIP3) for npn and pnp SiGe HBTs on SOI. 2. A novel comparison of large-signal robustness of npn and pnp SiGe HBTs for use in high-performance RF front-ends. 3. A systematic and rigorous comparison of SiGe HBT compact models for high-fidelity distortion modeling. 4. The first-ever feasibility study of using weakly-saturated SiGe HBTs for use in severely power constrained RF front-ends. 5. A novel X-band Low Noise Amplifier (LNA) using weakly-saturated SiGe HBTs. 6. Design and comprehensive analysis of RF switches with enhanced large-signal linearity. 7. Development of novel methods to reduce crosstalk noise in mixed-signal circuits and the first-ever analysis of crosstalk noise across temperature. 8. Design of a very high-linearity cellular band quadrature modulator for use in base-station applications using first-generation complementary SiGe HBTs.

<p>The explosive development of wireless communication services creates a demand for more flexible and cost-effective communication systems that offer higher data rates. The obvious trend towards small-size and ultra low power systems, in combination with the ever increasing number of applications integrated in a single portable device, tightens the design constraints at hardware and software level. The integration of current mobile systems with the third generation systems exemplifies and emphasizes the need of monolithic multi-band transceivers. A long term goal is a software defined radio, where several communication standards and applications are embedded and reconfigured by software. This motivates the need for highly flexible and reconfigurable analog radio frequency (RF) circuits that can be fully integrated in standard low-cost complementary metal-oxide-semiconductor (CMOS) technologies.</p><p>In this thesis, the Voltage-Controlled Oscillator (VCO), one of the main challenging RF circuits within a transceiver, is investigated for today’s and future communication systems. The contributions from this work may be divided into two parts. The first part exploits the possibility and design related issues of wide-band reconfigurable integrated VCOs in CMOS technologies. Aspects such as frequency tuning, power dissipation and phase noise performance are studied and design oriented techniques for wide-band circuit solutions are proposed. For demonstration of these investigations several fully functional wide-band multi-GHz VCOs are implemented and characterized in a 0.18µm CMOS technology.</p><p>The second part of the thesis concerns theoretical analysis of phase noise in VCOs. Due to the complex process of conversion from component noise to phase noise, computer aided methods or advanced circuit simulators are usually used for evaluation and prediction of phase noise. As a consequence, the fundamental properties of different noise sources and their impact on phase noise in commonly adopted VCO topologies have so far not been completely described. This in turn makes the optimization process of integrated VCOs a very complex task. To aid the design and to provide a deeper understanding of the phase noise mechanism, a new approach based on a linear time-variant model is proposed in this work. The theory allows for derivation of analytic expressions for phase noise, thereby, providing excellent insight on how to minimize and optimize phase noise in oscillators as a function of circuit related parameters. Moreover, it enables a fair performance comparison of different oscillator topologies in order to ascertain which structure is most suitable depending on the application of interest. The proposed method is verified with very good agreement against both advanced circuit simulations and measurements in CMOS and bipolar technologies. As a final contribution, using the knowledge gained from the theoretical analysis, a fully integrated 0.35µm CMOS VCO with superior phase noise performance and power dissipation is demonstrated.</p>

The objective of the proposed research is to present a compact system-on-package (SOP)-based passive front-end solution for millimeter-wave wireless communication/sensor applications, that consists of fully integrated three dimensional (3D) cavity filters/duplexers and antenna. The presented concept is applied to the design, fabrication and testing of V-band transceiver front-end modules using multilayer low temperature co-fired (LTCC) technology. The millimeter-wave front-end module is the foundation of 60 GHz (V-band) wireless systems for short-range multimedia applications, such as high-speed internet access, video streaming and content download. Its integration poses stringent challenges in terms of high performance, large number of embedded passive components, low power consumption, low interference between integrated components and compactness. To overcome these major challenges, a high level of integration of embedded passive functions using low-cost and high-performance materials that can be laminated in 3D, such as the multilayer LTCC, is significantly critical in the module-level design. In this work, various compact and high-performance passive building blocks have been developed in both microstrip and cavity configurations and their integration, enabling a complete passives integration solution for 3D low-cost wireless millimeter-wave front-end modules. It is worthy to note that most of the designs implemented comes away with novel ideas and is presented as the first extensive state-of-art components, entirely validated by measured data at 60 GHz bands.

The investigation of liquid crystal polymer (LCP) technology to function as a low-cost next-generation organic platform for designs up to millimeter-wave frequencies has been performed. Prior to this research, the electrical performance of LCP had been characterized only with the implementation of standard transmission lines and resonators. In this research, a wide variety of passive functions have been developed on LCP technology and characterized for the first time. Specifically, we present the development of patch antenna arrays for remote sensing applications, the performance of compact low-pass and band-pass filters up to millimeter-wave frequencies, and the integration of passive elements for X-band and V-band transceiver systems. First, dual-frequency/dual-polarization antenna arrays have been developed on multilayer LCP technology and have been integrated with micro-electro-mechanical-system (MEMS) switches to achieve real-time polarization reconfigurability. These arrays are conformal, efficient and have all the features desirable for applications that require space deployment. Second, a wide variety of filters with different physical and functional characteristics have been implemented on both single and multilayer LCP technology. These filters can be classified based on the filter type (low-pass/band-pass), the resonators used (single-mode/dual-mode), the response characteristics (symmetric/asymmetric), and the structure of the filter (modular/non-modular). Last, examples of integrated modules for use in transceiver systems are presented. This part of the research involves the development of duplexers, radiating elements, as well as their integration. The duplexers themselves are realized by integrating a set of band-pass filters and matching networks. The characterization of the individual components, and of the integrated system are included. This research has resulted in a thorough understanding of LCP's electrical performance and its multilayer lamination capabilities pertaining to its functioning as a material platform for integrated microwave systems. Novel passive prototypes that can take advantage of such multilayer capabilities have been developed.

博士<br>國立成功大學<br>電腦與通信工程研究所<br>106<br>This dissertation covers two main research topics. The first main research topic is to study the injection locking enhancement technique in CMOS injection-locked frequency divider (ILFD), which includes the dual-band operation of 30 GHz divide-by-three and 50 GHz divide-by-five ILFD. The ILFD can be applied to the proposed 28 GHz and 47 GHz frequency bands of the 5G mobile communication. The second main topic is to study the injection pulling mitigation technique in CMOS LC voltage-controlled Oscillator using a novel honeycomb-shaped planar inductor. The design of a divide-by-three frequency divider operating at 30 GHz with an injection- switched cross-coupled pair (IS-CPP) technique to enhance the locking range is reported in Chapter 2. A wider locking range as well as a lower operation voltage can be achieved because of this newly proposed topology. The divider is implemented in a 90 nm standard CMOS process. The total locking range of the divider core is 4.5 GHz with a power consumption of 2.85 mW from a supply voltage of 0.5 V. The total power consumption of the buffers is 2.65 mW from a supply voltage of 1.0 V. The measured output phase noise is -141 dBc/Hz at 1 MHz offset when the input referred signal with a phase noise of -131 dBc/Hz at 1 MHz offset from 30 GHz. The phase-noise difference of 10 dB is close to the theoretical value of 9.5 dB for division-by-three. The total chip size is 0.48 mm2 and the divider core size is only about 0.14 mm2. A CMOS 30 GHz divide-by-three ILFD using the IS-CCP technique can also operate at a divide-by-5 mode. The related experimental results to demonstrate the extra capability of the proposed divider as a 50 GHz divide-by-five ILFD. The total locking range of 2.4 GHz is available at 50 GHz with a total dc power dissipation of 5.5 mW. The measured output phase noise of -143 dBc/Hz is obtained from an input signal of -127 dBc/Hz at 1 MHz offset from 50 GHz. This divider can be applied to a millimeter-wave PLL design for 47 GHz radio band applications, which include the newly proposed frequency band for the 5G mobile communication. The last part of the dissertation presents the injection pulling mitigation technique applied to a voltage controlled oscillator (VCO) using a novel honeycomb-shaped planar inductor. Due to the twisted routes of the sub-coils in the proposed inductor, the interference caused by a nearby electromagnetic noise source can be compensated and reduced. By using a 0.18-μm standard CMOS process, the proposed honeycomb-shaped planar inductor and a conventional single-turn spiral inductor in a similar size are integrated into two respective VCO test chips. The injection pulling behaviors of these two oscillators are studied and compared. The experimental results show that the VCO integrated with the proposed honeycomb-shaped planar inductor can significantly mitigate the injection pulling phenomenon as compared to the VCO integrated with a conventional single-turn inductor in a similar size. In this study, the enhancement of mitigation over 15 dB can be achieved.

碩士<br>國立清華大學<br>電子工程研究所<br>100<br>Along with the improvement of technology, people realized the importance and indispensability of high data rate in communications. The Optical Fiber Communication provides the good properties of high bandwidth interface without the problems seen in electrical interface, and therefore the Optical Fiber Communication System plays an important role in modern data transmission. This thesis can be divided into two parts. One is the design of the analog front-end in a 3.125 Gb/s optical receiver, fabricated in TSMC 0.18μm CMOS technology. The designed optical receiver front-end circuit utilizes high performance differential active Miller capacitor (DAMC) circuits to replace the off-chip capacitors so as to achieve an area-efficient design. The fully integrated design can also avoid off-chip noise interference. The measured results show that it the circuit achieves high precise crossing points and minimal dc offset, at a bit error rate (BER) of 10-12 using the 231-1 pseudo-random bit sequence pattern. The achieved transimpedance gain, power consumption and chip area are 108.02dBΩ, 43.2mW and 0.53mm × 0.61mm, respectively. The results show superior performance when compared with the figures in other works. The other part of the thesis is the design of high responsivity photodetector, implemented through TSMC 0.18μm SiGe BiCMOS process. The responsivity of photodetector is improved by the properties of SiGe heterojunction and phototransistor and which achieves a measured high value of 75 A/W under a 750nm wavelength light.

Η πληθώρα των εφαρμογών που μπορεί να εξυπηρετήσει η τεχνολογία Υπερευρείας Ζώνης (UWB), από τα ασύρματα προσωπικά δίκτυα υψηλών ταχυτήτων, μέχρι τα ασύρματα δίκτυα αισθητήρων με δυνατότητες ακριβούς εντοπισμού θέσης, και τα ασύρματα δίκτυα ιατρικών αισθητήρων, έχει προκαλέσει έντονο ερευνητικό ενδιαφέρον γύρω από τις υλοποιήσεις UWB συστημάτων. Η ασυνήθιστα μεγάλη περιοχή συχνοτήτων που έχει ανατεθεί στο UWB, από τα 3.1-10.6 GHz, επιτρέπει την επίτευξη υψηλών ταχυτήτων με απλά σχήματα διαμόρφωσης, ωστόσο, λόγω της διαμοίρασης του φάσματος με τις υφιστάμενες τεχνολογίες ασύρματης δικτύωσης, οι UWB εκπομπές πρέπει να περιορίζονται σε ισχύ κάτω από το κατώφλι των -41.3 dBm/MHz, ικανοποιώντας πολύ αυστηρές μάσκες εκπομπής που εισάγουν έντονες προκλήσεις στη σχεδίαση των πομπών. Η υλοποίηση αναδιατάξιμων UWB πομπών σε σύγχρονες CMOS τεχνολογίες, με υψηλή φασματική ευελιξία, ταχύτητα και ποιότητα διαμόρφωσης, καθώς και με χαμηλή κατανάλωση, αποτέλεσε το αντικείμενο της συγκεκριμένης διατριβής. Υιοθετώντας την αρχιτεκτονική Multi-Band Impulse-Radio (MB-IR) σε συνδυασμό με την τεχνική Direct Sequence BPSK, η έρευνα προσανατολίστηκε προς την ανάπτυξη καινοτόμων μονάδων βασικής ζώνης, με στόχο την ενεργειακά αποδοτική αντιστροφή Γκαουσιανών μορφοποιημένων παλμών υψηλής ποιότητας φάσματος και διάρκειας μικρότερης ακόμα και από 1 nsec. Προς αυτή την κατεύθυνση, αναπτύχθηκε μια καινοτόμα γεννήτρια Γκαουσιανών παλμών με πολύ χαμηλούς πλευρικούς λοβούς στο φάσμα, τυπικά κάτω από -40 dB, ώστε να υποστηρίζονται οι αυστηρότερες μάσκες εκπομπής ή και μελλοντικές. Η σχεδίασης της προτεινόμενης γεννήτριας είχε ως κριτήριο την ευέλικτη ρύθμιση της διάρκειας των παραγόμενων παλμών, και αξιοποίησε τη χαρακτηριστική μεταφοράς τάσης ενός ωμικά φορτωμένου, ασύμμετρου CMOS αντιστροφέα. Η γεννήτρια βασίζεται κυρίως σε ψηφιακά κυκλώματα πολύ χαμηλής τάσης και, σε σύγκριση με τις υφιστάμενες υλοποιήσεις, παρουσιάζει σημαντικό προβάδισμα στον τομέα της ταχύτητας, καθώς και στο πλάτος εξόδου, η μεγάλη τιμή του οποίου χαλαρώνει σημαντικά τη σχεδίαση του RF front end. Η γεννήτρια μελετήθηκε διεξοδικά, διεξήχθη ανάλυση κλιμάκωσης, έγινε εξαγωγή σχεδιαστικών εξισώσεων και αναπτύχθηκαν εργαλεία λογισμικού για την αυτοματοποιημένη σχεδίασή της. Για περαιτέρω αύξηση της ταχύτητας των παλμικών σημάτων εφαρμόσθηκε ειδική σχεδίαση, η οποία αντιπραγματεύεται την ταχύτητα με το επίπεδο των λοβών του φάσματος. Για την αποδοτική BSPK διαμόρφωση των Γκαουσιανών παλμών αναπτύχθηκε ειδική τοπολογία “Μεταγωγής Σήματος Πυροδότησης Πλήρους Ισορροπίας με Up-Conversion”. Η τοπολογία αυτή, σε αντίθεση με τις ανταγωνιστικές τοπολογίες, αποφεύγει την αντιστροφή του παλμού με αναλογικά κυκλώματα υψηλής κατανάλωσης, αλλά και την αναλογική μεταγωγή, καθώς η διαμόρφωση λαμβάνει χώρα πριν από την παραγωγή των παλμών. Παράλληλα, επιτυγχάνονται υψηλοί ρυθμοί, καθώς και υψηλή ποιότητα διαμόρφωσης λόγω των ισορροπημένων μονοπατιών της τοπολογίας. Η γεννήτρια μαζί με το διαμορφωτή αποτελούν τις καινοτόμες παρεμβάσεις στη μονάδα Βασικής Ζώνης του προτεινόμενου πομπού. Για την ολοκλήρωση της λειτουργικότητας του πομπού, αναπτύχθηκε ένα RF front end, το οποίο αποτελείται από έναν διπλά ισορροπημένο μίκτη, έναν LO buffer, ένα μετατροπέα διαφορικού σήματος σε απλό, και έναν ενισχυτή ισχύος, ο οποίος είναι προσαρμοσμένος στα 50 Ohms, χωρίς να απαιτεί κανένα εξωτερικό στοιχείο. Το RF front end ολοκληρώθηκε μαζί με τη μονάδα βασικής ζώνης, και ο ολοκληρωμένος πομπός κατασκευάστηκε σε τεχνολογία CMOS 130 nm. Το ολοκληρωμένο προσαρτήθηκε στην RF πλακέτα συστήματος με την τεχνική Chip on Board. Για την επιτυχία του συστήματος με την πρώτη προσπάθεια έγινε συσχεδίαση σε επίπεδο IC-Package-PCB, δίνοντας ιδιαίτερη έμφαση στα ζητήματα Signal/Power Integrity. Ο πομπός παρουσίασε την υψηλότερη ταχύτητα από τις ανταγωνιστικές MB-IR UWB υλοποιήσεις, ίση με 1.5 Gbps, με αντίστοιχη ενεργειακή αποδοτικότητα 21 pJoule/bit και μέτρο διανυσματικού σφάλματος 5.5%. Ο πομπός βελτίωσε τους πλευρικούς λοβούς στο φάσμα περισσότερο από 10 dB, ενώ η διατριβή, εκμεταλλευόμενη την αναδιαταξιμότητα του πομπού, παρουσιάζει, επιπλέον, τις πρώτες μετρήσεις σε ταχύτητες εκατοντάδων Mbps για ικανοποίηση της χαμηλής ζώνης της πρόσφατα θεσμοθετημένης, και εξαιρετικά αυστηρής, ευρωπαϊκής μάσκας εκπομπής.<br>The multitude of applications that Ultra-Wideband (UWB) technology can serve, from high-speed Wireless Personal Area Networks, to Wireless Sensor Networks with precision Geolocation abilities, and Wireless Medical Networks, has attracted intense research interest in the implementation of UWB systems. The unusually wide range of frequencies assigned to UWB, from 3.1-10.6 GHz, allows UWB systems employing low order modulation schemes to enjoy high throughput at low power consumption. However, since UWB shares the spectrum with existing wireless networking technologies, UWB emissions must be limited to a power spectral density below the threshold of -41.3 dBm/MHz, satisfying very stringent emission masks and introducing great challenges in the design of UWB transmitters. The subject of this thesis is the design of low power, fully integrated, reconfigurable CMOS UWB transmitters, with high spectral flexibility, high speed and high modulation quality. Adopting the Multi-Band Impulse-Radio architecture, in conjunction with the Direct Sequence BPSK modulation, the research focused on the development of a baseband unit, able to precisely invert Gaussian shaped, subnanosecond pulses. The key contributions of this thesis are a CMOS Gaussian Pulse Generator and a BSPK modulation topology, which jointly constitute the proposed baseband unit. The Pulse Generator (PG) is based on non-linear shaping, so as to facilitate the configurability of the output pulse duration, and exploits the voltage transfer characteristic of a Resistive Loaded Asymmetrical CMOS Inverter, which results in spectral sidelobes typically better than -40 dB. The PG incorporates mostly-digital low voltage circuits, while the MOSFET devices that undertake the pulse shaping avoid exclusive operation in weak inversion, in contrast to previous implementations. Consequently, the proposed CMOS PG is able to support higher throughput, as well as higher output amplitude, which relaxes considerably the design of the RF front end. This thesis presents a systematic design procedure and a scaling analysis of the non-linear pulse shaper. Moreover, in order to further increase the speed, a special PRF boost technique is proposed, which trades off speed and spectral efficiency for the spectral sidelobes level. Regarding the BPSK modulator, this work introduces the “Trigger Switching Fully Balanced Up-Conversion” topology, which avoids the use of power-hungry and distortion-prone analog circuits for the accurate inversion of the subnanosecond shaped pulses, as well as avoids the application of analog waveform switching to the baseband pulses, since the baseband modulation takes place before the generation of the pulses. The digital nature of the switching lends itself to high data rates, while the balanced paths of the topology ensure high modulation quality with minimal design effort. Wafer probing measurements confirmed the high performance of the baseband unit. The functionality of the transmitter was completed by the development of an RF front end which consists of a double balanced mixer, an LO buffer, a differential to single-ended (DtoSE) converter, and a power amplifier which is ready to drive a 50 Ohms load without requiring any off-chip components. The integrated transmitter, which incorporates the proposed baseband unit and the RF front end, was fabricated in 130 nm CMOS technology. The transmitter RFIC was directly attached to the system RF PCB using the Chip-on-Board packaging option. The First-Pass success of the system was ensured by paying particular attention to Signal/Power Integrity issues and following an IC-Package-PCB co-design procedure. The transmitter was measured up to 1.5 Gbps, which, to the author’s knowledge, was the highest speed amongst the competitive Multi-Band Impulse-Radio UWB implementations in the literature. The corresponding energy efficiency was 21 pJoule/bit and the Error Vector Magnitude (EVM) 5.5%, while the proposed transmitter improved the spectral sidelobes by over 10 dB. Exploiting the reconfigurability of the transmitter, this thesis presents the first measurements at multi-Mbps speeds that completely meet the final version of the European spectrum emission mask.