Journal articles: 'Integrated Passive Devices IPD'

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Liu, Kai, YongTaek Lee, HyunTai Kim, Gwang Kim, and Billy Ahn. "RF System in Packages (SiP) using Integrated Passive Devices." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (January 1, 2011): 001977–95. http://dx.doi.org/10.4071/2011dpc-wp43.

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Passive components are indispensible parts used in System in Packages (SiP) for various functions, such as decoupling, biasing, resonating, filtering, matching, transforming, etc. Making passive components embedded inside laminate substrates is limited on passive density. SMD solutions are by far the most popular approaches in the industry, and may still be dominant for some times. As high integration and high performance have become a trend in the packaging solutions, integrated passive device (IPD) technology shows some unique features, which helps to achieve these goals, especially for RF packages. In the IPD process, low-loss substrate material is used, and therefore high-Q inductors can be built. In addition, thin-film IPD process has finer pitch feature and better tolerance control than other commonly available ones, such as PCB and LTCC technologies, which may yield very repeatable electrical performance, and provide packages of high integration. Several cases of study will be presented and here are some highlights of them. In case one, a most straightforward SiP approach is presented using QFN package, where several dies (including IPD dies) are implemented side-by-side. This approach may give fast developing cycle times. But importantly, wire-bonding models have big impact on performance from RF packaging, and should be obtained accurately for designs. Another case of study is a stack-die package, where inter-die coupling/cross talk could be a big issue as far as electrical performance is concerned. Placement of some critical parts, such as coils in IPD and in VCO, should be investigated very carefully in design phases. This leads to a concept of ‘IC/IPD/package’ co-design. Finally, a hybrid SiP package solution, where an IPD die is embedded in a mold compound along side with a RF power amplifier die, is presented. This approach (so called ‘eWLB’ packaging), results in the shortest interconnection between dies to dies and dies to balls. With the benefit from both the IPD process and the eWLB process (where low-loss mold materials are used), this approach may lead to high electrical performance and small form-factor at the same time.

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Prashant, Meenakshi, Seung Wook Yoon, GeunSik Kim, Kai Liu, and Flynn Carson. "Advanced SiP Packaging Technologies of IPD for Mobile Applications." Journal of Microelectronics and Electronic Packaging 7, no. 4 (October 1, 2010): 223–27. http://dx.doi.org/10.4071/imaps.267.

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Integrated passive device (IPD) technology was originally developed as a way to replace bulky discrete passive components, but it is now gaining popularity in ESD/EMI protection applications, as well as in RF, high-brightness LED silicon submounts, and digital and mixed-signal devices. IPD is a device realized by resistors, inductors, capacitors, filters, and so on, for electrical functions such as matching and transforming, among others. Passive devices essentially optimize overall device performance. The key benefits offered by IPDs, as compared with LTCC and laminate-embedded passive devices, are primarily a smaller form factor and higher performance. IPDs are finding applications wherever it is desirable to reduce space on the application board or to reduce cost at the system level.

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Lee, Ki-Hun, Eun-Seong Kim, Jun-Ge Liang, and Nam-Young Kim. "Design and Realization of a Compact High-Frequency Band-Pass Filter with Low Insertion Loss Based on a Combination of a Circular-Shaped Spiral Inductor, Spiral Capacitor and Interdigital Capacitor." Electronics 7, no. 9 (September 12, 2018): 195. http://dx.doi.org/10.3390/electronics7090195.

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In this study, the proposed bandpass filter (BPF) connects an interdigital and a spiral capacitor in series between the two symmetrical halves of a circular intertwined spiral inductor. For the mass production of devices and to achieve a higher accuracy and a better performance compared with other passive technologies, we used integrated passive device (IPD) technology. IPD has been widely used to realize compact BPFs and achieve the abovementioned. The center frequency of the proposed BPF is 1.96 GHz, and the return loss, insertion loss and transmission zero are 26.77 dB, 0.27 dB and 38.12 dB, respectively. The overall dimensions of BPFs manufactured using IPD technology are 984 × 800 μ m 2 , which is advantageous for miniaturization and integration.

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Liu, Kai, YongTaek Lee, HyunTai Kim, Gwang Kim, Guruprasad Badakere, Yaojian Lin, and Billy Ahn. "Passive Device Integration from Silicon Technology." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (January 1, 2010): 001967–89. http://dx.doi.org/10.4071/2010dpc-wp36.

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Passive components are indispensible parts used in electronics circuits for various functions, such decoupling, biasing, resonating, filtering, matching, transforming, etc. These passive components can be made on chips, or in PCBs, or in SMDs. SOC (system-on-chip) solutions where all passives are implemented may be long-term goals, but suffer high cost and long development cycle times at the time being. Making passive components embedded inside laminate substrates is limited on passive density. SMD solutions are by far the most popular approaches in the industry, and may still be dominant for some times. Passive components consume 70%–80% area of an electric package in a SiP solution, and therefore it is a great deal to reduce the area of passive components, in order to reduce the size of entire package. We have developed an IPD (integrated passive device) process from silicon technology to make these passive components of high-Q performance, preferably to be used in RF packages. Low-loss substrate material is used in this process, and thick Cu layer is used for high-Q inductors. From this process, we can make capacitors in 330pF/mm sq density, and the Q-factor is around 30–35 peak for a 3nH–5 nH inductor. Most importantly, the thin-film IPD process has better tolerance control than other commonly available ones, such as PCB and LTCC technologies, which may results in very repeatable electrical performance, and provides packages in high integration. For a passive function block, using BPF (band-pass-filter) as an example, an IPD filter is typically two times smaller in X-Y size and half thinner in Z-height. This makes such IPD very suitable to be integrated in a SiP package. Using some case studies (individual IPD and chip-scale-module-package), we will present how high integration can be achieved, and where are the right spots to use IPD approaches other than SAW, or SMD, or LTCC solutions for RF SiP applications.

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Bunel, C., J.-R. Tenailleau, F. Voiron, S. Borel, and A. Lefevre. "Integrated Passive Devices and TSV, a disruptive technology for miniaturization." International Symposium on Microelectronics 2013, no. 1 (January 1, 2013): 000794–98. http://dx.doi.org/10.4071/isom-2013-thp12.

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The 3D Silicon technology of IPDiA is a disruptive technology for miniaturization adopted by the best players in the Medical and Industrial segments for its outstanding performance and reliability demonstrated in harsh environments. The high density capacitors with multiple metal-insulator-metal (MIM) layer stacks in 3D structures reaching 250nF/mm2 already in production for several years is at the forefront of the research program where CEA-Leti and IPDiA are jointly providing innovative platforms for customers who want to combine these capacitors with Through Silicon Vias in order to demonstrate new technological concepts. The via last approach selected by IPDIA allows large possibility of integration combining TSV with active or passive devices such as High-density trench capacitors, MIM capacitors, Resistors, High-Q inductors or Zener diodes. In this paper, the interaction between TSV and IPD will be studied. Emphasis will be placed on the robustness of the 3D trench capacitor technology. Examples of applications using chip-to-chip interconnections through a passive TSV interposer in a 3D IC integration system-in-package (SiP) will be illustrated.

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Park, Yun-Mook, Jun-Kyu Lee, Byung-Jin Park, Byeung-Gee Kim, Jung-Won Lee, and In-Soo Kang. "Development on Silicon module with Cu-filled TSV and Integrated Passive Devices." International Symposium on Microelectronics 2010, no. 1 (January 1, 2010): 000385–91. http://dx.doi.org/10.4071/isom-2010-wa1-paper6.

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In recent years, market demands on more functionality, smaller form factor and higher speed is becoming strong increasingly. In order to come up with those, many new technologies are emerging in the market. Among them, TSV and IPD are key enabling technology to meet market demands because TSV interconnection can provide wider bandwidth and high transmission speed due to vertical one compared to wire bonding technology and IPD can provide higher performance, more area saving to be assembled and small form factor compared to discrete passive components. In this work, we have developed the silicon module with Cu filled TSV and LPF [Low Pass Filter] in combination with Inductor and MIM Capacitor integrated at the surface of silicon interposer. And also have made very small form factor package with less than 0.8mm in thickness including 2 chips mounted side by side at the silicon interposer. In order to make silicon module with Cu filled TSV, we have evaluated and optimized via etch, thin-film deposition and via filling process which characterized a high uniformity via etch, good step-coverage and void-free at 200um in depth and 65um in TSV diameter at wafer-level. Furthermore, the IL [Insertion loss] of 0.14dB and 0.11dB for 3rd order filter and 5th order filter at 2.4 GHz respectively was achieved through both front-end process capable of high uniformity insulator deposition and back-end process capable of forming thick Cu RDL [Redistribution]. A good matching between measured value and simulated one using 3D simulator was achieved. We are currently running component reliability tests for Preconditioning, TC, HTS and 85%/85. So test results will be discussed and submitted at the full manuscript.

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Liu, Kai, YongTaek Lee, HyunTai Kim, and MaPhooPwint Hlaing. "Mobile Device Passive Integration from Wafer Process." International Symposium on Microelectronics 2011, no. 1 (January 1, 2011): 000878–86. http://dx.doi.org/10.4071/isom-2011-tha1-paper1.

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In this paper, we present some passive components made from silicon substrate technology (Integrated Passive Device process) and integration schemes using these components for RF applications. RF decoupling capacitors from this process are characterized on ESR and ESL performance. Functional blocks (filters, baluns, diplexers, matching, etc) made from the IPD process, have shown good electrical performance with small form-factor features. The thin profiles from the IPDs make them very suitable to be used inside laminate and QFN packages. System-in-Packages or multiple-chip-modules using IPD approaches may have significant size reduction. The low profiles and the small form-factors of the IPDs result in less cross-talk between the IPDs and their nearby components (chips, SMDs, and routing traces, etc), and therefore it is easier to maintain signal integrity for packages.

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Zhu, Bao-Hua, Nam-Young Kim, Zhi-Ji Wang, and Eun-Seong Kim. "On-Chip Miniaturized Bandpass Filter Using GaAs-Based Integrated Passive Device Technology For L-Band Application." Materials 12, no. 18 (September 19, 2019): 3045. http://dx.doi.org/10.3390/ma12183045.

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In this work, a miniaturized bandpass filter (BPF) constructed of two spiral intertwined inductors and a central capacitor, with several interdigital structures, was designed and fabricated using integrated passive device (IPD) technology on a GaAs wafer. Five air-bridge structures were introduced to enhance the mutual inductive effect and form the differential geometry of the outer inductors. In addition, the design of the differential inductor combined with the centrally embedded capacitor results in a compact construction with the overall size of 0.037λ0 × 0.019λ0 (1537.7 × 800 μm2) where λ0 is the wavelength of the central frequency. For the accuracy evolution of the equivalent circuit, the frequency-dependent lumped elements of the proposed BPF was analyzed and modeled through the segment method, mutual inductance approach, and simulated scattering parameters (S-parameters). Afterward, the BPF was fabricated using GaAs-based IPD technology and a 16-step manufacture flow was accounted for in detail. Finally, the fabricated BPF was wire-bonded with Au wires and packaged onto a printed circuit board for radio-frequency performance measurements. The measured results indicate that the implemented BPF possesses a center frequency operating at 2 GHz with the insertion losses of 0.38 dB and the return losses of 40 dB, respectively, and an ultrawide passband was achieved with a 3-dB fraction bandwidth of 72.53%, as well. In addition, a transmission zero is located at 5.32 GHz. Moreover, the variation of the resonant frequency with different inductor turns and metal thicknesses was analyzed through the simulation results, demonstrating good controllability of the proposed BPF.

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Lau, J. H., C. J. Zhan, P. J. Tzeng, C. K. Lee, M. J. Dai, H. C. Chien, Y. L. Chao, et al. "Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300 mm Multi-Project Wafer (MPW)." Journal of Microelectronics and Electronic Packaging 8, no. 4 (October 1, 2011): 171–78. http://dx.doi.org/10.4071/imaps.306.

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The feasibility of a 3D IC integration SiP has been demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) interposer with an RDL (redistribution layer) on both sides, IPD (integrated passive devices), and SS (stress sensors). This interposer is used to support (with microbumps) a stack of four memory chips with TSVs, one thermal chip with heater and one mechanical chip with SS, and is then overmolded on its top side for pick and place purposes. The interposer's bottom side is attached to an organic substrate (with ordinary lead-free solder bumps), which is lead-free solder-balled on a PCB (printed circuit board). Key enabling technologies such as TSV etching, chemical mechanical polishing (CMP), thin-wafer handling, thermal management, and microbumping, assembly, and reliability are highlighted.

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Lau, J. H., C.-J. Zhan, P.-J. Tzeng, C.-K. Lee, M.-J. Dai, H.-C. Chien, Y.-L. Chao, et al. "Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300mm Multi-Project Wafer (MPW)." International Symposium on Microelectronics 2011, no. 1 (January 1, 2011): 000446–54. http://dx.doi.org/10.4071/isom-2011-wa1-paper1.

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The feasibility of a 3D IC integration SiP has been demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) interposer with RDL (redistribution layer) on both sides, IPD (integrated passive devices) and SS (stress sensors). This interposer is used to support (with microbumps) a stack of four memory chips with TSVs, one thermal chip with heater and one mechanical chip with SS, and then overmolded on its top side for pick and place purposes. The interposer’s bottom-side is attached to an organic substrate (with ordinary lead-free solder bumps), which is lead-free solder-balled on a PCB (printed circuit board). Key enabling technologies such as TSV etching, chemical mechanical polishing (CMP), thin-wafer handling, thermal management, and microbumping, assembly and reliability are highlighted.

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Quan, Chun-He, Zhi-Ji Wang, Jong-Chul Lee, Eun-Seong Kim, and Nam-Young Kim. "A Highly Selective and Compact Bandpass Filter with a Circular Spiral Inductor and an Embedded Capacitor Structure Using an Integrated Passive Device Technology on a GaAs Substrate." Electronics 8, no. 1 (January 9, 2019): 73. http://dx.doi.org/10.3390/electronics8010073.

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As one of the most commonly used devices in microwave systems, bandpass filters (BPFs) directly affect the performance of these systems. Among the processes for manufacturing filters, integrated passive device (IPD) technology provides high practicality and accuracy. Thus, to comply with latest development trends, a resonator-based bandpass filter with a high selectivity and a compact size, fabricated on a gallium arsenide (GaAs) substrate is developed. An embedded capacitor is connected between the ends of two divisions in a circular spiral inductor, which is intertwined to reduce its size to 0.024 λg × 0.013 λg with minimal loss, and along with the capacitor, it generates a center frequency of 1.35 GHz. The strong coupling between the two ports of the filter results in high selectivity, to reduce noise interference. The insertion loss and return loss are 0.26 dB and 25.6 dB, respectively, thus facilitating accurate signal propagation. The filter was tested to verify its high performance in several aspects, and measurement results showed good agreement with the simulation results.

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Hsiao, Chih-Ying, Yang-Chih Huang, and Tzong-Lin Wu. "An Ultra-Compact Common-Mode Bandstop Filter With Modified-T Circuits in Integrated Passive Device (IPD) Process." IEEE Transactions on Microwave Theory and Techniques 63, no. 11 (November 2015): 3624–31. http://dx.doi.org/10.1109/tmtt.2015.2481412.

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Takano, Takamasa, Satoru Kuramochi, and Hobie Yun. "3D IPD on Thru Glass Via Substrate using panel Manufacturing Technology." International Symposium on Microelectronics 2017, no. 1 (October 1, 2017): 000097–102. http://dx.doi.org/10.4071/isom-2017-tp41_060.

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Abstract As electronic products become smaller and thinner with increasing number of functions, the demand for high density and high integration becomes stronger. Glass has many properties that make it an ideal substrate for high integration substrate such as; ultra high resistivity, adjustable thermal expansion (CTE) high modulus, low dielectric constant, low dielectric loss and manufacturability with large panel sizes. Multi-bands with carrier aggregation, Wi-Fi/GPS coexistence, and LTE-U make RF front end more and more complicated. 3D IPD (integrated passive devices) on Glass substrate technology could be advantage solution include reducing power consumption and small form factor. This paper presents a demonstration of 3D RF front end filters using 3D solenoid inductors with through glass vias (TGV) and Cu-SiN-Cu MIM structure on Gen1 glass substrate (300mm × 400mm) panel format using color filter manufacturing line for flat panel display. For inductors, drastic performance (size and low resistance therefore high-quality factor) improvement have been demonstrated by technology evolutions from 3D solenoid using TGV with conformal Cu plating method, achieving low resistance of 3.1mohm per 70um diameter TGV on a 400um thick glass panel. This low-resistance TGV with 2.7mOhm/sq TGV connections on both sides of the glass substrate, record high inductor quality factor of 39 was obtained at 2.5GHz using five and half turn inductor of 7.9nH inductance, For capacitors, we have successfully integrated a Cu MIM (metal-insulator-metal) structure by using 15um thick Cu plates and dielectric, resulting in high capacitance density of 0.26nF/mm2 for RF application. By integrating TGV inductor-first and MIM capacitor-next, high-performance and high-density LC components are synthesized to perform as RF front end filters such as low-pass filters, diplexers, triplexers, and multiplexers. The 3D inductors, Cu MIM, LC resonators and filters were successfully integrated using glass panel manufacturing infrastructure for the first time. Process characterization and process control monitors were evaluated at the panel level to address high-volume and high-yield manufacturability of RF filters with the unprecedented filter performance in terms of insertion loss and out of band rejections in smaller form factor than any other technologies have achieved so far. Furthermore, the TGV filters were mounted on electrical evaluation boards as well as JEDEC standard testing boards to check any device-level, chip-level, and board-level reliabilities associated with glass or TGV materials as well as their interaction with Cu, SiN, polymer inter layer dielectric materials, and solder joints, showing no performance degradations during thermal cycling, drop shock, bending, or high-power testing situations.

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Chen, Jian, Zhi-Ji Wang, Bao-Hua Zhu, Eun-Seong Kim, and Nam-Young Kim. "Fabrication of QFN-Packaged Miniaturized GaAs-Based Bandpass Filter with Intertwined Inductors and Dendritic Capacitor." Materials 13, no. 8 (April 20, 2020): 1932. http://dx.doi.org/10.3390/ma13081932.

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This article presents a compact quad flat no-lead (QFN)-packaged second-order bandpass filter (BPF) with intertwined inductors, a dendritic capacitor, and four air-bridge structures, which was fabricated on a gallium arsenide (GaAs) substrate by integrated passive device (IPD) technology. Air-bridge structures were introduced into an approximate octagonal outer metal track to provide a miniaturized chip size of 0.021 × 0.021 λ0 (0.8 × 0.8 mm2) for the BPF. The QFN-packaged GaAs-based bandpass filter was used to protect the device from moisture and achieve good thermal and electrical performances. An equivalent circuit was modeled to analyze the BPF. A description of the manufacturing process is presented to elucidate the physical structure of the IPD-based BPF. Measurements were performed on the proposed single band BPF using a center frequency of 2.21 GHz (return loss of 26.45 dB) and a 3-dB fractional bandwidth (FBW) of 71.94% (insertion loss of 0.38 dB). The transmission zero is located at the 6.38 GHz with a restraint of 30.55 dB. The manufactured IPD-based BPF can play an excellent role in various S-band applications, such as a repeater, satellite communication, and radar, owing to its miniaturized chip size and high performance.

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Renaud-Bezot, Nick, and Mark Beesley. "Making New With Old." International Symposium on Microelectronics 2012, no. 1 (January 1, 2012): 000687–93. http://dx.doi.org/10.4071/isom-2012-wa53.

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In the past few years, embedding has emerged as a valid contender to traditional packaging technologies for specific applications. It uses PCB (Printed-Circuit Board) processes for 3D integration of active and passive elements to create SiPs (System in Package). Just like MEMS (Micro Electro-Mechanical System) and IPD (Integrated Passive Device) emerged from standard semiconductor processes, and then were adapted to match the specific requirements, so does embedding build on decades-old techniques to create this new class of packages. Inherent advantages include:- Compatibility with traditional SMT processes, in particular with regards to pitch,- Production batch size,- Historical reliability and process data,- Thermal management,- Possibility to integrate EMI shielding,- CTE matching. This paper will present the challenges and opportunities of this packaging technology in terms of processes, performance and reliability. It will focus on the solution developed by AT&S called ECP® (Embedded- Component Packaging). Whereas competition is integrating PCB processes to their semiconductor-packaging operations, AT&S is the only vendor building on its PCB tradition to enter the packaging industry, thereby presenting an alternative view of the subject.

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Tang, Jiajie, and Le Luo. "Wafer Level Integration of MMIC and Microwave IPD with Metal/BCB Multilayer Interconnection Based on Low Resistance Silicon." International Symposium on Microelectronics 2011, no. 1 (January 1, 2011): 001067–73. http://dx.doi.org/10.4071/isom-2011-tha6-paper1.

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A new high-density wafer-level integration of a GaAs based monolithic microwave integrated circuit (MMIC) chip and a microwave integrated passive device (IPD) is presented. This integration technology, an important and IC-compatible option for system-in-package (SiP), utilizes bulk Si fabrication and film deposition based multichip module (MCM-D) process. MMIC is entirely embedded into the silicon wafer while IPDs are integrated on the dielectric layers simultaneously with the metal/BCB multilayer interconnection. Key fabrication processes and crucial technologies are described in detail. Normal silicon wafer is selected as substrate because of its mature processing technology, low cost, good thermal dissipation as well as its thermal expansion matching with GaAs. To obtain excellent microwave performances and good planarization, thick photosensitive BCB of 25um/layer is adopted as dielectric and thus the use of tapered via that is hollow inside or filled by BCB is a cost-effective way to accomplish inter-layer connection instead of Au bump bonding or column used in dry-etch BCB process. Further promotions on microwave performances are achieved by the shielding effect through ground layer coverage on silicon surface and the application of microstrip lines. Several experiment results such as dc inter-layer connection resistance and thermal resistance measurements are complemented to investigate the characteristic of the whole package. The Microwave properties of the integration sample are measured by transmission performance test from 15GHz to 30GHz. The measurement results are analyzed and discussed comparing with the theoretical or simulation results.

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Flemming, Jeb, Kyle McWethy, Tim Mezel, Luis Chenoweth, and Carrie Schmidt. "Photosensitive Glass-Ceramics for Heterogeneous Integration." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (January 1, 2019): 000880–907. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_wp1_036.

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The push for heterogeneous integration requires very unique material properties with respect to processing, material constants, and integration capabilities with other materials (such as copper, III–V, magnetics, etc.). Current common circuit board materials such as ceramics and laminates, as well as silicon substrates, suffer from a variety of limitations. For ceramics and laminates, these constraints include: (1) the inability to produce narrow line widths <100 m with narrow gaps between lines <100 m; (2) high surface roughness (on the order of 2μm RMS); (3) layer-to-layer misalignments; and (4) lack of high-quality integrated passives. For silicon, these constraints include: (1) high cost; (2) long design/production lead times; and (3) electrical properties of standard doped silicon are not suitable for millimeter-wave applications. A significant drawback of ceramics and laminates is that they cannot be 3D structured with micron-scale precision which is necessary for advanced interconnects for millimeter-wave IC packaging integration (e.g. transistor-to-board interconnects). These characteristics lead to devices with limited integration options, large footprints, and higher power consumption. To overcome the above limitations, 3D Glass Solutions (3DGS) has developed a photo-sensitive glass ceramics as a board-level system substrate. Compared to ceramics, laminates, and silicon, photo-sensitive glass ceramic materials offer higher interconnect densities, lower processing cost, better spatial resolution, as well as improved electrical properties for both RF and millimeter-wave frequencies. Photo-sensitive glass ceramics are ideal systems-level materials for heterogeneous integration programs as they overcome many of the limitations of legacy materials such as ceramics and laminates for broadband applications (DC – 100GHz). Furthermore, the advanced manufacturing ability of photo-sensitive glass ceramics enable a broad category of IP Blocks. The innovations of the 3DGS technology and research effort include:Low loss and low dispersion: photosensitive glass material has a measured loss tangent of 0.008 at GHz frequencies. Furthermore, the thick and highly-conductive metallization layers allow for low-loss transmission lines.High current and power handling: the metallization processes enable lines with a range of thicknesses (<50m) and widths (>2m), which result in both low resistive loss and high current handling. Additionally, the RF power handling is high due to the high breakdown voltage of glass (10kV/100m) and the possibility of coaxial line integration.Thermal management: high-density metal-filled via arrays generate up to 100W/mK thermal transfer in the 3DGS process and provide an additional thermal path for chips that are not mounted directly on a heterogeneous interface heat spreader.Built-in filtering: when a variety of chiplets with unknown design parameters and with signals of varying time constants are interconnected, EMI becomes a significant problem. The 3DGS approach allows for high-quality filtering, coupling and self-assessment functions to be directly integrated within the 2.5D interposer system as IPDs eliminating wire bonding and providing seamless integration with low loss.Scalability: the glass interconnect plane can be fabricated with footprints up to 40mm × 40mm with integrated air cavities for chip placement, through glass vias for I/Os and redistribution metal. In this presentation, 3DGS will present on three Heterogeneous Integration attributes: (1) design considerations, (2) integration of passive devices, and (3) millimeter wave integration. Design Considerations 3DGS is developing an IP Block library with 11 distinct categories. These categories include: (1) metal filled I/Os, (2) copper redistribution layers, (3) thermal management blocks, (4) cavities, (5) metal filled through glass structures, (6) phased array antenna, (7) conductor undercuts, (8) magnetic core devices, (9) capacitors, (10) inductors, and (11) grounding. While each of these unique IP Blocks contributes their own advantages for analog performance, they can all be integrated into a single chip. Integration of Passives Devices The foundation of the work done by 3DGS is on developing a volume manufacturing approach for high uniformity through glass vias (TGVs). All TGVs for I/O applications are 100% copper filled for low-loss, high power, electrical connections. Two major building blocks of 3DGS' Heterogeneous technology are High Quality Factor inductors and capacitors. 3DGS has developed a broad library of inductor components ranging from 0.5 – 200nH. Footprints are determined by inductance sizes but may be as small as 01005. Capacitors are built by placing two slots inside of the glass material, filling the slots with copper, and using the glass' natural Dk to form a capacitor. The benefit of these capacitors include high breakdown voltage (>1,000V), small footprint, high reliability, and Quality factors between 200–300. Inductors and capacitors can be integrated into a single monolithic RF package called an Integrated Passive Device (IPD). The benefits of the IPD include the elimination of RF losses associated with PCB Interconnects, long metal redistribution line lengths, bond pads, solder balls, and inconsistent assembly. This leads to the production of RF devices, capable of operating in the MHz – GHz frequency range with higher overall system Quality Factors, lower ripple, and lower losses. Furthermore, IPDs can be directly integrated into more complex System-in-Package (SiP) architectures. This approach has been used to build an RF ZigBee module in APEX® Glass [1]. The glass SiP module consisted of 35+ SMT components and was itself soldered to a PCB board. The full RF module was then subjected full complement of reliability tests and met the customer's stringent performance goals. Millimeter Wave Integration A major benefit of glass is the ability to produce low loss structures for millimeter wave applications. 3DGS has been designing and producing a variety of millimeter wave band pass filters with a variety of bandwidths ranging from 5–40%. These bandpass filters are compact, fully shielded and low loss (<2.0dB) with high attenuation (>50dB).

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Morard, Adrien, Jean-Christophe Riou, and Gabriel Pares. "Flip chip reliability and intermetallic compounds for SIP module." International Symposium on Microelectronics 2018, no. 1 (October 1, 2018): 000029–36. http://dx.doi.org/10.4071/2380-4505-2018.1.000029.

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Abstract In the aeronautical field, the electronic integration roadmaps show that the weight and the volume dedicated to on-board electronics must be reduced by a factor of 4 to 10 compared to the existing ones for the most recurrent functions in the next years. This work is an opening to new technological solutions to increase our ability to save space while improving the overall reliability of the system. The first part of this work is dedicated to the study of “system in package” (SiP) solutions based on different substrates, namely organic or silicon. Generally speaking a SIP is composed by several active and passive components stacked on an interposer. Benchmarks done by our laboratory have demonstrated that in terms of substrate, embedded die technology leads to several advantages compared to 3D TSV or TGV based packaging approaches. The benefits provided by this substrate is the possibility to embed some surface mount technologies (SMT), some bare chips or some integrated passives devices (IPD) banks directly above or below the stacked active components. This way, top and bottom surface of the substrate can be used to integrate several heterogeneous dies side by side while using low profile flip-chip assemblies on the C4 side. Finally, in this kind of 3D architecture, this embedded technology enable a gain of integration, without using costly TSV connections. Substrates of high quality allow a reduction of I/Os interconnection pitches leading to very aggressive integration down to 50μm. Secondly, a 3D stack with 3 levels of components, as described above, leads to 2 or 3 REACH compliant sequential assembly processes, depending of the needs. In order to consider all the solutions for an optimized overall integration with high reliability, this work focuse on the study one simple SIP which includes the top die assembled by flip-chip. For the flip chip hybridization on organic interposers copper pillars technologies will be studied. The objective is to understand in depth the processes and to obtain information on the reliability aspect after thermal cycling stress of the flip chip assembly. Thirdly, we built many silicon test chips with different characteristics with a dedicated daisy chain test vehicle. The different parameters are: chip's thicknesses (50 to 200 μm), chip's sizes (2 to 8 mm), bump structures (diameter), the pitches of the interconnection (from 50 to 250 μm) and the number of interconnection rows. Designs were chosen in order to fit real operational configurations. Moreover, these configurations are interesting to build a comprehensive model in order to understand the failure mechanisms. These chips are then stacked by flip chip on the silicon and on the organic substrate. We are also designing the both configurations of substrates. Only the production of the organics part is outsourced. Fourth, for all assemblies thermos-cycling test results will be evaluated with thermo mechanical simulations done by finite elements. 3D models will take into account the different geometries in order to understand and quantify the various key parameters. The analysis will mainly focus on 3D interconnections. Design rules based on the results will be derivated. The aim is to obtain dimensional criteria based on stress versus deformation responses. Lastly intermetallic formation will be evaluated using EBSD analysis to obtain better understanding of copper pillar failures for this specific bumps size. Issued information's will be exploited for designing the future functional SIP. The ultimate goal of this work is finally to define mechanical design rules that can then be used in functional SiP modules.

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Morard, Adrien, Jean-Christophe Riou, and Gabriel Pares. "Flip chip reliability and design rules for SIP module." International Symposium on Microelectronics 2017, no. 1 (October 1, 2017): 000754–60. http://dx.doi.org/10.4071/isom-2017-thp43_125.

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Abstract The first part of this work is dedicated to the study of “system in package” (SiP) solutions based on different substrates, namely organic or silicon. Generally speaking a SIP is composed by several active and passive components stacked on an interposer. Benchmarks done by Safran have demonstrated that in terms of substrate, embedded die technology leads to several advantages compared to 3D TSV or TGV based packaging approaches. The benefits leaded by this substrate is the possibility to embed some Surface Mount Technologies, bare chips or integrated passives devices (IPD) banks directly above or below the stacked active components. This way, top and bottom surface of the substrate can be used to integrate several heterogeneous dies side by side while using low profile flip-chip assemblies on the C4 side. Finally, in this kind of 3D architecture, this embedded technology enable a gain of integration, without using costly TSV connections. Substrates of high quality allow a reduction of interconnection pitches leading to very aggressive integration. Secondly, a 3D stack with 3 levels of components, as described above, means to, at least, 2 or 3 REACH compliant sequential assembly processes, depending on the needs. In order to consider all the solutions for an optimized integration and a high reliability, this work focused on the study of a simple SIP, which includes the top die assembled by flip-chip. For the flip chip hybridization, copper-pillars technologies are studied in the case of both organic and silicon interposers. The aim of this study is to understand in depth both processes and to obtain information on the reliability aspect after thermal cycling stress of the flip chip assembly. Thirdly, we built many silicon test chips with different characteristics with a dedicated daisy chain test vehicle. The different parameters are: chips' thicknesses (50 to 200 μm), chips' sizes (2 to 8 mm), bump structures (diameter), and the pitches of the interconnection (from 50 to 250 μm) and the number of interconnection rows. Designs were chosen in order to fit real operational configurations. Moreover, these configurations are interesting to build a comprehensive model in order to understand the failure mechanisms. These chips are then stacked by flip-chip on the silicon and on the organic substrate. We are also designing the two configurations of substrates. Only the production of the organics part is outsourced. Fourth, with all these configurations we will be able to fit the thermo-cycling test results with thermos-mechanical simulations done by finite elements. 3D models will take into account the different geometries in order to understand and quantify the various key parameters. The analysis will mainly focus on 3D interconnections. Design rules based on the results will be derivate. The aim is to obtain dimensional criteria based on stress versus deformation responses. Information obtained will be exploited for designing the future functional SIP. Fifth, in order to assess the electrical behaviors of this 3D architecture, signal integrity aspect will be considered as well. As for the design, the migration from an existing 2D electrical design to a 3D architecture design will be studied keeping the signal transmission without any degradation. The ultimate aim of this work is to define mechanical and electrical design rules that can then be used in functional SiP modules.

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Gaylord, T. K., and A. Knoesen. "Passive Integrated Optical Anisotropy-based Devices." Journal of Modern Optics 35, no. 6 (June 1988): 925–46. http://dx.doi.org/10.1080/09500348814551061.

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Vaidhyanathan, Balasubramaniam, Ketharam Annapoorani, Jon Binner, and Ramesh Raghavendra. "Microwave Sintering of Multilayer Integrated Passive Devices." Journal of the American Ceramic Society 93, no. 8 (August 2010): 2274–80. http://dx.doi.org/10.1111/j.1551-2916.2010.03740.x.

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Gaborieau, Sophie, Catherine Bunel, and Franck Murray. "3D Passive Integrated Capacitors Towards Even Higher Integration." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (January 1, 2010): 001907–30. http://dx.doi.org/10.4071/2010dpc-wp32.

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IPDIA is involved in Silicon based 3D-IPD advanced technology. This very flexible technology is using standard processing techniques to integrate passive components such as inductors, resistors or capacitors into a silicon substrate. 3D high-density capacitor is at the forefront of IPDIA development program. First process generation with 25nF/mm2 and second generation reaching 80nF/mm2 have been in production for several years. The third generation with multiple metal-insulator-metal (MIM) layer stacks in the pores is reaching 250nF/mm2 and is being qualified now. Intrinsic low parasitic elements of these capacitors (low ESR and ESL) make it very attractive for DC decoupling and very competitive with the ceramic technology. Assembly can be performed using standard reflow soldering and its low profile also allows PICS capacitor integration in embedded module board technology. Sensors, healthcare and medical applications can benefit from this new development. To enable even higher integration, development activities are now focused on the third and fourth generation of high-density capacitors targeting ambitious 1μF/mm2. In this presentation, main characteristics of the PICS high-density capacitors will be described emphasizing on its capability, main applications and advantages versus discrete components. Then, in a second part, challenges raised by the increase of the capacitor density while keeping an acceptable breakdown voltage will be discussed. This includes the integration of high-k materials with adequate electrode and the research for maximizing the 3D silicon surface.

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Bunel, Catherine. "Ultra High Density Capacitors merged with Through Silicon Vias to enhance performances." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (January 1, 2013): 000691–728. http://dx.doi.org/10.4071/2013dpc-tp15.

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IPDIA presents itself as the 3D Silicon leader providing innovative platforms for customers who want to demonstrate technological concepts based on Through Silicon Vias. The market segments Medical, Lighting, and Industrial addressed by the Ipdia Technology are adopting 2.5-D and 3-D technologies to increase the performance and density of their devices through the use of silicon interposers and through-silicon vias (TSVs). The via last approach developed by IPDIA allows large possibility of integration combining TSV with active or passive devices such as High-density trench capacitors, MIM capacitors, Resistors, High-Q inductors or Zener diodes . The purpose of this paper is to focus on through-silicon via (TSV) combined with IPD , providing an interposer which could have two surfaces with devices. Emphasis is placed on 3D trench capacitor technology with an update of the roadmap .Examples of applications using chip-to-chip interconnections through a passive TSV interposer in a 3D IC integration system-in-package (SiP) are briefly presented. Some important results and recommendations are summarized: the process steps for passive devices interposer /TSV/redistribution layer (RDL)/microbumps /, the design rules .A comparison between TSV on active chips and passive interposer with TSV will be detailed.

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Friederich, A., C. Kohler, M. Sazegar, M. Nikfalazar, R. Jakoby, J. R. Binder, and W. Bauer. "Preparation of Integrated Passive Microwave Devices Through Inkjet Printing." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, CICMT (September 1, 2013): 000232–39. http://dx.doi.org/10.4071/cicmt-2013-tha24.

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Barium strontium titanate (BST) is a promising material for passive tunable microwave devices such as phase shifters or tunable matching networks. This publication covers the preparation of BST thick-films for microwave applications through inkjet printing. Two barium strontium titanate (BST) inks were prepared, printed on alumina substrates and sintered at different temperatures. The first ink was prepared with pure BST and sintered between 1100°C and 1200°C. The second ink was prepared with a BST–ZnO–B2O3 composition and was suitable to reduce the sintering temperature down to 800°C. The microstructure of the thick-films reveals the evolution of grain growth with increasing sintering temperature in the thick-films. Furthermore, a reaction with the substrate was observed for both inks at high sintering temperatures. The microwave characterization of the thick-films shows that for the permittivity and the tunability of the films, the effect of grain growth and reaction with the substrate compete against each other. Hence, the optimal microwave properties were achieved at a transition temperature, where first additional phases could already be observed. Even though, the properties are poorer for lower sintering temperatures, the investigations show that the preparation of silver- or gold-based metal–insulator–metal (MIM) structures through inkjet printing is possible with this composition. This allows various new design concepts for partly or fully inkjet printed passive microwave devices. Furthermore, it gives the opportunity for a future integration of passive tunable microwave devices in a low temperature co-fired ceramic (LTCC) fabrication process.

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Sinyukin, A. S., and B. G. Konoplev. "Integrated CMOS Microwave Power Converter for Passive Wireless Devices." Russian Microelectronics 50, no. 3 (May 2021): 189–96. http://dx.doi.org/10.1134/s1063739721020086.

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Kim, Geun Sik, Kai Liu, Flynn Carson, Seung Wook Yoon, and Meenakshi Padmanathan. "Advanced SiP Packaging Technologies of IPD for Mobile Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (January 1, 2010): 1–20. http://dx.doi.org/10.4071/2010dpc-wp31.

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IPD technology was originally developed as a way to replace bulky discrete passive components, but it¡¯s now gaining popularity in ESD/EMI protection applications, as well as in RF, high-brightness LED silicon sub-mounts, and digital and mixed-signal devices. Already well known as a key enabler of system-in-packages (SiPs), IPDs enable the assembly of increasingly complete and autonomous systems with the integration of diverse electronic functions such as sensors, RF transceivers, MEMS, power amplifiers, power management units, and digital processors. The application area for IPD will continue to evolve, especially as new packaging technology, such as flipchip, 3D stacking, wafer level packaging become available to provide vertical interconnections within the IPD. New applications like silicon interposers will become increasingly significant to the market. Currently the IPD market is being driven primarily by RF or wireless packages and applications including, but not limited to, cell phones, WiFi, GPS, WiMAX, and WiBro. In particular, applications and products in the emerging RF CMOS market that require a low cost, smaller size, and high performance are driving demand. In order to get right products in size and performance, packaging design and technology should be considered in device integration and implemented together in IPD designs. In addition, a comprehensive understanding of electrical and mechanical properties in component and system level design is important. This paper will highlight some of the recent advancements in SiP technology for IPD and integration as well as what is developed to address future technology requirements in IPD SiP solutions. The advantage and applications of SiP solution for IPD will be presented with several examples of IPD products. The design, assembly and packaging challenges and performance characteristics will be also discussed.

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Liu, Kai, YongTaek Lee, HyunTai Kim, Gwang Kim, and Billy Ahn. "3D Integration of RF Package." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, DPC (January 1, 2012): 1–21. http://dx.doi.org/10.4071/2012dpc-tp45.

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As form-factor has been one of the key drivers for mobile devices, 3D integrations that make the use of vertical dimension have been widely explored. Conventional side-by-side approaches, for implementing memory devices, controlling circuits, baseband devices, application processors, RF devices, etc., have been replaced by package-on-package (PoP) or other 3D approaches. One key issue for 3D approaches is to maintain signal integrity, which is typically not the bottle-neck for side-by-side solutions. For an RF stack-die package, where at least one of the chips in the configuration is RF chip, having either active or passive function, the interference or cross-talk between the chips in a package may severely deteriorate the signal integrity, and may make the package malfunction. In this paper, we will describe a RF stack-die package where a RF transceiver chip and an IPD chip are implemented. Chip-to-chip interference directly by individual components (e.g., between inductor coils in different chips), and through the power feeding lines (or power distribution networks) in the IPD chip and in the laminate substrate, is investigated. Based on this analysis, proper arrangement of the off-set between the two chips is applied in the final package design, and is approved to be able to overcome a receiver sensitivity issue occurred in the previous version of the package.

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Fainman, Yeshaiahu, D. Tan, S. Zamek, O. Bondarenko, A. Simic, A. Mizrahi, M. Nezhad, et al. "Passive and Active Nanophotonics." Advances in Science and Technology 82 (September 2012): 9–18. http://dx.doi.org/10.4028/www.scientific.net/ast.82.9.

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Dense photonic integration requires miniaturization of materials, devices and subsystems, including passive components (e.g., engineered composite metamaterials, filters, etc.) and active components (e.g., lasers, modulators, detectors). This paper discusses passive and active devices that recently have been demonstrated in our laboratory, including monolithically integrated short pulse compressor utilized with silicon on insulator material platform and design, fabrication and testing of nanolasers constructed using metal-dielectric-semiconductor resonators confined in all three dimensions.

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Han, Mei, Gaowei Xu, and Le Luo. "HIGH PERFORMANCE SILICON-BASED INDUCTORS FOR RF INTEGRATED PASSIVE DEVICES." Progress In Electromagnetics Research 146 (2014): 181–86. http://dx.doi.org/10.2528/pier14040803.

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Clearfield, H. M., J. L. Young, S. D. Wijeyesekera, and E. A. Logan. "Wafer-level chip scale packaging: benefits for integrated passive devices." IEEE Transactions on Advanced Packaging 23, no. 2 (May 2000): 247–51. http://dx.doi.org/10.1109/6040.846642.

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Hauffe, R., U. Siebel, K. Petermann, R. Moosburger, J. R. Kropp, and F. Arndt. "Methods for passive fiber chip coupling of integrated optical devices." IEEE Transactions on Advanced Packaging 24, no. 2 (2001): 450–55. http://dx.doi.org/10.1109/6040.982828.

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Ryu, Jin Hwa, Sangwon Byun, In-Bok Baek, Bong Kuk Lee, Won Ick Jang, Eun-Hye Jang, Ah-Yung Kim, and Han Yung Yu. "Integrated Flexible Electronic Devices Based on Passive Alignment for Physiological Measurement." Sensors 17, no. 4 (April 18, 2017): 889. http://dx.doi.org/10.3390/s17040889.

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Wang Qin, 汪钦, 徐红春 Xu Hongchun, and 胡广文 Hu Guangwen. "Planar Lightwave Circuit Opto-Electronic Integrated Devices for Passive Optical Network." Laser & Optoelectronics Progress 49, no. 11 (2012): 112301. http://dx.doi.org/10.3788/lop49.112301.

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Gill, P., M. Miller, and B. Y. Nguyen. "New materials for active and passive integrated devices for wireless applications." Microelectronic Engineering 56, no. 1-2 (May 2001): 169–75. http://dx.doi.org/10.1016/s0167-9317(00)00522-0.

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Navarro, J. A., and Kai Chang. "Inverted stripline antennas integrated with passive and active solid-state devices." IEEE Transactions on Microwave Theory and Techniques 43, no. 9 (1995): 2059–65. http://dx.doi.org/10.1109/22.414541.

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Mushtaha, Emad S., Taro Mori, and Enai Masamichi. "The Impact of Passive Design on Building Thermal Performance in Hot and Dry Climate." Open House International 37, no. 3 (September 1, 2012): 81–91. http://dx.doi.org/10.1108/ohi-03-2012-b0009.

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Several calls have been everywhere asking for proper use of passive design tools like shading devices, insulation, natural ventilation and solar panels in building architecture of hot-dry area in order to improve the thermal performance of indoor spaces. This paper examines the effect of these passive tools on indoor thermal performance which in turn helps arrange thermal priorities properly. Herein, basic principles of Successive Integration Method (SIM) have been utilized for an integrated design of two floors with small openings integrated with floor cooling, solar panels, natural ventilation, shading devices, and insulation. As a result, create priorities of passive tools that are structured consequently for ventilation, insulation, solar panels, and shading devices. This structure could guide designers and builders to set their priorities for the new development of building construction.

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Vorozhtsov, A. L., A. A. Ivanov, and I. M. Petrenko. "DEVELOPMENT OF MINIATURE BANDPASS FILTER L-BAND FROM INTEGRATED PASSIVE DEVICES TECHNOLOGY." RADIO COMMUNICATION TECHNOLOGY 43 (2019): 70–78. http://dx.doi.org/10.33286/2075-8693-2019-43-70-78.

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Zoschke, Kai, M. JÜrgen Wolf, Michael Topper, Oswin Ehrmann, Thomas Fritzsch, Katrin Kaletta, Franz-Josef Schmuckle, and Herbert Reichl. "Fabrication of Application Specific Integrated Passive Devices Using Wafer Level Packaging Technologies." IEEE Transactions on Advanced Packaging 30, no. 3 (August 2007): 359–68. http://dx.doi.org/10.1109/tadvp.2007.901770.

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Jeong, Inho, J. Y. Kim, B. J. Lee, J. J. Choi, and Y. S. Kwon. "Comparison of RF integrated passive devices on smart silicon and glass substrate." Microwave and Optical Technology Letters 45, no. 5 (2005): 441–44. http://dx.doi.org/10.1002/mop.20848.

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BEIQUE, GENEVIEVE, JOHN ALMERICO, ROBERT DITIZIO, GUILLAUME GUEGAN, and JEAN PHILIPE QUENIOT. "DRY ETCHING OF HIGH-K DIELECTRIC PZT STACKS FOR INTEGRATED PASSIVE DEVICES." Integrated Ferroelectrics 86, no. 1 (January 2006): 49–56. http://dx.doi.org/10.1080/10584580601085669.

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Kwon, Choul, and Kang Lee. "Integrated Daylighting Design by Combining Passive Method with DaySim in a Classroom." Energies 11, no. 11 (November 15, 2018): 3168. http://dx.doi.org/10.3390/en11113168.

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This paper suggests a daylighting design method by combining a passive approach and advanced software to design external shading devices for daylighting in a classroom. A simplified method to predict and assess the indoor natural illuminance is a prerequisite for designers to design schools with better performance. Recently there has been growing demand for school refurbishment; mainly environmental improvement of classrooms in Korea. However, the passive approach of design has been neglected while the use of advanced simulation software has increased, requiring additional time and cost. Combining passive design methods with up-to-date numerical simulation is explored with shading devices to verify the daylighting distribution and daylight autonomy in classrooms with different orientations and shading forms. Weather tool Autodesk Ecotect, for the shading coefficient, and DaySim software (v3.0), for daylight autonomy, were adopted for the initial and the detail design stage, respectively. The findings support the linked design approaches of passive and advanced software would benefit designers in the strategic design process with further potential for design options and lighting electricity reduction.

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Sederberg, Shawn, Curtis J. Firby, Shawn R. Greig, and Abdulhakem Y. Elezzabi. "Integrated nanoplasmonic waveguides for magnetic, nonlinear, and strong-field devices." Nanophotonics 6, no. 1 (January 6, 2017): 235–57. http://dx.doi.org/10.1515/nanoph-2016-0135.

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AbstractAs modern complementary-metal-oxide-semiconductor (CMOS) circuitry rapidly approaches fundamental speed and bandwidth limitations, optical platforms have become promising candidates to circumvent these limits and facilitate massive increases in computational power. To compete with high density CMOS circuitry, optical technology within the plasmonic regime is desirable, because of the sub-diffraction limited confinement of electromagnetic energy, large optical bandwidth, and ultrafast processing capabilities. As such, nanoplasmonic waveguides act as nanoscale conduits for optical signals, thereby forming the backbone of such a platform. In recent years, significant research interest has developed to uncover the fundamental physics governing phenomena occurring within nanoplasmonic waveguides, and to implement unique optical devices. In doing so, a wide variety of material properties have been exploited. CMOS-compatible materials facilitate passive plasmonic routing devices for directing the confined radiation. Magnetic materials facilitate time-reversal symmetry breaking, aiding in the development of nonreciprocal isolators or modulators. Additionally, strong confinement and enhancement of electric fields within such waveguides require the use of materials with high nonlinear coefficients to achieve increased nonlinear optical phenomenon in a nanoscale footprint. Furthermore, this enhancement and confinement of the fields facilitate the study of strong-field effects within the solid-state environment of the waveguide. Here, we review current state-of-the-art physics and applications of nanoplasmonic waveguides pertaining to passive, magnetoplasmonic, nonlinear, and strong-field devices. Such components are essential elements in integrated optical circuitry, and each fulfill specific roles in truly developing a chip-scale plasmonic computing architecture.

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Beal, Aubrey N., John Tatarchuk, Colin Stevens, Thomas Baginski, Michael Hamilton, and Robert N. Dean. "Design Considerations and Ring-down Characteristics of Micromachined, High Current Density Capacitors." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, DPC (January 1, 2014): 001380–406. http://dx.doi.org/10.4071/2014dpc-wa32.

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The need for integrated passive components which meet the stringent power system requirements imposed by increased data rates, signal path density and challenging power distribution network topologies in integrated systems yield diverse motivations for high density, miniaturized capacitors capable of quickly sourcing large quantities of current. These diverse motivations have led to the realization of high density capacitor structures through the means of several technologies. These structures have been evaluated as high-speed, energy storage devices and their respective fabrication technologies have been closely compared for matching integrated circuit speed and density increase, chip current requirements, low resistance, low leakage current, high capacitance and compatibility with relatively high frequencies of operation (~1GHz). These technologies include devices that utilize pn junctions, Schottky barriers, optimized surface area techniques and the utilization of high dielectric constant (high-K) materials, such as hafnium oxide, as a dielectric layer through the means of atomic layer deposition (ALD). The resulting devices were micro-machined, large surface area, thin, high-density capacitor technologies optimized as embedded passive devices for thin silicon interposers. This work outlines the design, fabrication, simulation and testing of each device revision using standard silicon microfabrication processes and silicon interposer technologies. Consequently, capacitive storage devices were micro-machined with geometries which maximize surface area and exhibit the capability of sourcing 100A of current with a response time greater than 100 A/nsec through the use of thin layered, ALD high-K materials. The simulation and testing of these devices show general agreement when subjected to a standard ring-down procedure. This paper provides descriptions and design challenges encountered during fabrication, testing and integration of these passive devices. In addition, potential device integration and implementation strategies for use in silicon interposers are also provided. The modification and revision of several device generations is documented showing increased device capacitance density, maximized current capabilities and minimized effects of series inductance and resistance. The resulting structures are thin, capacitive devices that may be micro-machined using industry standard Si MEMS processes and are compatible with Si interposer 3D technologies. The subsequent design processes allow integrated passive components to be attached beneath chips in order to maximize system area and minimize the chip real estate required for capacitive energy storage devices.

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Sun, Xin, Yun-hui Zhu, Zhen-hua Liu, Qing-hu Cui, Sheng-lin Ma, Jing Chen, Min Miao, and Yu-feng Jin. "Electrical characterization of integrated passive devices using thin film technology for 3D integration." Journal of Zhejiang University SCIENCE C 14, no. 4 (April 2013): 235–43. http://dx.doi.org/10.1631/jzus.c12mnt01.

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Cocorullo, G., F. G. Della Corte, R. de Rosa, I. Rendina, A. Rubino, and E. Terzini. "Amorphous silicon-based guided-wave passive and active devices for silicon integrated optoelectronics." IEEE Journal of Selected Topics in Quantum Electronics 4, no. 6 (1998): 997–1002. http://dx.doi.org/10.1109/2944.736096.

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Cheung, T. S. D., and J. R. Long. "Shielded Passive Devices for Silicon-Based Monolithic Microwave and Millimeter-Wave Integrated Circuits." IEEE Journal of Solid-State Circuits 41, no. 5 (May 2006): 1183–200. http://dx.doi.org/10.1109/jssc.2006.872737.

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Jiang, Pisu, and Krishna C. Balram. "Suspended gallium arsenide platform for building large scale photonic integrated circuits: passive devices." Optics Express 28, no. 8 (April 9, 2020): 12262. http://dx.doi.org/10.1364/oe.385618.

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Hsu, Yuan-Chia, Hwann-Kaeo Chiou, Hua-Yen Chung, Tsung-Yu Yang, Chia-Long Chang, and Ying-Zong Juang. "A V-band band-pass filter design using advanced integrated passive devices technology." Microwave and Optical Technology Letters 58, no. 1 (November 26, 2015): 199–202. http://dx.doi.org/10.1002/mop.29521.

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Righini, Giancarlo C., and Jesús Liñares. "Active and Quantum Integrated Photonic Elements by Ion Exchange in Glass." Applied Sciences 11, no. 11 (June 4, 2021): 5222. http://dx.doi.org/10.3390/app11115222.

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Ion exchange in glass has a long history as a simple and effective technology to produce gradient-index structures and has been largely exploited in industry and in research laboratories. In particular, ion-exchanged waveguide technology has served as an excellent platform for theoretical and experimental studies on integrated optical circuits, with successful applications in optical communications, optical processing and optical sensing. It should not be forgotten that the ion-exchange process can be exploited in crystalline materials, too, and several crucial devices, such as optical modulators and frequency doublers, have been fabricated by ion exchange in lithium niobate. Here, however, we are concerned only with glass material, and a brief review is presented of the main aspects of optical waveguides and passive and active integrated optical elements, as directional couplers, waveguide gratings, integrated optical amplifiers and lasers, all fabricated by ion exchange in glass. Then, some promising research activities on ion-exchanged glass integrated photonic devices, and in particular quantum devices (quantum circuits), are analyzed. An emerging type of passive and/or reconfigurable devices for quantum cryptography or even for specific quantum processing tasks are presently gaining an increasing interest in integrated photonics; accordingly, we propose their implementation by using ion-exchanged glass waveguides, also foreseeing their integration with ion-exchanged glass lasers.

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Dindo, S., R. North, and D. Madge. "A manufacturing process for gallium arsenide monolithic microwave integrated circuits." Canadian Journal of Physics 65, no. 8 (August 1, 1987): 885–91. http://dx.doi.org/10.1139/p87-138.

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Over the last several years, Optotek has successfully developed the capability to design and process high-frequency x-band monolithic microwave integrated circuits. A process for fabricating active devices and passive elements is described. In addition, dc and microwave measurements are presented.

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Journal articles on the topic 'Integrated Passive Devices IPD'

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