Academic literature on the topic 'Inter-processor communication'

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Journal articles on the topic "Inter-processor communication"

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Hossain, M. A., and M. O. Tokhi. "INTER-PROCESSOR AND INTER-PROCESS COMMUNICATION IN REALTIME MULTI-PROCESS COMPUTING." IFAC Proceedings Volumes 35, no. 1 (2002): 337–42. http://dx.doi.org/10.3182/20020721-6-es-1901.00962.

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Baker, A. H., R. D. Falgout, and U. M. Yang. "An assumed partition algorithm for determining processor inter-communication." Parallel Computing 32, no. 5-6 (2006): 394–414. http://dx.doi.org/10.1016/j.parco.2006.06.009.

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Malleswar, C. D., and Ashok Jhunjhunwala. "Inter Processor Communication for Fault Diagnosis in Multiprocessor Systems." Defence Science Journal 44, no. 2 (1994): 99–104. http://dx.doi.org/10.14429/dsj.44.4156.

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AL NA'MNEH, RAMI, W. DAVID PAN, and SEONG-MOO YOO. "TWO PARALLEL 1-D FFT ALGORITHMS WITHOUT ALL-TO-ALL COMMUNICATION." Parallel Processing Letters 16, no. 02 (2006): 153–64. http://dx.doi.org/10.1142/s012962640600254x.

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Computing the 1-D Fast Fourier Transform (FFT) using the conventional six-step FFT algorithm on parallel computers requires intensive all-to-all communication due to the necessity of matrix transpose in three steps. This all-to-all communication is a limiting factor in improving the performance of FFT in its parallel implementations. In this paper, we present two parallel algorithms for implementing the 1-D FFT without all-to-all communication between processors, at the expense of increased inner-processor computation as compared to the conventional six-step FFT algorithm. Our analysis reveals
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Nielsen, Kjell, and Harald Carlsson. "Inter-processor communication and Ada in distributed real-time systems." Computer Communications 13, no. 8 (1990): 451–59. http://dx.doi.org/10.1016/0140-3664(90)90128-4.

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Haefner, James W. "Food-web simulation on parallel computers: Inter-processor communication benchmarks." Ecological Modelling 54, no. 1-2 (1991): 73–79. http://dx.doi.org/10.1016/0304-3800(91)90099-m.

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Ando, Yuki, Yukihito Ishida, Shinya Honda, Hiroaki Takada, and Masato Edahiro. "Automatic Synthesis of Inter-heterogeneous-processor Communication for Programmable System-on-chip." IPSJ Transactions on System LSI Design Methodology 8 (2015): 95–99. http://dx.doi.org/10.2197/ipsjtsldm.8.95.

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Adiono, Trio, Rian Ferdian, Febri Dawani, Imran Abdurrahman, Rachmad Vidya Wicaksana Putra, and Nur Ahmadi. "An Inter-Processor Communication (IPC) Data Sharing Architecture in Heterogeneous MPSoC for OFDMA." Journal of ICT Research and Applications 12, no. 1 (2018): 70–86. http://dx.doi.org/10.5614/itbj.ict.res.appl.2018.12.1.5.

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Masood, Sabeen, Shoab Ahmed Khan, Ali Hassan, and Urooj Fatima. "A Novel Framework for Testing High-Speed Serial Interfaces in Multiprocessor Based Real-Time Embedded System." Applied Sciences 11, no. 16 (2021): 7465. http://dx.doi.org/10.3390/app11167465.

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Recent years has seen a tremendous increase in processing requirements of present-day embedded system applications. Embedded systems consist of multiple processing elements (PEs) connected to each other using different types of interfaces. Many complicated tasks are accomplished by embedded systems in varied settings, which may introduce errors during inter-processor communication. Testing such systems is tremendously difficult and challenging from testing non-real time systems. A major part of testing real time embedded systems involves ensuring accuracy and timing in synchronous inter-proces
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Jiang, Jian Chun, Bing He, Peng Hua Li, and Kai Long Wang. "A Dual-Core Operating System Framework Based on AutoSAR OS for HCS12X Series Processor." Applied Mechanics and Materials 536-537 (April 2014): 1041–46. http://dx.doi.org/10.4028/www.scientific.net/amm.536-537.1041.

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One kind of processors with coprocessor is widely used in control areas. Traditional single-core operating system (OS) cant support the coprocessor. In order to take full advantage of the performance of the processor, we presented a real-time operating system framework named AutoOSEK-CP on the basis of AutoOSEK, which is a single-core operating system based on AutoSAR OS, to support dual-core processor. In this architecture, alarm management, interrupt processing and inter-core communication mechanism were moved in coprocessor module, and the master processor was responsible for the other func
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Dissertations / Theses on the topic "Inter-processor communication"

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Tseng, Yu-Chee. "Strategies for processor allocation and inter-processor communication in multicomputer networks /." The Ohio State University, 1994. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487849696965046.

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Apel, T., G. Haase, A. Meyer, and M. Pester. "Parallel solution of finite element equation systems: efficient inter-processor communication." Universitätsbibliothek Chemnitz, 1998. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-199800670.

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This paper deals with the application of domain decomposition methods for the parallel solution of boundary value problems for partial differential equations over a domain $Omegabset R^d$, $d=2,3$. The attention is focused on the conception of efficient communication routines for the data exchange which is necessary for example in the preconditioned cg-algorithm for solving the resulting system of algebraic equations. The paper describes the data structure, different algorithms, and computational tests.
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Kennedy, Matthew D. "Power-Efficient Nanophotonic Architectures for Intra- and Inter-Chip Communication." Ohio University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1458232838.

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Thompson, Christopher Callum. "On the simulation and design of manycore CMPs." Thesis, University of Edinburgh, 2015. http://hdl.handle.net/1842/11699.

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The progression of Moore’s Law has resulted in both embedded and performance computing systems which use an ever increasing number of processing cores integrated in a single chip. Commercial systems are now available which provide hundreds of cores, and academics have proposed architectures for up to 1024 cores. Embedded multicores are increasingly popular as it is easier to guarantee hard-realtime constraints using individual cores dedicated for tasks, than to use traditional time-multiplexed processing. However, finding the optimal hardware configuration to meet these requirements at minimum
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Havran, Jan. "Komunikace na čipu ADSP-SC58x." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2018. http://www.nusl.cz/ntk/nusl-385887.

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This projects describes the design of communication between SHARC and ARM cores on ADSP-SC58x platform, concretely between bare-metal and Linux applications on ADSP-SC589 chips. There are outlined several available technologies for data transfer, such as MCAPI, MDMA or shared memory. There are also designed and implemented new communication principes based on current implementations of these technologies.
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Kågesson, Filip, and Simon Cederbom. "Resource Optimization of MPSoC for Industrial Use-cases." Thesis, Högskolan i Halmstad, Akademin för informationsteknologi, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-39729.

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Today’s embedded systems require more and more performance but they are still required to meet power constraints. Single processor systems can deliver high performance but this leads to high power consumption. One solution to this problem is to use a multiprocessor system instead which is able to provide high performance and at the same time meet the power constraints. The reason that such a system can meet the power constraints is that it can have a lower clock frequency than a similar single processor system. The focus of the project is to explore possibilities when developing new multiproce
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Hedge, S. J. "Inter-processor communications in microelectronic associative string processors." Thesis, Brunel University, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.375201.

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Lee, Sung-Yuan, and 李松遠. "Evaluation and Optimization of Inter-processor communication for Embedded Heterogeneous Multi-core." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/81861216898299196306.

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碩士<br>國立交通大學<br>資訊學院碩士在職專班資訊組<br>97<br>A heterogeneous multi-core processor composed of a general purpose processor (GPP) which handles the program flow and I/O and a digital signal processor (DSP) which processes mass data is widely used in an embedded system to improve the performance and energy efficiency. To exchange the data between a GPP and DSP, inter-processor communication (IPC) mechanism is required. In this paper, we evaluate the performance of the IPC for an embedded heterogeneous multi-core processor under different design strategies and parameters through a comprehensive experime
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Chen, Chiun-Shiu, and 陳俊旭. "Integrated Support to Improve Inter-Thread Communication and Synchronization in a Multithreaded Processor." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/84705715131146512462.

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碩士<br>國立交通大學<br>資訊工程研究所<br>82<br>This thesis suggests an integrated compiler, runtime control, and hardware solution to improve inter-thread communication and synchronization in a multithreaded processor architecture. Multithreading improves processor utilization by supporting and exphoiting more parallelism. The improvement of utilization, however, meets a great hindrance in inter-thread communication and synchronization problems. These problems incur extra communication overheads and thus
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Lee, Jia-Ming, and 李家銘. "A Parallel Algorithm for Partial Multiple Periodic Patterns Mining with Minimum Inter-Processor Communication." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/70119644272000704783.

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碩士<br>國立東華大學<br>資訊工程學系<br>92<br>Partial periodic patterns mining is a very interesting topic in data mining problem. It is widely used in the market analysis, such as stock management and sale management, etc. However, as the amount of data increases, the scalability of data mining algorithm has become a very important objective. To improve the scalability, in recent years, the concept of parallel computing has been applied on general data mining algorithm. In this thesis, the problem of mining partial multiple periodic patterns under the parallel computing environment is discussed. To reduc
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Books on the topic "Inter-processor communication"

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Hedge, Stephen John. Inter-processor communications in microelectronic associative string processors. Brunel University, 1987.

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Book chapters on the topic "Inter-processor communication"

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Ekman, J., C. Berger, F. Kiamilev, et al. "A Distributed Computing Demonstration System Using FSOI Inter-Processor Communication." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-45591-4_153.

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Murakami, Ken-ichiro. "A pseudo network approach to inter-processor communication on a shared-memory multi-processor MacELIS." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 1990. http://dx.doi.org/10.1007/bfb0024162.

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Lai, Guan-Joe, Jywe-Fei Fang, Pei-Shan Sung, and Der-Lin Pean. "Scheduling Parallel Tasks onto NUMA Multiprocessors with Inter-processor Communication Overhead." In Parallel and Distributed Processing and Applications. Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/3-540-37619-4_9.

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Kubota, Atsushi, Shogo Tatsumi, Toshihiko Tanaka, et al. "A technique to eliminate redundant inter-processor communication on parallelizing compiler TINPAR." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/bfb0024216.

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Palazzari, Paolo, Thomas Lippert, and Klaus Schilling. "Hyper-Systolic Processing on the Quadrics: Improving Inter-Processor Communication by Simulated Annealing." In Advances in High Performance Computing. Springer Netherlands, 1997. http://dx.doi.org/10.1007/978-94-011-5514-4_9.

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Rosner, S., M. Scholles, and D. Forchel. "Near-optimal scheduling of synchronous data-flow graphs by exact calculation of inter-processor communication costs." In High-Performance Computing and Networking. Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/bfb0031677.

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"Inter-Processor Communication (IPC)." In Multicore DSP. John Wiley & Sons, Ltd, 2017. http://dx.doi.org/10.1002/9781119125587.ch9.

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Storer, Christine. "Factors Affecting Inter-Organisational Information Management Systems in Australian Food Processor Chains." In Supply Chain Management. IGI Global, 2007. http://dx.doi.org/10.4018/978-1-59904-231-2.ch009.

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It is agreed that good communication systems between organisations increase customer satisfaction and relationship behaviour and are important issues in chain collaboration and competition. However, less is known about the details of how information is used to manage relationships and coordinate customers and suppliers in chains. In earlier stages of the research, a dynamic model of interorganisational information management systems (IOIMS) and relationships was developed. This chapter presents an evaluation of this model based on a survey of Australian food processors and a green life industry case study and an evaluation of a revised version of this model. It was found that a strategic-oriented IOIMS were positively associated with IOIMS satisfaction that was, in turn, positively associated with perceived current outcomes (satisfaction with performance, perceived responsiveness, and strength of relationship trust). However, (attitudinal) commitment to develop long-term customer/supplier relationships was not significantly associated with the IOIMS, IOIMS satisfaction, or current outcomes. Results were moderated by the nature of the business environment—power/dependency, experience, and market uncertainty. These findings are discussed along with implications for management and suggestions for future research.
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Wu, Xiaoxin, Huan Chen, Yaoda Liu, and Wenwu Zhu. "A Novel Energy Saving Approach through Mobile Collaborative Computing Systems." In Wireless Technologies. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-61350-101-6.ch310.

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Energy saving has been studied widely in both of computing and communication research communities. For handheld devices, energy is becoming a more and more critical issue because lots of applications running on handhelds today are computation or communication intensive and take a long time to finish. Unlike previous work that proposes computing or communication energy solutions alone, this paper proposes a novel energy savings approach through mobile collaborative systems, which jointly consider computing and communication energy cost. In this work, the authors use streaming video as investigated application scenario and propose multi-hop pipelined wireless collaborative system to decode video frames with a requirement for maximum inter-frame time. To finish a computing task with such a requirement, this paper proposes a control policy that can dynamically adapt processor frequency and communication transmission rate at the collaborative devices. The authors build a mathematical energy model for collaborative computing systems. Results show that the collaborative system helps save energy, and the transmission rate between collaborators is a key parameter for maximizing energy savings. The energy saving algorithm in computing devices is implemented and the experimental results show the same trend.
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Khawand, Charbel. "Smart Inter-Processor Communicator Protocol Stack." In Encyclopedia of Wireless and Mobile Communications. Auerbach Publications, 2007. http://dx.doi.org/10.1201/noe1420043266.ch120.

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Conference papers on the topic "Inter-processor communication"

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Katevenis, Manolis G. H. "Towards unified mechanisms for inter-processor communication." In 2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS). IEEE, 2008. http://dx.doi.org/10.1109/icsamos.2008.4664839.

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Poornima, Y. T., Suresh Reddy Kalathuru, and Prerana Gupta Poddar. "Mailbox based inter-processor communication in SoC." In 2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT). IEEE, 2017. http://dx.doi.org/10.1109/rteict.2017.8256756.

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Shanmugam, Karthik. "Securing Inter-Processor Communication in Automotive ECUs." In Symposium on International Automotive Technology 2019. SAE International, 2019. http://dx.doi.org/10.4271/2019-26-0363.

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Samman, Faizal Arya, Thagiat Ahzan, Fandhi Nugraha, and Rhiza S. Sadjad. "Design and Validation of Asynchronous Inter FPGA Transceivers for Inter Processor Communication." In 2018 International Seminar on Intelligent Technology and Its Applications (ISITIA). IEEE, 2018. http://dx.doi.org/10.1109/isitia.2018.8711250.

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Pei, Ke, and Gang Zhang. "Inter-processor Communication Interface Design in Complementary Multiprocessor Systems." In 2009 International Conference on New Trends in Information and Service Science (NISS). IEEE, 2009. http://dx.doi.org/10.1109/niss.2009.266.

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Kandemir, Mahmut, Yuanrui Zhang, Sai Prasanth Muralidhara, Ozcan Ozturk, and Sri Hari Krishna Narayanan. "Slicing based code parallelization for minimizing inter-processor communication." In the 2009 international conference. ACM Press, 2009. http://dx.doi.org/10.1145/1629395.1629409.

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Xingang_Ju, Yi Qin, LiangYang, and Shitan_Huang. "Overview of inter-communication mechanism on multi-core processor." In 2010 International Conference on Computer Application and System Modeling (ICCASM 2010). IEEE, 2010. http://dx.doi.org/10.1109/iccasm.2010.5620488.

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Tongsan, Pasakorn, and Krerk Piromsopa. "A software-defined inter-processor communication for embedded system." In 2016 13th International Joint Conference on Computer Science and Software Engineering (JCSSE). IEEE, 2016. http://dx.doi.org/10.1109/jcsse.2016.7748848.

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Yang, Chengmo, and Alex Orailoglu. "Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs." In the 2007 international conference. ACM Press, 2007. http://dx.doi.org/10.1145/1289881.1289909.

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Bing Yang, Zhigang Mao, Jieming Yin, and Xiao Chen. "A point to point inter-cluster communication network in clustered superscalar processor." In 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT). IEEE, 2008. http://dx.doi.org/10.1109/icsict.2008.4734916.

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