Relevant bibliographies by topics / Interconnect line

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Interconnect line'

Author: Grafiati
Published: 4 June 2021
Last updated: 11 February 2022

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Journal articles on the topic "Interconnect line"

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Majumder, Manoj Kumar, Nisarg D. Pandya, B. K. Kaushik, and S. K. Manhas. "Signal Integrity Analysis in Single and Bundled Carbon Nanotube Interconnects." Journal of Nanoscience 2013 (August 4, 2013): 1–6. http://dx.doi.org/10.1155/2013/407301.

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Carbon nanotube (CNT) can be considered as an emerging interconnect material in current nanoscale regime. They are more promising than other interconnect materials such as Al or Cu because of their robustness to electromigration. This research paper aims to address the crosstalk-related issues (signal integrity) in interconnect lines. Different analytical models of single- (SWCNT), double- (DWCNT), and multiwalled CNTs (MWCNT) are studied to analyze the crosstalk delay at global interconnect lengths. A capacitively coupled three-line bus architecture employing CMOS driver is used for accurate estimation of crosstalk delay. Each line in bus architecture is represented with the equivalent RLC models of single and bundled SWCNT, DWCNT, and MWCNT interconnects. Crosstalk delay is observed at middle line (victim) when it switches in opposite direction with respect to the other two lines (aggressors). Using the data predicted by ITRS 2012, a comparative analysis on the basis of crosstalk delay is performed for bundled SWCNT/DWCNT and single MWCNT interconnects. It is observed that the overall crosstalk delay is improved by 40.92% and 21.37% for single MWCNT in comparison to bundled SWCNT and bundled DWCNT interconnects, respectively.
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Kahng, Andrew B., Sudhakar Muddu, and Egino Sarto. "Tuning Strategies for Global Interconnects in High-Performance Deep-Submicron ICs." VLSI Design 10, no. 1 (January 1, 1999): 21–34. http://dx.doi.org/10.1155/1999/38974.

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Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of line thicknesses, widths and spacings in multi-layer interconnect to simultaneously optimize signal distribution, signal performance, signal integrity, and interconnect manufacturability and reliability. This is a key activity in most leading-edge design projects, but has received little attention in the literature. Our work provides the first technology-specific studies of interconnect tuning in the literature. We center on global wiring layers and interconnect tuning issues related to bus routing, repeater insertion, and choice of shielding/spacing rules for signal integrity and performance. We address four basic questions. (1) How should width and spacing be allocated to maximize performance for a given line pitch? (2) For a given line pitch, what criteria affect the optimal interval at which repeaters Should be inserted into global interconnects? (3) Under what circumstances are shield wires the optimum technique for improving interconnect performance? (4) In global interconnect with repeaters, what other interconnect tuning is possible? Our study of question (4) demonstrates a new approach of offsetting repeater placements that can reduce worst-case cross-chip delays by over 30% in current technologies.
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List, R. Scott, Abha Singh, Andrew Ralston, and Girish Dixit. "Integration of Low-k Dielectric Materials Into Sub-0.25-μm Interconnects." MRS Bulletin 22, no. 10 (October 1997): 61–69. http://dx.doi.org/10.1557/s0883769400034229.

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As the dimensions of ultralarge-scale-integration devices scale to smaller feature sizes and larger die dimensions, the resistance-capacitance (RC) delay of the metal interconnect will increasingly limit the performance of high-speed logic chips. This is because the transistor capacitance and resistance both scale to lower values as the feature size is reduced, while both the line-to-line capacitance and resistance of the metal-interconnect lines increase as their dimensions decrease. For interconnects 5-mm long, the crossover feature size at which the interconnect delay dominates the transistor delay is approximately 0.5 μm. Since this interconnect RC delay increases roughly quadratically with decreasing feature size versus the historical quadratic reduction in transistor delay, device designers currently face difficult barriers to continued performance increases with scaling. Figure 1 presents the components of the RC delay for a single-transistor/single-interconnect combination with 0.35-μm feature sizes. The total delay can be broken into four additive components: the transistor delay R0C0, the interconnect delay rLcL, and the two transistor/interconnect cross terms where R0 and C0 are the transistor resistance and capacitance, r and c are the specific resistance and capacitance, and L is the interconnect length. As can be seen for interconnect lengths less than about 100-μm long, the intrinsic transistor delay dominates. However for interconnect lengths between approximately 100 μm and 10 mm, the resistance of the transistor coupled with the capacitance of the interconnect dominates the combined delay, resulting in a linear increase in delay with increasing line length.
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O'Reilly, Michael, Michael J. Renn, and Stephen Barnes. "Aerosol Jet Printer as an Alternative to Wire Bond and TSV Technology for 3D Interconnect Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (January 1, 2011): 001250–68. http://dx.doi.org/10.4071/2011dpc-wa11.

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Optomec's Aerosol Jet print platform provides an evolutionary alternative to both wire bond and TSV technology, providing high density 3-dimensional interconnect capabilities which enable multi-functional integrated circuits to be stacked and vertically interconnected in high performance System-in-Package (SiP) solutions. The die stacks can include 8 or more die, with a total stack height of ~ 1 mm. The printing system has a working distance of several mm which means that no Z-height adjustments are required for the interconnect printing. Closely coupled pneumatic atomizers with multiplexed print nozzles are used to achieve production throughput of greater than 15,000 interconnects per hour. The Aerosol Jet deposits silver nanoparticle ink connections on staggered multi-chip die stacks. High aspect ratio interconnects with <30-micron line width and 6-micron line heights have been demonstrated at sub 60-micron pitches with resistivity <1x10−7 ohm*m. Pre-production yields exceeding 80% have been consistently realized. This paper will be further expanded to include pre-production qualification results, final production packaging, and further definition of the Aerosol Jet print platform integrated within a high throughput, manufacturing ready automation solution.
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Praveen Kumar, Ch, E. Sreenivasa Rao, and P. Chandra Sekhar. "Novel Approach to Analyze Crosstalk for a Multi-Line Bus System at 32-nm Technology." Journal of Circuits, Systems and Computers 29, no. 13 (March 3, 2020): 2050216. http://dx.doi.org/10.1142/s0218126620502163.

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This research paper presents a novel approach to analyze the crosstalk-induced delay of multi-layered graphene nanoribbon (MLGNR) and multi-walled carbon nanotube (MWCNT) interconnects. A multi-line driver-interconnect-load (DIL) system is employed to analyze the crosstalk-induced delay for different switching transitions. The interconnect lines of the proposed DIL are said to be operated by either a resistive or a CMOS, or a CNFET driver for different switching transitions at 32-nm technology. Using the unique CNFET driver, the victim line of the multi-level MLGNR/MWCNT-based bus system experiences a delay almost 57.25% and 31.62% lesser in comparison to a resistive driver and a CMOS interconnect driver, respectively. Additionally, the overall worst-case delays are reduced by 89.45% and 98.98% for MLGNR in comparison to an equivalent MWCNT at 100[Formula: see text][Formula: see text]m and 1,000[Formula: see text][Formula: see text]m interconnect lengths, respectively.
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Murthy, N. S., and M. Kavicharan. "A Survey on FDTD-Based Interconnect Modeling." Journal of Circuits, Systems and Computers 24, no. 01 (November 10, 2014): 1530001. http://dx.doi.org/10.1142/s0218126615300019.

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This paper presents a selective survey of finite difference time domain (FDTD)-based interconnects modeling for signal integrity analysis problems. In spite of 47 years of its existence, researchers have focused on FDTD method with further modifications and enhancements for the signal integrity analysis of interconnects over the past two decades only. Because of the remarkable amount of interconnect-based FDTD-related research activity, tracking the FDTD literature can be a tedious and challenging task. This survey presents some of the significant methods and approaches employed to analyze the developments achieved up to the present-day signal integrity related research. These methods are based on solving telegrapher's equations which represent the transmission line behavior of interconnects. Recent research concentrates on developing novel methods for accurate interconnect modeling, extraction of interconnect parameters and incorporation of more lumped elements into FDTD. In this paper an attempt has been made to compare and summarize some of the well-known FDTD-based methods, which were used in interconnect related research.
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Leon, R., J. A. Colon, K. C. Evans, D. T. Vu, V. Blaschke, B. Bavarian, E. T. Ogawa, and P. S. Ho. "Void evolution and its dependence on segment length in Cu interconnects." Journal of Materials Research 19, no. 11 (November 1, 2004): 3135–38. http://dx.doi.org/10.1557/jmr.2004.0408.

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Void evolution during electromigration was studied by recording void nucleation, growth, and displacements at various intervals during thermal (240 °C) and electrical stress tests (2 × 106 amps/cm2) of Cu interconnects. Structural data was collected for various serially arranged line segment lengths and correlated with resistance and increases in resistance due to electromigration-induced thinning and voiding. These results allowed determination of void growth rates in Cu interconnects. Void nucleation and growth show a clear dependence on segment length. Void formation did not occur at the via/interconnect interface, which improved interconnect reliability by allowing extensive voiding before catastrophic failure.
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KAVICHARAN, M., N. S. MURTHY, and N. BHEEMA RAO. "EFFICIENT DELAY AND CROSSTALK ESTIMATION MODELS FOR CURRENT-MODE HIGH SPEED INTERCONNECTS UNDER RAMP INPUT." Journal of Circuits, Systems and Computers 23, no. 06 (May 14, 2014): 1450082. http://dx.doi.org/10.1142/s0218126614500820.

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In this paper, closed-form models for the computation of finite ramp responses of current-mode resistance inductance capacitance (RLC) interconnects in VLSI circuits are presented. These models are based on extended Eudes model and Scaling and Squaring algorithm which allow numerical estimation of delay in lossy very large scale integration (VLSI) interconnects. The existing Eudes model for interconnect transfer function approximation is extended to higher-order and then Scaling and Squaring method is applied for further improving the accuracy of delay estimation. With the equivalent lossy interconnect transfer function, finite ramp responses are obtained and line delay is estimated for various line lengths, per unit inductances and load capacitances. The estimated 50% delay values are compared with HSPICE W-element model. The worst case errors observed in the estimated delay values are 14.3% for Eudes model and 2% for extended Eudes model while the proposed Scaling and Squaring based model with 1% error is in very good agreement with HSPICE for line lengths 0.1–0.5 cm. The estimated crosstalk induced delay values of proposed model maximum error percentage is nearly half of the extended Eudes model. For both single and three coupled interconnect lines, the proposed model is in good agreement with HSPICE.
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Farrokhi, Maryam, Rahim Faez, Saeed Haji Nasiri, and Bita Davoodi. "Effect of Varying Dielectric Constant on Relative Stability for Graphene Nanoribbon Interconnects." Applied Mechanics and Materials 229-231 (November 2012): 201–4. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.201.

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The remarkable properties of graphene nanoribbons (GNRs) make them attractive for nano-scale devices applications, especially for transistor and interconnect. Furthermore, for reduction interconnects signal delay, low dielectric constant materials are being introduced to replace conventional dielectrics in next generation IC technologies. With these regards, studding the effect of varying dielectric constant (ɛr) on relative stability of graphene nanoribbons interconnect is an important viewpoint in performance evaluation of system. In this paper, Nyquist stability analysis based on transmission line modeling (TLM) for graphene nanoribbon interconnects is investigated. In this analysis, the dependence of the degree of relative stability for multilayer GNR (MLGNR) interconnects on the dielectric constant has been acquired. It is shown that, increasing the dielectric constant of each ribbon, MLGNR interconnects become more stable.
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Salinas, J., Yinan Shen, and F. Lombardi. "A sweeping line approach to interconnect testing." IEEE Transactions on Computers 45, no. 8 (1996): 917–29. http://dx.doi.org/10.1109/12.536234.

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Dissertations / Theses on the topic "Interconnect line"

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Shah, Chintan Hemendra. "Inductively Coupled Interconnect for Chip to Chip Communication over Transmission Line." NCSU, 2009. http://www.lib.ncsu.edu/theses/available/etd-04012009-003531/.

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As data frequency increases beyond several Gbps range, low power chip to chip communication becomes more critical. The concept researched in this thesis is inductively coupled interconnect (LCI) over short length transmission line. The data will be transmitted across a 10 cm differential microstrip line on FR-4 material with a transformer on each side of the line. The transmitter and receiver circuits are designed in TSMC 0.18μm process technology and can operate at 2.5 Gbps. The power consumption of the design is 5.53 mW at 2.5 Gbps which yields around 2.21 mW.Gb-1.s-1. This design can achieve BER of less than 10-12. The inductive coupling will reduce DC power because the low frequency DC component of the signal will be blocked by coupling inductors. The power consumed by this design is lower than most of the conventional I/Os that use physical contact interconnects. An H-bridge current steering driver is used at the transmitter and a differential amplifier and Sense-amp Flip flop is used at the receiver.
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Wikström, Adam. "Modeling of stresses and deformation in thin film and interconnect line structures." Doctoral thesis, KTH, Solid Mechanics, 2001. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3224.

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Wikström, Adam. "Modeling of stresses and deformation in thin film and interconnect line structures /." Stockholm : Tekniska högsk, 2001. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3224.

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Gao, Youxin. "Interconnect optimization in deep sub-micron design under the transmission line model." Digital version:, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p9992795.

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Uzelac, Lawrence Stevan. "A Multiple Coupled Microstrip Transmission Line Model for High-Speed VLSI Interconnect Simulation." PDXScholar, 1991. https://pdxscholar.library.pdx.edu/open_access_etds/4526.

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A model is presented which incorporates the advantages of a mixed mode simulation to characterize transmission line behavior in multiple coupled Transmission line systems. The model is intended for use by digital circuit designers who wish to be able to obtain accurate transmission line behavior for complex digital systems for which continuous time simulation tools such as SPICE would time prohibitive. The model uses a transverse electromagnetic wave approximation to obtain solutions to the basic transmission line equations. A modal analysis technique is used to solve for the attenuation and propagation constants for the transmission lines. Modal analysis done in the frequency domain after a Fast Fourier Transform of the time-domain input signals. Boundary conditions are obtained from the Thevinized transmission line input equivalent circuit and the transmission line output load impedance. The model uses a unique solution queue system that allows n-line coupled transmission lines to be solved without resorting to large order matrix methods or the need to diagonals larger matrices using linear transformations. This solution queue system is based on the method of solution superposition. As a result, the CPU time required for the model is primarily a function of the number of transitions and not the number of lines modeled. Incorporation of the model into event driven circuit simulators such as Network C is discussed. It will be shown that the solution queue methods used in this model make it ideally suited for incorporation into a event-driven simulation network. The model presented in this thesis can be scaled to incorporate direct electromagnetic coupling between first, second, or third lines adjacent to the line transitioning. It is shown that modeling strictly adjacent line coupling is adequate for typical digital technologies. It is shown that the model accurately reproduces the transmission line behavior of systems modeled by previous authors. Example transitions on a 8-line system are reviewed. Finally, future model improvements are discussed.
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Boijort, Daniel, and Oskar Svanell. "Pulse Width Modulation for On-chip Interconnects." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-6341.

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With an increasing number of transistors integrated on a single die, the need for global on-chip interconnectivity is growing. Long interconnects, in turn, have very large capacitances which consume a large share of a chip’s total power budget.

Power consumption can be lowered in several ways, mainly by reduction of switching activity, reduction of total capacitance and by using low voltage swing. In this project, the issue is addressed by proposing a new encoding based on Pulse Width Modulation (PWM). The implementation of this encoding will both lower the switching activity and decrease the capacitance between nearby wires. Hence, the total effective capacitance will be reduced considerably. Schematic level implementation of a robust transmitter and receiver circuit was carried out in CMOS090, designed for speeds up to 100 MHz. On a 10 mm wire, this implementation would give a 40% decrease in power dissipation compared to a parallel bus having the same metal footprint. The proposed encoding can be efficiently applied for global interconnects in sub-micron systems-on-chip (SoC).

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Rehman, Saif Ur. "Développement des techniques de test et de diagnostic pour les FPGA hiérarchique de type mesh." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT110/document.

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L’évolution tendant à réduire la taille et augmenter la complexité des circuits électroniques modernes, est en train de ralentir du fait des limitations technologiques, qui génèrent beaucoup de d’imperfections et de defaults durant la fabrication ou la durée de vie de la puce. Les FPGAs sont utilisés dans les systèmes numériques complexes, essentiellement parce qu’ils sont reconfigurables et rapide à commercialiser. Pour garder une grande fiabilité de tels systèmes, les FPGAs doivent être testés minutieusement pour les defaults. L’optimisation de l’architecture des FPGAs pour l’économie de surface et une meilleure routabilité est un processus continue qui impacte directement la testabilité globale et de ce fait, la fiabilité. Cette thèse présente une stratégie complète pour le test et le diagnostique des defaults de fabrication des “mesh-based FPGA” contenant une nouvelle topologie d’interconnections à plusieurs niveaux, ce qui promet d’apporter une meilleure routabilité. Efficacité des schémas proposes est analysée en termes de temps de test, couverture de faute et résolution de diagnostique
The evolution trend of shrinking feature size and increasing complexity in modern electronics is being slowed down due to physical limits that generate numerous imperfections and defects during fabrication steps or projected life time of the chip. Field Programmable Gate Arrays (FPGAs) are used in complex digital systems mainly due to their reconfigurability and shorter time-to-market. To maintain a high reliability of such systems, FPGAs should be tested thoroughly for defects. FPGA architecture optimization for area saving and better signal routability is an ongoing process which directly impacts the overall FPGA testability, hence the reliability. This thesis presents a complete strategy for test and diagnosis of manufacturing defects in mesh-based FPGAs containing a novel multilevel interconnects topology which promises to provide better area and routability. Efficiency of the proposed test schemes is analyzed in terms of test cost, respective fault coverage and diagnostic resolution
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Hanchate, Narender. "A game theoretic framework for interconnect optimization in deep submicron and nanometer design." [Tampa, Fla] : University of South Florida, 2006. http://purl.fcla.edu/usf/dc/et/SFE0001523.

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Lopez, Gerald Gabriel. "The impact of interconnect process variations and size effects for gigascale integration." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31781.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.
Committee Chair: Jeffrey A. Davis; Committee Co-Chair: James D. Meindl; Committee Member: Azad J. Naeemi; Committee Member: Dennis W. Hess; Committee Member: George F. Riley; Committee Member: Linda S. Milor. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Tang, Yongbo. "Study on electroabsorption modulators and grating couplers for optical interconnects." Doctoral thesis, KTH, Mikroelektronik och tillämpad fysik, MAP, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-24178.

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Decades of efforts have pushed the replacement of electrical interconnects by optical links to the interconnects between computers, racks and circuit boards. It may be expected that optical solutions will further be used for inter-chip and intra-chip interconnects with potential benefits in bandwidth, capacity, delay, power consumption and crosstalk. Silicon integration is emerging to be the best candidate nowadays due to not only the dominant status of silicon in microelectronics but also the great advantages brought to the photonic integrated circuits (PICs). Regarding the recent breakthroughs concerning active devices on silicon substrate, the question left is no longer the feasibility of the optical interconnects based on silicon but the competitiveness of the silicon device compared with other alternatives. This thesis focuses on the study of two key components for the optical interconnects, both especially designed and fabricated for silicon platform. One is a high speed electroabsorption modulator (EAM), realized by transferring an InP-based segmented design to the hybrid silicon evanescent platform. The purpose here is to increase the speed of the silicon PICs to over 50  Gb/s or more. The other one is a high performance grating coupler, with the purpose to improve the optical interface between the silicon PICs and the outside fiber-based communication system. An general approach based on the transmission line analysis has been developed to evaluate the modulation response of an EAM with a lumped, traveling-wave, segmented or capacitively-loaded configuration. A genetic algorithm is used to optimize its configuration. This method has been applied to the design of the EAMs on hybrid silicon evanescent platform. Based on the comparison of various electrode design, segmented configuration is adopted for the target of a bandwidth over 40 GHz with as low as possible voltage and high extinction ratio. In addition to the common periodic analysis, the grating coupler is analyzed by the antenna theory assisted with an improved volume-current method, where the directionality of a grating coupler can be obtained analytically. In order to improve the performance of the grating coupler, a direct way is to address its shortcoming by e.g. increasing the coupling efficiency. For this reason, a nonuniform grating coupler with apodized grooves has been developed with a coupling efficiency of 64%, nearly a double of a standard one. Another way is to add more functionalities to the grating coupler. To do this, a polarization beam splitter (PBS) based on a bidirectional grating coupler has been proposed and experimentally demonstrated. An extinction ratio of around -20 dB, as well as a maximum coupling efficiency of over 50% for both polarizations, is achieved by such a PBS with a Bragg reflector underneath.
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Books on the topic "Interconnect line"

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New York (State). Legislature. Senate. Standing Committee on Energy and Telecommunications. Public hearing on electric transmission line proposed by New York Regional Interconnect, Inc. New Hartford, N.Y: New York State Legislature, 2006.

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B, Steer M., and Edwards T. C, eds. Foundations of interconnect and microstrip design. 3rd ed. Chichester: John Wiley, 2000.

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McManus, Tom. The Interconnector: The Ireland - United Kingdom Interconnector Project 1990-1993. Dublin: BordGáis, 1994.

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New York (State). Legislature. Senate. Standing Committee on Energy and Telecommunications. Hearing held regarding the New York Regional Interconnect, Inc., proposal. Earlville, N. Y. (1478 Billings Hill Rd, Earlville, N.Y. 13332): Corporate Reporters, 2006.

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International/ICIT, MCS. Gas interconnector project, subsea: Environmental statement on behalf of the Project Management Team. Cork: Bord Gáis Éireann, 1992.

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Ltd, RSK Environment. Gas interconnector project, Irish onshore pipeline: Environmental statement on behalf of the Project Management Team. Cork: Bord Gáis Éireann, 1992.

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Durston, Sarah, and Ton Baggerman. The Universe, Life and Everything. NL Amsterdam: Amsterdam University Press, 2017. http://dx.doi.org/10.5117/9789462987401.

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Our current understanding of our world is nearly 350 years old. It stems from the ideas of Descartes and Newton and has brought us many great things, including modern science and increases in wealth, health and everyday living standards. Furthermore, it is so ingrained in our daily lives that we have forgotten it is a paradigm, not a fact. There are, however, some problems with it. First, there is no satisfactory explanation for why we have consciousness and experience meaning in our lives. Second, modern-day physics tells us that observations depend on characteristics of the observer at the large, cosmic, and small, subatomic scales. Third, ongoing humanitarian and environmental crises show us that our world is vastly interconnected. Our understanding of reality is expanding to incorporate these issues. In The Universe, Life and Everything . . . Dialogues on our Changing Understanding of Reality, some of the scholars at the forefront of this change, from the fields of physics, psychology, and social sciences, discuss the direction it is taking and its urgency.
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Board, Canada National Energy. Reasons for decision in the matter of Sumas Energy 2, Inc: Application dated 7 July 1999, amended 23 October 2000 for the construction and operation of an international power line. Calgary, Alta: National Energy Board Publications Office, 2004.

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United States. Congress. House. Committee on Energy and Commerce. Subcommittee on Energy and Air Quality. Electric transmission policy: Regional transmission organizations, open access, and federal jurisdiction : hearing before the Subcommittee on Energy and Air Quality of the Committee on Energy and Commerce, House of Representatives, One Hundred Seventh Congress, first session, October 10, 2001. Washington: U.S G.P.O., 2001.

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Zell, Michael. Rembrandt, Vermeer, and the Gift in Seventeenth-Century Dutch Art. NL Amsterdam: Amsterdam University Press, 2021. http://dx.doi.org/10.5117/9789463726429.

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Rembrandt, Vermeer, and the Gift in Seventeenth-Century Dutch Art offers a new perspective on the art of the Dutch Golden Age by exploring the interaction between the gift's symbolic economy of reciprocity and obligation and the artistic culture of early modern Holland. Gifts of art were pervasive in seventeenth-century Europe, and many Dutch artists, like their counterparts elsewhere, embraced gift giving to cultivate relations with patrons, art lovers, and other members of their social networks. Rembrandt also created distinctive works to function within a context of gift exchange, and both Rembrandt and Vermeer engaged the ethics of the gift to identify their creative labor as motivated by what contemporaries called a "love of art," not materialistic gain. In the merchant republic’s vibrant market for art, networks of gift relations and the anti-economic rhetoric of the gift mingled with the growing dimension of commerce, revealing a unique chapter in the interconnected history of gift giving and art making.
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Book chapters on the topic "Interconnect line"

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Bainbridge, John. "The Link Layer." In Asynchronous System-on-Chip Interconnect, 41–59. London: Springer London, 2002. http://dx.doi.org/10.1007/978-1-4471-0189-5_5.

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Edwards, T. C., and M. B. Steer. "Parallel-Coupled Lines and Directional Couplers." In Foundations of Interconnect and Microstrip Design, 269–314. West Sussex, England: John Wiley & Sons, Ltd, 2013. http://dx.doi.org/10.1002/9781118894514.ch8.

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Grimm, M., and H. K. Dirks. "Efficient Computation of the Parameters of Parallel Transmission Lines in IC Interconnects." In Interconnects in VLSI Design, 155–79. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4615-4349-7_13.

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Beyene, Wendemagegnehu T., and José E. Schutt-Ainé. "Analysis of Frequency-Dependent Transmission Lines Using Rational Approximation and Recursive Convolution." In Signal Propagation on Interconnects, 1–11. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-6512-0_1.

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Dandoti, Shilpa, and V. D. Mytri. "Switch Line Fault Diagnosis in FPGA Interconnects Using Line Tracing Approach." In Lecture Notes in Electrical Engineering, 425–32. New York, NY: Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-3363-7_48.

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Baglieri, Daniela, and Fabrizio Cesaroni. "Patent Information System in R&D Strategies: Tasks, Techniques and On-line Search Tools." In Management of the Interconnected World, 69–76. Heidelberg: Physica-Verlag HD, 2010. http://dx.doi.org/10.1007/978-3-7908-2404-9_9.

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Ravelo, Blaise. "Symmetric Tree Interconnects Modeling with Elementary Distributed RC-Line." In Analytical Methodology of Tree Microstrip Interconnects Modelling For Signal Distribution, 107–16. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0552-2_6.

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Yamagiwa, Shinichi, Masaaki Ono, Takeshi Yamazaki, Pusit Kulkasem, Masayuki Hirota, and Koichi Wada. "Maestro-link: A high performance interconnect for PC cluster." In Lecture Notes in Computer Science, 421–25. Berlin, Heidelberg: Springer Berlin Heidelberg, 1998. http://dx.doi.org/10.1007/bfb0055273.

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Tampieri, Laura. "The Simulation by Second Life of SMEs Start Up: The Case of New Fashion Perspectives." In Management of the Interconnected World, 259–66. Heidelberg: Physica-Verlag HD, 2010. http://dx.doi.org/10.1007/978-3-7908-2404-9_30.

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Zhou, D., S. Su, F. Tsui, D. S. Gao, and J. S. Cong. "A Simplified Synthesis of Transmission Lines with a Tree Structure." In Modeling and Simulation of High Speed VLSI Interconnects, 19–30. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2718-3_3.

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Conference papers on the topic "Interconnect line"

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Kadoch, Daniel, Michael Duane, and Yohan Lee. "Line length dependencies in interconnect optimization." In Microelectronic Manufacturing, edited by Divyesh N. Patel and Mart Graef. SPIE, 1997. http://dx.doi.org/10.1117/12.284657.

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Nogami, T., R. Patlolla, J. Kelly, B. Briggs, H. Huang, J. Demarest, J. Li, et al. "Cobalt/copper composite interconnects for line resistance reduction in both fine and wide lines." In 2017 IEEE International Interconnect Technology Conference (IITC). IEEE, 2017. http://dx.doi.org/10.1109/iitc-amc.2017.7968961.

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Kim, Andrew T., Tae-Young Jeong, Miji Lee, YoungJoon Moon, SeYoung Lee, BoungJu Lee, and Hyungoo Jeon. "Line Edge Roughness of Metal Lines and Time-Dependent Dielectric Breakdown Characteristics of Low-k Interconnect Dielectrics." In 2007 IEEE International Interconnect Technology Conferencee. IEEE, 2007. http://dx.doi.org/10.1109/iitc.2007.382376.

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Masu, Kazuya, Kenichi Okada, and Hiroyuki Ito. "Transmission line interconnect on Si CMOS LSI." In 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings. IEEE, 2006. http://dx.doi.org/10.1109/icsict.2006.306214.

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Ku, Y. S., D. M. Shyu, P. Y. Chang, and W. T. Hsu. "In-line metrology of 3D interconnect processes." In SPIE Advanced Lithography, edited by Alexander Starikov. SPIE, 2012. http://dx.doi.org/10.1117/12.915810.

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Kang, Qinghua, and Altan M. Ferendeci. "Characterization of Vertical Interconnects in 3-D System in a Package." In ASME 2003 International Electronic Packaging Technical Conference and Exhibition. ASMEDC, 2003. http://dx.doi.org/10.1115/ipack2003-35247.

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A novel RF MEMS integration technology was developed to achieve the three-dimensional integration of microwave and millimeter-wave components and sub-circuits with improved performance using multilayer vertical interconnects. This technology, which allows planar circuits to be monolithically stacked vertically in three dimensions (3D), provides one of the major initial steps in the realization of a “system in a package.” To process high-aspect-ratio via interconnects in 3D MMIC multilayer circuitry, combination of unique microelectronic and traditional MEMS microfabrication technologies were used. Based on these techniques, a set of test structures were successfully fabricated to facilitate the vertical interconnect characterization. Experimental results revealed that at microwave frequencies, e.g. X band (8–12 GHz), the vertical interconnect discontinuities contributed significantly to the insertion loss and the phase change. With the available advanced conductor loss models, lumped-element equivalent circuit models were derived from the via module measurements. Using quarter wavelength T-junction resonator structures, polyimide was also characterized for its microwave properties over a wide frequency range. Multilayer vertically interconnected transmission line circuits were monolithically processed and used to verify the derived electrical models.
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Baert, R., I. Ciofi, Ph Roussel, L. Mattii, P. Debacker, and Zs Tokei. "System-Level Impact of Interconnect Line-Edge Roughness." In 2018 IEEE International Interconnect Technology Conference (IITC). IEEE, 2018. http://dx.doi.org/10.1109/iitc.2018.8430429.

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Jousseaume, V., J. Buckley, Y. Bernard, P. Gonon, C. Vallee, M. Mougenot, H. Feldis, et al. "Back-end-of-line integration approaches for resistive memories." In 2009 IEEE International Interconnect Technology Conference - IITC. IEEE, 2009. http://dx.doi.org/10.1109/iitc.2009.5090335.

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Qing-Tang Jiang, Ming-Hsing Tsai, and R. H. Havemann. "Line width dependence of copper resistivity." In Proceedings of the IEEE 2001 International Interconnect Technology Conference. IEEE, 2001. http://dx.doi.org/10.1109/iitc.2001.930068.

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Jones, Robert E. "Line Width Dependence of Stresses in Aluminum Interconnect." In 25th International Reliability Physics Symposium. IEEE, 1987. http://dx.doi.org/10.1109/irps.1987.362148.

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Reports on the topic "Interconnect line"

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Uzelac, Lawrence. A Multiple Coupled Microstrip Transmission Line Model for High-Speed VLSI Interconnect Simulation. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.6410.

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Frear, D. R., S. N. Burchett, and M. K. Neilsen. Life prediction modeling of solder interconnects for electronic systems. Office of Scientific and Technical Information (OSTI), February 1997. http://dx.doi.org/10.2172/486148.

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Esener, S. C., R. Paturi, and S. H. Lee. Random-Like Interconnects, Fault Tolerance and Grain-Size Studies for Optoelectronic Computing. Fort Belvoir, VA: Defense Technical Information Center, September 1992. http://dx.doi.org/10.21236/ada262360.

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Yarimbiyik, A. Emre, Harry A. Schafft, Richard A. Allen, Mona E. Zaghloul Zaghloul, and David L. Blackburn. Implementation of simulation program for modeling the effective resistivity of nanometer scale film and line interconnects. Gaithersburg, MD: National Institute of Standards and Technology, 2006. http://dx.doi.org/10.6028/nist.ir.7234.

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Shaping the COVID decade: addressing the long-term societal impacts of COVID-19. The British Academy, 2021. http://dx.doi.org/10.5871/bac19stf/9780856726590.001.

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In September 2020, the British Academy was asked by the Government Office for Science to produce an independent review to address the question: What are the long-term societal impacts of COVID-19? This short but substantial question led us to a rapid integration of evidence and an extensive consultation process. As history has shown us, the effects of a pandemic are as much social, cultural and economic as they are about medicine and health. Our aim has been to deliver an integrated view across these areas to start understanding the long-term impacts and how we address them. Our evidence review – in our companion report, The COVID decade – concluded that there are nine interconnected areas of long-term societal impact arising from the pandemic which could play out over the coming COVID decade, ranging from the rising importance of local communities, to exacerbated inequalities and a renewed awareness of education and skills in an uncertain economic climate. From those areas of impact we identified a range of policy issues for consideration by actors across society, about how to respond to these social, economic and cultural challenges beyond the immediate short-term crisis. The challenges are interconnected and require a systemic approach – one that also takes account of dimensions such as place (physical and social context, locality), scale (individual, community, regional, national) and time (past, present, future; short, medium and longer term). History indicates that times of upheaval – such as the pandemic – can be opportunities to reshape society, but that this requires vision and for key decisionmakers to work together. We find that in many places there is a need to start afresh, with a more systemic view, and where we should freely consider whether we might organise life differently in the future. In order to consider how to look to the future and shape the COVID decade, we suggest seven strategic goals for policymakers to pursue: build multi-level governance; improve knowledge, data and information linkage and sharing; prioritise digital infrastructure; reimagine urban spaces; create an agile education and training system; strengthen community-led social infrastructure; and promote a shared social purpose. These strategic goals are based on our evidence review and our analysis of the nine areas of long-term societal impact identified. We provide a range of illustrative policy opportunities for consideration in each of these areas in the report that follows.
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