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Dissertations / Theses on the topic 'Interconnect line'
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Shah, Chintan Hemendra. "Inductively Coupled Interconnect for Chip to Chip Communication over Transmission Line." NCSU, 2009. http://www.lib.ncsu.edu/theses/available/etd-04012009-003531/.
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As data frequency increases beyond several Gbps range, low power chip to chip communication becomes more critical. The concept researched in this thesis is inductively coupled interconnect (LCI) over short length transmission line. The data will be transmitted across a 10 cm differential microstrip line on FR-4 material with a transformer on each side of the line. The transmitter and receiver circuits are designed in TSMC 0.18μm process technology and can operate at 2.5 Gbps. The power consumption of the design is 5.53 mW at 2.5 Gbps which yields around 2.21 mW.Gb-1.s-1. This design can achieve BER of less than 10-12. The inductive coupling will reduce DC power because the low frequency DC component of the signal will be blocked by coupling inductors. The power consumed by this design is lower than most of the conventional I/Os that use physical contact interconnects. An H-bridge current steering driver is used at the transmitter and a differential amplifier and Sense-amp Flip flop is used at the receiver.
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Wikström, Adam. "Modeling of stresses and deformation in thin film and interconnect line structures." Doctoral thesis, KTH, Solid Mechanics, 2001. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3224.
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Wikström, Adam. "Modeling of stresses and deformation in thin film and interconnect line structures /." Stockholm : Tekniska högsk, 2001. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3224.
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Gao, Youxin. "Interconnect optimization in deep sub-micron design under the transmission line model." Digital version:, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p9992795.
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Uzelac, Lawrence Stevan. "A Multiple Coupled Microstrip Transmission Line Model for High-Speed VLSI Interconnect Simulation." PDXScholar, 1991. https://pdxscholar.library.pdx.edu/open_access_etds/4526.
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A model is presented which incorporates the advantages of a mixed mode simulation to characterize transmission line behavior in multiple coupled Transmission line systems. The model is intended for use by digital circuit designers who wish to be able to obtain accurate transmission line behavior for complex digital systems for which continuous time simulation tools such as SPICE would time prohibitive. The model uses a transverse electromagnetic wave approximation to obtain solutions to the basic transmission line equations. A modal analysis technique is used to solve for the attenuation and propagation constants for the transmission lines. Modal analysis done in the frequency domain after a Fast Fourier Transform of the time-domain input signals. Boundary conditions are obtained from the Thevinized transmission line input equivalent circuit and the transmission line output load impedance. The model uses a unique solution queue system that allows n-line coupled transmission lines to be solved without resorting to large order matrix methods or the need to diagonals larger matrices using linear transformations. This solution queue system is based on the method of solution superposition. As a result, the CPU time required for the model is primarily a function of the number of transitions and not the number of lines modeled. Incorporation of the model into event driven circuit simulators such as Network C is discussed. It will be shown that the solution queue methods used in this model make it ideally suited for incorporation into a event-driven simulation network. The model presented in this thesis can be scaled to incorporate direct electromagnetic coupling between first, second, or third lines adjacent to the line transitioning. It is shown that modeling strictly adjacent line coupling is adequate for typical digital technologies. It is shown that the model accurately reproduces the transmission line behavior of systems modeled by previous authors. Example transitions on a 8-line system are reviewed. Finally, future model improvements are discussed.
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Boijort, Daniel, and Oskar Svanell. "Pulse Width Modulation for On-chip Interconnects." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-6341.
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With an increasing number of transistors integrated on a single die, the need for global on-chip interconnectivity is growing. Long interconnects, in turn, have very large capacitances which consume a large share of a chip’s total power budget.
Power consumption can be lowered in several ways, mainly by reduction of switching activity, reduction of total capacitance and by using low voltage swing. In this project, the issue is addressed by proposing a new encoding based on Pulse Width Modulation (PWM). The implementation of this encoding will both lower the switching activity and decrease the capacitance between nearby wires. Hence, the total effective capacitance will be reduced considerably. Schematic level implementation of a robust transmitter and receiver circuit was carried out in CMOS090, designed for speeds up to 100 MHz. On a 10 mm wire, this implementation would give a 40% decrease in power dissipation compared to a parallel bus having the same metal footprint. The proposed encoding can be efficiently applied for global interconnects in sub-micron systems-on-chip (SoC).
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Rehman, Saif Ur. "Développement des techniques de test et de diagnostic pour les FPGA hiérarchique de type mesh." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT110/document.
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L’évolution tendant à réduire la taille et augmenter la complexité des circuits électroniques modernes, est en train de ralentir du fait des limitations technologiques, qui génèrent beaucoup de d’imperfections et de defaults durant la fabrication ou la durée de vie de la puce. Les FPGAs sont utilisés dans les systèmes numériques complexes, essentiellement parce qu’ils sont reconfigurables et rapide à commercialiser. Pour garder une grande fiabilité de tels systèmes, les FPGAs doivent être testés minutieusement pour les defaults. L’optimisation de l’architecture des FPGAs pour l’économie de surface et une meilleure routabilité est un processus continue qui impacte directement la testabilité globale et de ce fait, la fiabilité. Cette thèse présente une stratégie complète pour le test et le diagnostique des defaults de fabrication des “mesh-based FPGA” contenant une nouvelle topologie d’interconnections à plusieurs niveaux, ce qui promet d’apporter une meilleure routabilité. Efficacité des schémas proposes est analysée en termes de temps de test, couverture de faute et résolution de diagnostiqueThe evolution trend of shrinking feature size and increasing complexity in modern electronics is being slowed down due to physical limits that generate numerous imperfections and defects during fabrication steps or projected life time of the chip. Field Programmable Gate Arrays (FPGAs) are used in complex digital systems mainly due to their reconfigurability and shorter time-to-market. To maintain a high reliability of such systems, FPGAs should be tested thoroughly for defects. FPGA architecture optimization for area saving and better signal routability is an ongoing process which directly impacts the overall FPGA testability, hence the reliability. This thesis presents a complete strategy for test and diagnosis of manufacturing defects in mesh-based FPGAs containing a novel multilevel interconnects topology which promises to provide better area and routability. Efficiency of the proposed test schemes is analyzed in terms of test cost, respective fault coverage and diagnostic resolution
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Hanchate, Narender. "A game theoretic framework for interconnect optimization in deep submicron and nanometer design." [Tampa, Fla] : University of South Florida, 2006. http://purl.fcla.edu/usf/dc/et/SFE0001523.
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Lopez, Gerald Gabriel. "The impact of interconnect process variations and size effects for gigascale integration." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31781.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.Committee Chair: Jeffrey A. Davis; Committee Co-Chair: James D. Meindl; Committee Member: Azad J. Naeemi; Committee Member: Dennis W. Hess; Committee Member: George F. Riley; Committee Member: Linda S. Milor. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Tang, Yongbo. "Study on electroabsorption modulators and grating couplers for optical interconnects." Doctoral thesis, KTH, Mikroelektronik och tillämpad fysik, MAP, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-24178.
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Decades of efforts have pushed the replacement of electrical interconnects by optical links to the interconnects between computers, racks and circuit boards. It may be expected that optical solutions will further be used for inter-chip and intra-chip interconnects with potential benefits in bandwidth, capacity, delay, power consumption and crosstalk. Silicon integration is emerging to be the best candidate nowadays due to not only the dominant status of silicon in microelectronics but also the great advantages brought to the photonic integrated circuits (PICs). Regarding the recent breakthroughs concerning active devices on silicon substrate, the question left is no longer the feasibility of the optical interconnects based on silicon but the competitiveness of the silicon device compared with other alternatives. This thesis focuses on the study of two key components for the optical interconnects, both especially designed and fabricated for silicon platform. One is a high speed electroabsorption modulator (EAM), realized by transferring an InP-based segmented design to the hybrid silicon evanescent platform. The purpose here is to increase the speed of the silicon PICs to over 50 Gb/s or more. The other one is a high performance grating coupler, with the purpose to improve the optical interface between the silicon PICs and the outside fiber-based communication system. An general approach based on the transmission line analysis has been developed to evaluate the modulation response of an EAM with a lumped, traveling-wave, segmented or capacitively-loaded configuration. A genetic algorithm is used to optimize its configuration. This method has been applied to the design of the EAMs on hybrid silicon evanescent platform. Based on the comparison of various electrode design, segmented configuration is adopted for the target of a bandwidth over 40 GHz with as low as possible voltage and high extinction ratio. In addition to the common periodic analysis, the grating coupler is analyzed by the antenna theory assisted with an improved volume-current method, where the directionality of a grating coupler can be obtained analytically. In order to improve the performance of the grating coupler, a direct way is to address its shortcoming by e.g. increasing the coupling efficiency. For this reason, a nonuniform grating coupler with apodized grooves has been developed with a coupling efficiency of 64%, nearly a double of a standard one. Another way is to add more functionalities to the grating coupler. To do this, a polarization beam splitter (PBS) based on a bidirectional grating coupler has been proposed and experimentally demonstrated. An extinction ratio of around -20 dB, as well as a maximum coupling efficiency of over 50% for both polarizations, is achieved by such a PBS with a Bragg reflector underneath.QC 20100906
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Stangl, Marcel. "Charakterisierung und Optimierung elektrochemisch abgeschiedener Kupferdünnschichtmetallisierungen für Leitbahnen höchstintegrierter Schaltkreise." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2008. http://nbn-resolving.de/urn:nbn:de:bsz:14-ds-1218567869996-80674.
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Die Entwicklung der Mikroelektronik wird durch eine fortschreitende Miniaturisierung der Bauelemente geprägt. Infolge einer Reduzierung der Querschnittflächen von Leitbahnstrukturen erhöht sich die elektrische Leistungsdichte und das Metallisierungssystem bestimmt zunehmend die Übertragungsgeschwindigkeiten. Kupfer repräsentiert hierbei das verbreitetste Leitbahnmaterial und wird vorwiegend mittels elektrochemischer Abscheidung in vergrabene Damaszen-Strukturen eingebracht. Die vorliegende Dissertation beschreibt Möglichkeiten für eine Optimierung von Kupferleitbahnen für höchstintegrierte Schaltkreise. Von besonderem Interesse sind hierbei die Gefügequalität und der Reinheitsgrad. Es erfolgen umfangreiche werkstoffanalytische und elektrochemische Untersuchungen zur Charakterisierung von Depositionsmechanismen, des Einbaus von Fremdstoffen, des Mikrogefüges nach der Abscheidung und der Mikrogefügeumwandlung. In einem abschließenden Forschungsschwerpunkt werden Kupfer-Damaszen-Teststrukturen mit unterschiedlichen Gehalten nichtmetallischer Verunreinigungen hergestellt und entsprechenden Lebensdauerexperimenten unterzogen. Hierdurch gelingt eine Evaluierung des Einflusses jener Verunreinigungen auf die Elektromigrationsbeständigkeit von Kupferleitbahnen. Die Arbeit umfasst daher das gesamte Spektrum von der Grundlagenforschung bis zur Applikation von elektrochemisch abgeschiedenen Kupferdünnschichtmetallisierungen.
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Stangl, Marcel. "Charakterisierung und Optimierung elektrochemisch abgeschiedener Kupferdünnschichtmetallisierungen für Leitbahnen höchstintegrierter Schaltkreise." Doctoral thesis, Technische Universität Dresden, 2007. https://tud.qucosa.de/id/qucosa%3A23688.
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Die Entwicklung der Mikroelektronik wird durch eine fortschreitende Miniaturisierung der Bauelemente geprägt. Infolge einer Reduzierung der Querschnittflächen von Leitbahnstrukturen erhöht sich die elektrische Leistungsdichte und das Metallisierungssystem bestimmt zunehmend die Übertragungsgeschwindigkeiten. Kupfer repräsentiert hierbei das verbreitetste Leitbahnmaterial und wird vorwiegend mittels elektrochemischer Abscheidung in vergrabene Damaszen-Strukturen eingebracht. Die vorliegende Dissertation beschreibt Möglichkeiten für eine Optimierung von Kupferleitbahnen für höchstintegrierte Schaltkreise. Von besonderem Interesse sind hierbei die Gefügequalität und der Reinheitsgrad. Es erfolgen umfangreiche werkstoffanalytische und elektrochemische Untersuchungen zur Charakterisierung von Depositionsmechanismen, des Einbaus von Fremdstoffen, des Mikrogefüges nach der Abscheidung und der Mikrogefügeumwandlung. In einem abschließenden Forschungsschwerpunkt werden Kupfer-Damaszen-Teststrukturen mit unterschiedlichen Gehalten nichtmetallischer Verunreinigungen hergestellt und entsprechenden Lebensdauerexperimenten unterzogen. Hierdurch gelingt eine Evaluierung des Einflusses jener Verunreinigungen auf die Elektromigrationsbeständigkeit von Kupferleitbahnen. Die Arbeit umfasst daher das gesamte Spektrum von der Grundlagenforschung bis zur Applikation von elektrochemisch abgeschiedenen Kupferdünnschichtmetallisierungen.
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Percey, Andrew K. (Andrew Kenneth). "Analysis and modeling of capacitive coupling along metal interconnect lines." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/39067.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.Includes bibliographical references (leaf 87).
by Andrew K. Percey.
M.Eng.
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Teo, Yu Xian. "Modelling of interconnects including coaxial cables and multiconductor lines." Thesis, University of Nottingham, 2013. http://eprints.nottingham.ac.uk/13832/.
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In recent years, electromagnetic compatibility (EMC) problems associated with high frequency and high speed interconnects are becoming of increasing concern. Coaxial cables are a popular form of interconnect. In this thesis, the crosstalk coupling between two parallel coaxial cables in free space and above a ground plane is investigated. The degree of coupling is usually formulated analytically in the frequency domain. In this thesis, a method for time domain simulation is proposed using the TLM technique. Results are compared with frequency domain solutions and experimental results. Also; the standard model has been improved by including the skin depth effect in the coaxial cable braid. The crosstalk between the two coaxial cables is observed through the induced voltages on the loads of the adjacent cable, which is deemed to be the usual measureable form of cable coupling. The equivalent circuit developed for the coupling path of two coaxial cables in free space takes account of the differential mode (DM) current travelling in the braids of the cables. As for the coupling path of the cables via a ground plane, the equivalent circuit is developed based on the flow of differential mode (DM) and common mode (CM) currents in the braid, where the coaxial braid’s transfer impedance is modelled using Kley’s model. The radiated electric (E) field from the coaxial cable above a ground plane is also deduced from the predicted cable sheath current distribution and by the Hertzian dipoles’ approach. Results are validated against the radiated electric field of a single copper wire above ground. Both the simulated and experimental results are presented in the time and frequency domains and good agreement is observed thus validating the accuracy of the model.
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Rajasekaran, Vinod. "Power delivery in systems with lossy cables or interconnects." Diss., Available online, Georgia Institute of Technology, 2003:, 2003. http://etd.gatech.edu/theses/available/etd-11252003-095456/unrestricted/rajasekaranvinod200312phd.pdf.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2004.Dr. Bonnie S. Heck, Committee Chair; David G. Taylor, Committee Member; Thomas. G. Habetler, Committee Member; Linda M. Wills, Committee Member; Eric Johnson, Committee Member. Includes bibliography.
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Yao, Ziwen. "Régulateur adaptatif robuste pour les liaisons de transport a courant continu en haute tension." Vandoeuvre-les-Nancy, INPL, 1993. http://www.theses.fr/1993INPL051N.
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Cette thèse présente un ensemble de méthodes de synthèse du contrôle commande adaptatif robuste dans le domaine fréquentiel pour les liaisons de transport à courant continu en haute tension destine à améliorer la stabilité en basse fréquence du réseau. Cet ensemble de méthodes consiste en une méthode de modélisation des réseaux d'interconnexion, une méthode d'analyse de stabilité pour les réseaux d'interconnexion, une approche d'identification des réseaux électriques et une approche de synthèse du régulateur adaptatif-robuste. La méthode de simplification de modélisation des réseaux d'interconnexion est fondée sur des propriétés algébriques: l'y-symétrie et la possibilité de découplage de la matrice de caractéristiques de fréquence des réseaux. Basé sur ces propriétés et sur le critère de stabilité de Nyquist généralisé, un critère de stabilité est proposé pour les réseaux d'interconnexion. L'approche d'identification des réseaux électriques est fondée sur ces propriétés algébriques et est réalisée à l'aide de la transformation de Fourier. Afin de montrer les avantages ainsi que les inconvénients des méthodes proposées cette thèse est illustrée par différents résultats de simulation numérique. Dans ces simulations numériques sont étudiés les phénomènes d'interaction torsionnelle entre la liaison TCCHT IFA 2000 et les turboalternateurs voisins
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Ghouali, Noureddine. "Optimisation en ligne des systemes interconnectes en etat statique." Nantes, 1988. http://www.theses.fr/1988NANT2026.
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Presentation et mise en oeuvre de quelques methodes basees sur les techniques duales, dans lesquelles le coordonnateur doit determiner le vecteur prix, fonction de la difference entre les interactions calculees et mesurees. On propose une extension de cette technique a une large classe de problemes non convexes en introduisant l'approche par penalite deplacee
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Caputa, Peter. "Efficient high-speed on-chip global interconnects." Doctoral thesis, Linköping, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7123.
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Lo, George Chih-Yu. "Electroplated Compliant High-Density Interconnects For Next-Generation Microelectronic Packaging." Thesis, Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4778.
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Dramatic advances are taking place in the microelectronic industry. The feature size continues to scale down and it is expected that the minimum feature size on the integrated circuit is expected to reach 9 nm by 2016, and there will be more than 8 billion transistors on a 310 cm² chip, according to various available roadmaps. Subsequently, this reduction in feature size would require the first-level input-output interconnects to decrease in pitch size to meet the increased number of transistors on the chip. Also, to minimize the on-chip interconnect delay, development of low-K dielectric/copper will become increasingly common in future devices. However, due to the low fracture strength of low-K dielectric, it is essential that the first-level interconnects exert minimal force on the die pads and therefore, do not crack or delaminate the low-K dielectric material. It is also preferable to have a wafer-level packaging approach to facilitate test-and-burn in and to produce known-good dies. Based on these growing demands from the microelectronics industry, there is a compelling need to develop innovative interconnect technologies.
This thesis aims to develop one such innovative interconnect — G-Helix interconnect. G-Helix is a scalable lithography-based wafer-level electroplated compliant interconnect that has the potential to meet the fine-pitch first-level chip-to-substrate interconnect requirements. The three-mask fabrication of G-Helix is based on lithography, electroplating and molding (LIGA-like) technologies, and this fabrication can be easily integrated into large-area wafer-level fine-pitch batch processing. In this work, the fabrication, assembly, experimental reliability testing, and numerical physics-based modeling of the G-Helix interconnects will be presented.
The fabrication of the interconnects will be demonstrated at 100μm pitch on a 20 x 20 mm die in a class 10/1000 cleanroom facility. The wafers with compliant interconnects will be singulated into individual dies and assembled on substrates using Pb/Sn eutectic solder. The assembly will then be subjected to air-to-air thermal cycling between 0℃and 100℃ and the reliability of the compliant interconnect will be assessed. In addition to the thermo-mechanical reliability testing, some of the dies with free-standing interconnects will also be used for measuring the compliance of the interconnects by compressing with a nanoindenter. In parallel to the experimental research, a numerical analysis study will also be carried out. The numerical model will use direction-, temperature, time-dependent, and time independent material constitutive properties as appropriate. The thermo-mechanical fatigue life of the compliant interconnect assembly will be determined and compared with the experimental data. Recommendations will be developed for further enhancement of reliability and reduction in pitch size.
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Hopkins, Glenn Daniel. "Empirical characterization of a plated-through-hole interconnect for a multilayer stripline assembly at microwave frequencies." Thesis, Georgia Institute of Technology, 1991. http://hdl.handle.net/1853/15658.
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You, Hong. "Modeling of lossy multiconductor transmission lines for the design of high-speed IC interconnects /." Thesis, Connect to this title online; UW restricted, 1990. http://hdl.handle.net/1773/5864.
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Bi, Tianshu. "Distributed intelligent system for on-line fault section estimation of large-scale power networks." Click to view the E-thesis via HKUTO, 2002. http://sunzi.lib.hku.hk/hkuto/record/B42576714.
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畢天姝 and Tianshu Bi. "Distributed intelligent system for on-line fault section estimation oflarge-scale power networks." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2002. http://hub.hku.hk/bib/B42576714.
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Lin, Chien-Min. "Efficiently computational techniques for solving large-scale electromagnetic problems microstrip interconnects and rough surface scattering /." Thesis, Connect to this title online; UW restricted, 1998. http://hdl.handle.net/1773/5878.
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Habtay, Yehdego Tekeste. "Advanced static VAr compensator for direct on line starting of induction motors in an interconnected offshore power system." Thesis, Heriot-Watt University, 2002. http://hdl.handle.net/10399/371.
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Spencer, Todd Joseph. "Air-gap transmission lines on printed circuit boards for chip-to-chip interconnections." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/34754.
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Low-loss off-chip interconnects are required for energy-efficient communication in dense microprocessors. To meet these needs, air cavity parallel plate and microstrip lines with copper conductors were fabricated on an FR-4 epoxy-fiberglass substrate using conventional microelectronics manufacturing techniques. Copper transmission lines were separated by a composite dielectric of air and Avatrel 2000P and by a dielectric layer of air only. The composite dielectric lines were characterized to 10 GHz while the all air dielectric lines were characterized to 40 GHz. The transmission line structures showed loss as low 1.5 dB/cm at 40 GHz with an effective dielectric constant below 1.4. These novel structures show low loss in the dielectric due to the reduced relative permittivity and loss tangent introduced by the air cavity.
Transmission line structures with a composite dielectric were built by coating the sacrificial polymer poly(propylene carbonate) (PPC) over a copper signal line, encapsulating with an overcoat polymer, electroplating a ground line, and decomposing PPC to form an air cavity. The signal and ground wires were separated by a layer of 15 µm of air and 20 µm of Avatrel 2000P. Air cavity formation reduced dielectric constant more than 30 percent and loss of less than 0.5 dB/cm was measured at 10 GHz.
Residue from PPC decomposition was observed in the cavity of composite dielectric structures and the decomposition characteristics of PPC were evaluated to characterize the residue and understand its formation. Analysis of PPC decomposition based on molecular weight, molecular backbone structure, photoacid concentration and vapor pressure, casting solvent, and decomposition environment was performed using thermogravimetric analysis and extracting kinetic parameters.
Novel interaction of copper and PPC was observed and characterized for the self-patterning of PPC on copper. Copper is dissolved from the surface during PPC spincoating and interacts with the polymer chains to improve stability. The improved thermal stability allows selective patterning of PPC on copper. Decomposition characteristics, residual metals analysis, and diffusion profile were analyzed. The unique interaction could simplify air-gap processing for transmission lines.
Inorganic-organic hybrid polymers were characterized for use as overcoat materials. Curing characteristics of the monomers and mechanical properties of the polymer films were analyzed and compared with commercially available overcoat materials. The modulus and hardness of these polymers was too low for use as an air-gap overcoat, but may be valuable as a barrier layer for some applications.
The knowledge gained from building transmission line structures with a composite dielectric, analyzing PPC decomposition, interaction with copper, and comparison of hybrid polymers with commercial overcoats was used to build air-gap structures with improved electrical design. The ground metal was separated from the signal only by air. The signal wire was supported from above using 60 µm of Avatrel 8000P as an overcoat. Structures showed loss of less than 1.5 dB/cm at 40 GHz, the lowest reported value for a fully encapsulated transmission line structure.
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Pasha, Soheila. "Electromagnetic Modeling of High-Speed Interconnects with Frequency Dependent Conductor Losses, Compatible with Passive Model Order Reduction Techniques." Diss., The University of Arizona, 2012. http://hdl.handle.net/10150/268354.
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A computationally efficient, discrete model is presented for transmission line analysis and passive model order reduction of high-speed interconnect systems. The development of this model was motivated by the on-going efforts in chip/package co-design to route a major portion of the on-chip clock and high-speed data buses through the package in order to overcome the bandwidth reduction and delay caused by the high ohmic loss of on-chip wiring. The geometric complexity of the resulting interconnections is such that model order reduction is essential for rapid and accurate signal integrity assessment to support pre-layout design iteration and optimization. The modal network theory of the skin effect in conjunction with the theory of compact differences is used for the development of discrete models for dispersive, multi-conductor interconnects compatible with passive model order reduction algorithms. The passive reduced-order interconnect modeling algorithm, PRIMA, is then used on the resulting discrete model to generate a low-order, multi-port macromodel for interconnect networks. Numerical examples are used to demonstrate the validity and efficiency of the proposed model.
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Boudjema, Cédric. "La fonction éducative des musées dans la société numérique : analyse comparative de l'offre pédagogique en ligne de huit musées nationaux dans quatre pays (France, Angleterre, Australie, Etats-Unis)." Thesis, Lille 3, 2016. http://www.theses.fr/2016LIL30013/document.
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Cette thèse porte sur les sites internet des musées et plus particulièrement les sections pédagogiques de huit institutions nationales de quatre pays différents et s’attache à montrer que les musées sont, en ligne, des acteurs de contenus pédagogiques. L’enjeu est d’étudier les sections pédagogiques de ces sites en privilégiant une analyse de contenu et en mettant en œuvre une démarche comparative entre les quatre pays et les types de sites internet afin de saisir les pratiques - et notamment ce que Jean Davallon a appelé « l’anticipation par le destinateur » de ce que fera le visiteur (le destinateur visant par exemple à retenir l’intention de ce dernier ou à le guider dans le contenu), la typologie des contenus, les stratégies pédagogiques mises en œuvre par les institutions muséales en ligne. L’offre pédagogique en ligne est ici définie comme une activité permanente à distance de critiques, de construction de savoirs, de consultation et de divertissement, à propos des ressources muséales. Cette offre se construit également selon des règles cohérentes de design Web. Nous avons choisi d’étudier la pédagogie en ligne autrement selon une démarche constructiviste qui nous conduit à privilégier certains concepts clés : parcours d’apprentissage individualisés, processus d’apprentissage, stratégies cognitives, stratégies métacognitives, « learning styles », taxonomie. D’un point de vue méthodologique, cette thèse s’appuie sur une démarche qualitative et privilégie l’analyse de contenu à partir d’une grille d’analyse comportant 11 catégories : le corpus se compose de huit sites internet et de deux types de musées nationaux : les musées d’art et les musées de sciences avec une section pédagogique. La thèse se compose en deux tomes. Le tome 2 contient l’analyse complète des sites et le tome 1 comporte trois parties. Dans une première partie, la thèse se concentre sur la vocation éducative des musées en prenant en compte ses spécificités et ses complexités. Cette partie précise le contexte historique de la fonction éducative des musées qui ont très tôt développé une stratégie pédagogique en direction du public. Elle s’attache aussi à montrer la spécificité du musée dans l’éducation informelle en le situant en tant que lieu d’apprentissage de concepts et de développement qui développe deux types de médiation. Le musée favorise la formulation de questions, il oriente la réflexion et suscite des interrogations. Elle montre ensuite le musée en tant que partenaire important et complémentaire de l’école. Enfin, cette partie précise le contexte historique des musées en ligne dans les quatre pays de notre analyse et le développement progressif des politiques culturelles d'aujourd’hui et les actions progressives mises en opération par les musées. Dans un second temps, la thèse porte sur l’analyse thématique des sites internet et de leurs sections pédagogiques et s’attache à montrer les étapes successives de l'analyse de contenu via la grille d’analyse conçue pour cette recherche. Dans un premier, temps, il s’agit donc de présenter l’ergonomie générale des sites pour progressivement arriver au traitement général des sections pédagogiques des sites c’est à dire d’identifier les mécanismes sous jacents des sites internet et de leurs sections pédagogiques et dans un second temps d’identifier les différences entre les types de musées et les pays. Enfin, la troisième partie de la thèse attache de l’importance à la typologie des contenus pédagogiques en ligne et se focalise sur les stratégies mises en œuvre sur les sites ainsi que sur la pédagogie déployée. Les sites internet sont ainsi vus comme des éléments interconnectés, destinés à un public cible et renforçant le rôle social du musée. Les publics scolaires et les enseignants sont publics privilégiées, une place prépondérante à ces publics est soulignéeThis research studies museum internet sites and in particular the pedagogy of eight national institutions in four different countries and suggests that online museums are educational content players.The interest is to investigate the educational content of the internet sites using a content analysis and implementing a comparison between the four countries and the types of internet sites to be able to understand the practices – and especially what Jean Davallon calls « the anticipation by the “sender” » that the visitor will engage in (the sender aiming for example to keep the attention of the latter or to provide guidance in the contents), the typology of content and the teaching strategies put in place by the online museum institutions. The online educational offer is defined here as a permanent activity as a source of building knowledge, consultation, criticism, and entertainment, from the museum resources. This offer is also constructed according to the consistent rules of Web design.We have chosen to study the online pedagogy according to a constructivist approach that drives us to privilege certain key concepts : individual learning ways, learning processes, cognitive strategies, meta-cognitive strategies, {learning styles}, taxonomy. From a methodological point of view, this thesis relies on a qualitative approach and privileges a content analysis from an analysis grid with eleven categories : the corpus is composed of eight internet sites and of two types of national museums : the art museums and the science museums with an educational section. The thesis is composed of two tomes. The tome 2 contains the complete analysis of the sites and the tome 1 includes three parts. In the first part, the research discusses the educational role of museums with its specificities and complexities. This part defines the historical context of the educational function of museums that very early on developed an educational strategy for the public. It also shows the specificity of museums in informal education as a place of learning concepts and development that develop two types of mediation. The museum favours the formulation of questions; it orientates reflexion and raises questions. It then shows the museum as an important partner and complementary to school. Finally, this part precises the historical context of online museums of the four countries from our analysis and the progressive development of the cultural policies of the present and the progressive actions put into place by the museums.Secondly, the research focuses on the thematic analysis of the internet sites and on their educational sections and attempts to show the successive steps of the content analysis via the analysis grid constructed for this research. Firstly, it is about showing the ergonomics of the sites to progressively arrive upon the general treatment of the educational sections of the sites, that is to say to identify the mechanisms of underlying internet sites and of their educational sections and secondly to identify the differences between the types of museums and their countries. Finally, the third part of the research attaches importance to the typology of the online educational content and focuses on the strategies put into place in the sites as well as the pedagogy deployed. The internet sites are thus viewed as interconnected elements, intended for a target audience and reinforcing the social role of the museum. The schools and the teaching body are a privileged population; a prominent place for them is underlined
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Akour, Amneh M. "Design Techniques for Manufacturable 60GHz CMOS LNAs." The Ohio State University, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=osu1306443049.
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Tmimi, Mohammed. "Nouvelle approche pour lien série en technologie FD-SOI 28 nm CMOS avancée et au-delà." Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT079.
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Dans le cadre de l’échange massif de données numériques, la solution du lien série est largement utilisée dans les systèmes électroniques. Dans ce cadre, il existe une course permanente pour accroître le débit de transfert de données. Notamment les efforts portent sur l’amélioration de l’efficacité énergétique du système et l’optimisation des canaux de transmission. Cependant la contrainte physique du canal de transmission est une donnée majeure dans cette approche de transmission de données à haut débit.Les méthodes standard de transmission intra-puces point à point utilisent la bande de base, le délai de transmission dans cette bande se situe autour de 40 ps/mm, acceptable pour des distances courtes inférieures au mm. Or, pour un lien de quelques mm, la solution standard d’utiliser des routeurs n’est plus optimale quant à la consommation et au temps de transfert dus à la propagation du signal en bande de base. En conséquence, un changement de paradigme est nécessaire afin de réduire ce délai.Aujourd’hui, les recherches sont très actives concernant l’intégration monolithique de lien série, ce qui permet d’avoir une excellente base de concepts et de solutions. Dans la littérature, on note ainsi plusieurs solutions, la principale étant la transmission sans-fil intra-puces « wireless on-chip (WiNOC) », où des antennes intra-puces sont utilisées pour transmettre les données. On peut également noter l’utilisation de l’optoélectronique pour transmettre avec un délai minimal. Il en résulte un changement de processus.Dans ce travail, on vise les liens de quelques mm de long, où aucune des solutions précédentes n’est optimale, soit à cause du temps de propagation soit à cause de la complexité de l’implémentation due au changement du procédé. Cette solution est complémentaire aux solutions existantes et nous pensons qu’elle permet de résoudre certains de leurs problèmes et prolonger la durée de vie des architectures réseau sur puces (NoC) existantes.On investigue la transmission en bande millimétrique (à 60 GHz) où la vitesse de propagation du signal est autour de 1,5.10^8 m/s, impliquant un délai minimal (7 ps/mm). Par ailleurs, différentes modulations seront investiguées pour augmenter le débit et exploiter efficacement les bandes passantes disponibles à ces fréquences. On a choisi la modulation duobinaire pour son avantage en termes de compression du spectre, ce qui nous a permis de doubler le débit utilisé pour une même bande passante, ainsi que pour sa simplicité de modulation/démodulation. Dans notre cas, on utilise 5 GHz de bande pour transmettre un signal de 10 Gbps.Cette approche théorique a été modélisée pour ensuite la comparer aux différents systèmes à l’état de l’art ; un débit maximal de 14 Gbps a été atteint avec un taux d’erreur inférieur a 10^(-12) en simulation. Un démonstrateur sur silicium à 10 Gbps a été conçu sur la base de la technologie CMOS avancée 28 nm FD-SOI de STMicroelectronics. Le transmetteur, le récepteur ainsi que des lignes de propagation d’une longueur de 4.6 mm ont été implémentés, les résultats de mesures seront publiées dans de futurs travaux. Les simulations ont montré que nous avons atteint un débit plus élevé (au moins le double) que l’état de l’art, pour une surface plus faible et une efficacité énergétique comparable.Nous avons également proposé d'utiliser la même approche pour les canaux d’interposeurs afin de connecter des chiplets avec un délai minimal. Nous étudions son application pour un interposeur passif en silicium en technologie BiCMOS 130 nm, mais il peut également être utilisé pour les circuits actifs. Nous avons connecté deux puces en technologie 28 nm FD-SOI à une distance de 7 mm et obtenu un taux d’erreur binaire inférieur à 10^(-12) avec une latence de 7 ps / mm en simulationThe global internet traffic exceeded the zettabyte marker in 2016. Since then, internet traffic proliferated with a compound annual growth rate of 26%; and is expected to continue its astronomical growth rate. This perpetual growth has significant implications for networking technologies. Researchers anticipated their limits and managed to stay ahead of the curve by innovating and optimizing all data transfer levels. In that context, this work focuses on on-chip data transfer, acknowledging that communication energy efficiency is one of the integrated circuits near future bottlenecks, as the gap between the computation energy and on-die IC energy grows.Evidently, improvements have to be made to the existing links solutions; higher data rates must be reached while considering the energy efficiency and the circuit complexity. Furthermore, with the increasing data rates, signal integrity problems arise due to channel imperfections. Although transistor scaling provided higher density packing of devices and faster transistors, it did not benefit the interconnections performance since it resulted in higher wires density. Wires are more sensitive to their environment than active devices, that is, closer wires are more sensible to crosstalk and longer delay due to the wire's intrinsic delay. Delay is a critical metric for data transmission. In this work, we developed a high data-rate low delay solution for long-range on-chip serial links. The developed solution is complementary to the massively employed existing solutions. We believe it will help solve some of their issues and extend the existing Network on chips architectures lifetime.We start this work by introducing the standard and emerging on-chip interconnect solutions, then discussing their advantages and challenges. The chosen RF interconnects technique is most suitable for our requirements, mainly due to low delay, high available bandwidths, and CMOS process compatibility/friendliness. This approach requires transmitting the data at high frequencies instead of the baseband, that is, up-converting the data signal before transmitting it through the transmission lines. In practice, transmission lines behave differently at baseband and high-frequencies. In particular, both distortion and delay are much lower at high-frequencies. These two properties are essential for our work; low distortion implies that high signal integrity is reached without equalization or error-correcting codes, up to 14 Gbps in the proposed study. At least four times lower than baseband delay, the high-frequency low delay property signifies that long distances across the chip can be crossed in less time.We believe this approach is most beneficial for distances longer than a couple of mm and up to twentieth mm.Bandwidth at higher frequencies (60 GHz in our case) is a valuable commodity. To take full advantage of it, we used duobinary modulation to double the data rate. This spectrum compression relaxes the RF components constraints such as linearity; The chosen modulation simplifies the demodulation where a simple envelope detector is used to recover the data.A 10 Gbps prototype chip was designed and fabricated in the advanced 28 nm FD-SOI technology from STMicroelectronics. In this work, we explained the design process of the transceiver (composed of a transmitter, a receiver, and a 4.6mm channel). The simulation results showed that we reached a higher data rate (at least double) than the state of the art, for a smaller area and a comparable energy efficiency. The post-layout simulation resulted in a BER lower than 10^(-12). The measurement results will be published in future works.We also proposed to use the same approach for interposer channels to connect chiplets with minimal delay. We study its application for a 130 nm BiCMOS technology passive silicon interposer. We connected two 28 nm FD-SOI chiplets at a 7-mm distance and achieved a BER lower than 10^(-12) with a 7 ps/mm delay in simulations
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Lábsky, Balázs. "Metody analýzy přenosových struktur v časové oblasti." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-218020.
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This work deals with techniques of time-domain analysis of interconnects. After a studying crucial issue of time-domain analysis of interconnects methods of modeling and simulation simple interconnects in electrotechnics are described. For transient effect analysis two elementary methods can be used: the state variable method and the FDTD (Finite - Difference Time - Domain) method. The FDTD method can be used to solve partial differential equations in time domain, for instance equations of transmission lines. The method is very effective and delivers satisfactory results in case of linear and non-linear lines with a single “live” conductor. The method can be easily programmed in Matlab.
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Ševčík, Břetislav. "Metody optimalizace pro zajištění integrity signálů pro vysokorychlostní přenos dat mezi čipy." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-263351.
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Tato disertační práce je obsahově zaměřená na problematiku integrity signálů v moderních čipových obvodech. Na základě provedených simulací a praktických experimentů byl proveden návrh equalizační techniky druhého řádu pro efektivnější vysokorychlostní komunikaci. Předložený návrh respektuje současné požadavky na vyvíjené signalizační techniky, které zahrnují efektivnější využití šířky pásma přenosového kanálu a energetickou úsporu. Provedené analýzy podrobně ukazují možnost zvýšení přenosové rychlosti při přenosu signálu skrz nízkonákladové přenosové kanály s využitím navržené signální metody. Výkonnost navrhované signalizační techniky je demonstrována na různých typech přenosových kanálů s přenosovou funkcí vyššího řádu. Diskutovány jsou rovněž možnosti omezení rušivých vlivů na přenosové kanály během návrhu.
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Fu-XiangLiang and 梁富翔. "Impact of Line-Edge-Roughness on Interconnect RC for Advanced Technology Nodes." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/tr2gt6.
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Chao, Chuan-Jane, and 趙傳珍. "Analysis, Design, and Modeling of Inductor and Interconnect Transmission Line for Silicon Technology." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/22045727951810831781.
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博士國立交通大學
電子工程系
90
The characteristics of Si IC spiral inductors and transmission lines are analyzed. The complete characterization and new models of s-parameters, inductance value, and quality factor of a single spiral inductor, as well as coupling effect of coplanar spiral inductors are presented. Some enhancement methods by layout design are introduced and examined for improving the inductor performance. A novel methodology with correlative test structures is addressed for the determination of the conventional RC-based model regarding the interconnection parasitic parameters. Frequency-dependent characterizations and parameters extraction are carried out to investigate the Telegrapher’s equation in terms of transmission line model parameters (R, L, G, and C), loss, and coupling effects in silicon technologies.
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(9337943), Chun-Li Lo. "Applications of Two-Dimensional Layered Materials in Interconnect Technology." Thesis, 2020.
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Copper (Cu) has been used as the main conductor in interconnects due to its low resistivity. However, because of its high diffusivity, diffusion barriers/liners (tantalum nitride/tantalum; TaN/Ta) must be incorporated to surround Cu wires. Otherwise, Cu ions/atoms will drift/diffuse through the inter-metal dielectric (IMD) that separates two distinct interconnects, resulting in circuit shorting and chip failures. The scaling limit of conventional Cu diffusion barriers/liners has become the bottleneck for interconnect technology, which in turn limits the IC performance. The interconnect half-pitch size will reach ~20 nm in the coming sub-5 nm technology nodes. Meanwhile, the TaN/Ta (barrier/liner) bilayer stack has to be > 4 nm to ensure acceptable liner and diffusion barrier properties. Since TaN/Ta occupy a significant portion of the interconnect cross-section and they are much more resistive than Cu, the effective conductance of an ultra-scaled interconnect will be compromised by the thick bilayer. Therefore, two dimensional (2D) layered materials have been explored as diffusion barrier alternatives owing to their atomically thin body thicknesses. However, many of the proposed 2D barriers are prepared at too high temperatures to be compatible with the back-end-of-line (BEOL) technology. In addition, as important as the diffusion barrier properties, the liner properties of 2D materials must be evaluated, which has not yet been pursued.
The objective of the thesis is to develop a 2D barrier/liner that overcomes the issues mentioned. Therefore, we first visit various 2D layered materials to understand their fundamental capability as barrier candidates through theoretical calculations. Among the candidates, hexagonal-boron-nitride (h-BN) and molybdenum disulfide (MoS2) are selected for experimental studies. In addition to studying their fundamental properties to know their potential, we have also developed techniques that can realize low-temperature-grown 2D layered materials. Metal-organic chemical vapor deposition (MOCVD) is adopted for the synthesis of BEOL-compatible MoS2. The electrical test results demonstrate the promises of integrating 2D layered materials to the state-of-the-art interconnect technology. Furthermore, by considering not only diffusion barrier properties but also liner properties, we develop another 2D layered material, tantalum sulfide (TaSx), using plasma-enhanced chemical vapor deposition (PECVD). The TaSx is promising in both barrier and liner aspects and is BEOL-compatible. Therefore, we believed that the conventional TaN/Ta bilayer stack can be replaced with an ultra-thin TaSx layer to maximize the Cu volume for ultra-scaled interconnects and improve the performance. Furthermore, Since via resistance has become the bottleneck for overall interconnect performance, we study the vertical conduction of TaSx. Both the intrinsic and extrinsic properties of this material are investigated and engineering approaches to improve the vertical conduction are also tested. Finally, we explore the possibilities of benefiting from 2D materials in other applications and propose directions for future studies.
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Chen, Yen-hsun, and 陳彥勛. "Three Dimensions Interconnect Investigation of System In Package and Equivalent Long Transmission Line by Modify-T Model." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/71600605912782123357.
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碩士國立高雄大學
電機工程學系碩士班
98
Recently, face the high replacement of products and the pressure of taking new products into market in time, the designers need to shorten the used time. The engineer need to design high performance electronic products within limited time. We need to accomplish many circuit interconnects in a small Printed Circuit Board. This reason make much more complicated and difficult situations. The designers not only consider circuit interconnect but also consider circuit performance. In this thesis, the first part is three dimensions interconnect investigation of system in package. We analyse the discontinue effect of transfer layer and compare traditional via model with via model established in this thesis. We also study via structure to improve SSN.The second part is the equivalent long transmission line by Modify-T Model. The chip of Modify-T Model equivalent long microstrip line are 3cm,3cm+3cm,and 6cm.We compare the area and the difference of the performance.
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Li, Ling Y. "Efficient analysis of interconnect networks with frequency dependent lossy transmission lines." 2005. http://hdl.handle.net/1993/18061.
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Kim, Jooyong. "Parameter extraction and characterization of transmission line interconnects based on high frequency measurement." Thesis, 2006. http://hdl.handle.net/2152/2909.
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(8815964), Minsuk Koo. "Energy Efficient Neuromorphic Computing: Circuits, Interconnects and Architecture." Thesis, 2020.
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Neuromorphic computing has gained tremendous interest because of its ability to overcome the limitations of traditional signal processing algorithms in data intensive applications such as image recognition, video analytics, or language translation. The new computing paradigm is built with the goal of achieving high energy efficiency, comparable to biological systems.
To achieve such energy efficiency, there is a need to explore new neuro-mimetic devices, circuits, and architecture, along with new learning algorithms. To that effect, we propose two main approaches:
First, we explore an energy-efficient hardware implementation of a bio-plausible Spiking Neural Network (SNN). The key highlights of our proposed system for SNNs are 1) addressing connectivity issues arising from Network On Chip (NOC)-based SNNs, and 2) proposing stochastic CMOS binary SNNs using biased random number generator (BRNG). On-chip Power Line Communication (PLC) is proposed to address the connectivity issues in NOC-based SNNs. PLC can use the on-chip power lines augmented with low-overhead receiver and transmitter to communicate data between neurons that are spatially far apart. We also propose a CMOS 'stochastic-bit' with on-chip stochastic Spike Timing Dependent Plasticity (sSTDP) based learning for memory-compressed binary SNNs. A chip was fabricated in 90 nm CMOS process to demonstrate memory-efficient reconfigurable on-chip learning using sSTDP training.
Second, we explored coupled oscillatory systems for distance computation and convolution operation. Recent research on nano-oscillators has shown the possibility of using coupled oscillator networks as a core computing primitive for analog/non-Boolean computations. Spin-torque oscillator (STO) can be an attractive candidate for such oscillators because it is CMOS compatible, highly integratable, scalable, and frequency/phase tunable. Based on these promising features, we propose a new coupled-oscillator based architecture for hybrid spintronic/CMOS hardware that computes multi-dimensional norm. The hybrid system composed of an array of four injection-locked STOs and a CMOS detector is experimentally demonstrated. Energy and scaling analysis shows that the proposed STO-based coupled oscillatory system has higher energy efficiency compared to the CMOS-based system, and an order of magnitude faster computation speed in distance computation for high dimensional input vectors.
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"An investigation of interconnect geometry and fatigue life of ball-grid array electronic packages." Tulane University, 1999.
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A model for the shapes and residual forces for an individual, axisymmetric BGA solder interconnect is developed from the basic assumption that the surface bounding the solder possesses constant mean curvature. The inputs for the model include: pad radius, stand-off height, and the volume of the solder. The model is contrasted with simpler ones to identify the combinations of parameters for which more relaxed assumptions regarding the shape of the interconnect (e.g., a cylinder, truncated sphere, or circular arc meridian) may lead to unacceptable errors when designing for the demanding requirements of aerospace applications. The parameter combinations include situations when there exists a large stand-off height in conjunction with residual tension in the interconnect and when there is considerable tension or compression in the interconnect. The errors can be especially significant if one is designing around presumed surface contact angles at the solder/pad/PCB junction The results of this model are incorporated into a fatigue life analysis for BGA packages. In the aerospace industry the fatigue loading on the individual interconnects is Mode II shearing due to cyclic temperatures. A fracture mechanics approach is taken which accounts for this Mode II fatigue loading as well as a constant Mode I loading that is due to the residual forces arising from the surface tension within the molten interconnect. This model, which is referred to as the relative life model, is capable of demonstrating how the relative fatigue life of an interconnect can be altered as a result of a change in the residual force (and, therefore, the shape) of the interconnect. The model is capable of capturing this relationship for variable joint dimensions (i.e., volumes, stand-off heights, radii), service loading, and material constituents (i.e., solder alloys, PCBs, and IC carriers). For an array of pads of known radii, a procedure is presented for determining the optimal volumes of each solder joint so as to optimize the relative life of the entire packageacase@tulane.edu
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Huang, Ren-Hong, and 黃仁鴻. "Selective Formation of Carbon Nanotube-like Structures by Laser Direct Writing for Nano-interconnect Application." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/71035032807599466626.
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碩士國立清華大學
材料科學工程學系
97
This research is to form high-density, high-conductivity carbon nanotube-like (CNT-like) structures for nano-interconnect application. The effect of amorphous carbon (a-C) characteristics on CNT-like formation was investigated by using C2H2 or CH4 as a reaction gas for a-C deposition with various C2H2/H2 and CH4/H2 ratios. Besides, the feasibility of selective CNT-like structures formation from the a-C film with patterned catalysts underneath was studied so as to form the nano-interconnect composed of insulating a-C and conducting CNT-like structures. In this research, 248 nm KrF excimer laser light was exposed on the substrates with a-C(30 nm)/Ni(10 nm)/Ti(10 nm) on top for 10 s at 1 Hz to form CNT-like structures. Higher quality of CNT-like structures is achieved at laser energy density ramped from 46 mJ/cm2 to 36 mJ/cm2 gradually. The effect of a-C characteristics on the formation of CNT-like structures was investigated at laser condition as above. It was found that C2H2-deposited a-C films were more suitable for formation of CNT-like structures. Increasing the C2H2/H2 ratio can also improve the quality and adhesion of CNT-like structures on substrates. The a-C films with patterned Ni/Ti catalyst underneath were deposited on SiO2/Si to verify the feasibility of forming CNT-like structures selectively by laser direct writing for the formation of nano-interconnect consisting of insulating a-C and conducting CNT-like structures.
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Shu, Huang, and 黃淑津. "Course of interconnected system of the life field to the first grade students." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/23987461489481470998.
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碩士國立中正大學
教育研究所
93
This study using the action research researches the whole course of interconnected system of the life field to the first grade students who study in a explore class of a wonderful elementary school. And, the purposes of the study are： 1. Probe into questions that happened at the whole course of interconnected system of the life field to the first grade students and carry on situation analysis. 2. Seek to partners carrying the action research out. 3. Draw a project of action research to solve the questions that happened at the whole course of interconnected system of the life field to the first grade students. 4. Explore the progress by carrying out a project of action research. 5. Comment and give the feedback to the result of developing the project of action research to solve the questions that happened at the whole course of interconnected system of the life field to the first grade students. This research is in accordance with finding and making into the following conclusions mainly: 1. Question that whole course of interconnected system of first grade primary school life field encounters, analyze in accordance with the situation that finds, there are six respects, such as community's characteristic, school nature, teacher , student , parents , teaching equipment ,etc. separately. 2. Invite and carry on action research in coordination with the cooperative partner, share, inspect the effect that takes action to study with the professional gains, and reach the function that the specialty improves. 3. Probe into through documents, according to the develop stage of students’ intelligence specialty, and whether teaching material object experience, Department's book edition designs, selects the interconnected system of the theme whole, grind and plan to strengthen the course scheme, in thinking and revising constantly, plan the whole action scheme of interconnected system of two course themes. 4. Implementation course of whole course of interconnected system of the first grade primary school life field, implement through four respects, such as diversified teaching activities, abundant study teaching material, building the educational environment of life, establishing the cooperation with parents, etc. separately. 5. Comment the ancient bronze mirror and feedback the whole result of developing the action scheme of course of interconnected system of the first grade primary school life field, including students' cognition, affection, movement technical ability are in the effect that students study. Finally, according to the conclusion of this research, to wanting to implement three directions, such as whole course school of interconnected system of the first grade primary school life field, wanting to implement the whole course teacher of interconnected system of the first grade primary school life field and follow-up study, etc., propose the concrete suggestion for your guidance. Keywords：course of life field, course interconnected system are whole , whole course of interconnected system, action research
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LIN, SHU-HSUAN, and 林書玄. "Development of 20-Gbps Silicon-Based Transmission Lines and Its Application to Board-to-Board Optical Interconnect Modules." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/10194552445634415329.
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碩士國立中央大學
光電科學與工程學系
101
The research of this thesis is first proposed that the 20-Gbps high-frequency transmission line is integrated into silicon optical bench (SiOB), and applied to board-to-board optical interconnect module. The high-frequency transmission line could be high-frequency signal line to connect among active components, like vertical-cavity surface-emitting laser (VCSEL), photo-detector (PD), driver integrated circuit (IC) of transmitter, and transimpedance amplifier (TIA) of receiver. The above components would be integrated into the SiOB to be a high-speed board-to-board optical interconnect module, and the high-speed optical signal would coupled into ribbon fiber via 45° Si-based optical micro-reflector of SiOB. In the packaging approaches, the VCSEL and PD were assembled by flip-chip bonding method and the driver IC and TIA were assembled by wire bonding method to connect with transmission line. In order to evaluate and analyze the characteristics of transmission line, the scattering parameters (S-parameters) of passive circuit with single-ended and differential transmission lines would be measured, respectively. These transmission lines were designed based on the coplanar waveguide structure. The return loss and insertion loss of single-ended transmission line at 50-GHz were -30.5dB and -0.15dB, respectively. The differential transmission line was operated at 40-GHz, which had return loss of -20.12 dB and insertion loss of -0.28 dB. For high-frequency characteristics of board-to-board optical interconnect module, the clear eye diagram is operated with data rate of 20-Gbps and the bit error rate (BER) of receiver can be achieved the level of 10-12. The results are confirmed the design of 20-Gbps high-frequency transmission lines can be integrated into SiOB, and apply to board-to-board optical interconnect module with transmissive level as high as 20-Gbps.
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Shin, Jinhong 1972. "Growth and characterization of CVD Ru and amorphous Ru-P alloy films for liner application in Cu interconnect." Thesis, 2007. http://hdl.handle.net/2152/3684.
Full textAbstract:
Copper interconnect requires liner materials that function as a diffusion barrier, a seed layer for electroplating, and an adhesion promoting layer. Ruthenium has been considered as a promising liner material, however it has been reported that Ru itself is not an effective Cu diffusion barrier due to its microstructure, which is polycrystalline with columnar grains. The screening study of Ru precursors revealed that all Ru films were polycrystalline with columnar structure, and, due to its strong 3D growth mode, a conformal and ultrathin Ru film was difficult to form, especially on high aspect ratio features. The microstructure of Ru films can be modified by incorporating P. Amorphous Ru(P) films are formed by chemical vapor deposition at 575 K using a single source precursor, cis-RuH₂(P(CH₃)₃)₄, or dual sources, Ru₃(CO)₁₂ and P(CH₃)₃ or P(C6H5)₃ The films contain Ru and P, which are in zero-valent states, and C as an impurity. Phosphorus dominantly affects the film microstructure, and incorporating > 13% P resulted in amorphous Ru(P) films. Metastable Ru(P) remains amorphous after annealing at 675 K for 3 hr, and starts recrystallization at ~775 K. The density of states analysis of the amorphous Ru(P) alloy illustrates metallic character of the films, and hybridization between Ru 4d and P 3p orbitals, which contributes to stabilizing the amorphous structure. Co-dosing P(CH)₃ with Ru₃(CO)₁₂ improves film step coverage, and the most conformal Ru(P) film is obtained with cis-RuH2(P(CH₃)₃)₄; a fully continuous 5 nm Ru(P) film is formed within 1 µm deep, 8:1 aspect ratio trenches. First principles density functional theory calculations illustrate degraded Cu/Ru adhesion by the presence of P at the interface, however, due to the strong Ru-Cu bonds, amorphous Ru(P) forms a stronger interface with Cu than Ta and TaN do. Cu diffusion studies at 575 K suggests improved barrier property of amorphous Ru(P) films over polycrystalline PVD Ru.
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Peng, Che-Hsuan, and 彭哲瑄. "Design of Transmission Lines for 4-Channel × 25-Gbps Optical Interconnect Module Based on Optical Flexible Printed Circuit." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/92564094448962900254.
Full textAbstract:
碩士國立中央大學
光電科學與工程學系
105
In this paper, the 4-channel 25-Gbps high-frequency transmission line is integrated into the flexible circuit board. This design is used as a high frequency transmission line between a receiver-side photodetector, a transimpedance amplifier (TIA) and a transmitter-side Vertical Cavity Surface Emitting Laser (VCSEL), and an integrated driver chip.And then the above elements and polymer waveguide and 45˚ reflective surface common integration in the flexible circuit board. This paper evaluates and analyzes high frequency transmission lines for use on flexible circuit boards, including the single-ended transmission line and differential transmission line of the return loss and insertion loss. The transmission lines are designed in the form of a coplanar waveguide. Through the high frequency simulation, the operating frequency of 0 ~ 62.5GHz The single-ended transmission line return loss of the transmitter and the receiver is less than -4 dB, the insertion loss is above -2.8 dB. On the other hand, in the operating frequency of 0 ~ 62.5 GHz, the differential transmission line return loss is less than -6 dB, insertion loss are more than -1.7 dB.
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"Fatigue life prediction of solder interconnects in area-array microelectronic packages and the effects of underfill." Tulane University, 2004.
Find full textAbstract:
High cycle vibration fatigue tests are performed on Ball Grid Array (BGA) packages employing a specially designed Cyclic Controlled Curvature Cantilever Device (C4D) and an imaging system in which a stroboscope is used with an optical sensor to freeze the vibration of the critical solder interconnect in BGA specimens. The failure mode is identified as crack initiation and propagation on the component side along the nickel/solder interface. A primary crack starts from the inner edge, progressing stably until the secondary crack begins on the opposite edge. The crack growth is then accelerated till the complete crack has been formed. Averagely, the time spent in crack initiation, stable propagation and accelerated crack propagation are about 15%, 60% and 25%, respectively. Vibration tests at various frequencies were also performed. The cycles to failure is found to be frequency-independent from 50 Hz to 100 Hz Several commonly used fatigue life-prediction models, such as Solomon's model and Paris' law, are examined based on failure parameters computed from nonlinear finite element analysis. It is found that while the damage models usually show large discrepancy, the fracture model can correlate with the test data within a factor of 1.5 The High Sensitivity Moire Interferometry method is also used to capture the mechanical response in the BGA three-point bending and Flip Chip four-point bending tests. Both packages come in two forms: with and without underfill. The influence of underfill is shown to be obvious Underfill curing-induced shrinkage problem is investigated using a unit cell finite element model comprised of solder and underfill in cylindrical shape. A two-phase solution scheme is utilized: The shrinkage is modeled in the first phase by introducing a thermal contraction to the underfill; the solder is allowed to creep based on a hyperbolic creep law in the second phase for 1000 hours. A compressive residual steady state stress in the solder interconnects can be reached within several weeks time. This compressive stress can extend the fatigue life of solder interconnects undergoing Mode II cyclic shear according to a relative life model proposed by Larson and Verges (2003)acase@tulane.edu
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"Accelerated Life testing of Electronic Circuit Boards with Applications in Lead-Free Design." Doctoral diss., 2012. http://hdl.handle.net/2286/R.I.14570.
Full textAbstract:
abstract: This dissertation presents methods for addressing research problems that currently can only adequately be solved using Quality Reliability Engineering (QRE) approaches especially accelerated life testing (ALT) of electronic printed wiring boards with applications to avionics circuit boards. The methods presented in this research are generally applicable to circuit boards, but the data generated and their analysis is for high performance avionics. Avionics equipment typically requires 20 years expected life by aircraft equipment manufacturers and therefore ALT is the only practical way of performing life test estimates. Both thermal and vibration ALT induced failure are performed and analyzed to resolve industry questions relating to the introduction of lead-free solder product and processes into high reliability avionics. In chapter 2, thermal ALT using an industry standard failure machine implementing Interconnect Stress Test (IST) that simulates circuit board life data is compared to real production failure data by likelihood ratio tests to arrive at a mechanical theory. This mechanical theory results in a statistically equivalent energy bound such that failure distributions below a specific energy level are considered to be from the same distribution thus allowing testers to quantify parameter setting in IST prior to life testing. In chapter 3, vibration ALT comparing tin-lead and lead-free circuit board solder designs involves the use of the likelihood ratio (LR) test to assess both complete failure data and S-N curves to present methods for analyzing data. Failure data is analyzed using Regression and two-way analysis of variance (ANOVA) and reconciled with the LR test results that indicating that a costly aging pre-process may be eliminated in certain cases. In chapter 4, vibration ALT for side-by-side tin-lead and lead-free solder black box designs are life tested. Commercial models from strain data do not exist at the low levels associated with life testing and need to be developed because testing performed and presented here indicate that both tin-lead and lead-free solders are similar. In addition, earlier failures due to vibration like connector failure modes will occur before solder interconnect failures.Dissertation/Thesis
Ph.D. Industrial Engineering 2012
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Palaniappan, Arun. "Modeling, Optimization and Power Efficiency Comparison of High-speed Inter-chip Electrical and Optical Interconnect Architectures in Nanometer CMOS Technologies." Thesis, 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8618.
Full textAbstract:
Inter-chip input-output (I/O) communication bandwidth demand, which rapidly scaled with integrated circuit scaling, has leveraged equalization techniques to operate reliably on band-limited channels at additional power and area complexity. High-bandwidth inter-chip optical interconnect architectures have the potential to address this increasing I/O bandwidth. Considering future tera-scale systems, power dissipation of the high-speed I/O link becomes a significant concern. This work presents a design flow for the power optimization and comparison of high-speed electrical and optical links at a given data rate and channel type in 90 nm and 45 nm CMOS technologies.
The electrical I/O design framework combines statistical link analysis techniques, which are used to determine the link margins at a given bit-error rate (BER), with circuit power estimates based on normalized transistor parameters extracted with a constant current density methodology to predict the power-optimum equalization architecture, circuit style, and transmit swing at a given data rate and process node for three different channels. The transmitter output swing is scaled to operate the link at optimal power efficiency. Under consideration for optical links are a near-term architecture consisting of discrete vertical-cavity surface-emitting lasers (VCSEL) with p-i-n photodetectors (PD) and three long-term integrated photonic architectures that use waveguide metal-semiconductor-metal (MSM) photodetectors and either electro-absorption modulator (EAM), ring resonator modulator (RRM), or Mach-Zehnder modulator (MZM) sources. The normalized transistor parameters are applied to jointly optimize the transmitter and receiver circuitry to minimize total optical link power dissipation for a specified data rate and process technology at a given BER.
Analysis results shows that low loss channel characteristics and minimal circuit complexity, together with scaling of transmitter output swing, allows electrical links to achieve excellent power efficiency at high data rates. While the high-loss channel is primarily limited by severe frequency dependent losses to 12 Gb/s, the critical timing path of the first tap of the decision feedback equalizer (DFE) limits the operation of low-loss channels above 20 Gb/s. Among the optical links, the VCSEL-based link is limited by its bandwidth and maximum power levels to a data rate of 24 Gb/s whereas EAM and RRM are both attractive integrated photonic technologies capable of scaling data rates past 30 Gb/s achieving excellent power efficiency in the 45 nm node and are primarily limited by coupling and device insertion losses. While MZM offers robust operation due to its wide optical bandwidth, significant improvements in power efficiency must be achieved to become applicable for high density applications.
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Alcheikh-Hamoud, Khaled. "MODELISATION DES GRANDS SYSTEMES ELECTRIQUES INTERCONNECTES : APPLICATION A L'ANALYSE DE SECURITE DANS UN ENVIRONNEMENT COMPETITIF." Phd thesis, 2010. http://tel.archives-ouvertes.fr/tel-00477583.
Full textAbstract:
La restructuration du secteur de l'énergie électrique et la dérégulation du marché de l'électrécité, les contraintes environnementales et dans certains cas des investissements insuffisants dans les infrastructures des systèmes électriques forment actuellement les principaux facteurs qui poussent les opérateurs des systèmes électriques à faire fonctionner ces derniers dans des conditions opérationnelles contraignantes, à savoir de plus en plus près de leurs limites de stabilité. En effet, afin de pouvoir exploiter leurs réseaux électriques avec des marges de sécurité réduites sans détérioration significative de la sûreté de fonctionnement, les gestionnaires des réseaux de transport (GRTs) ont récemment adopté un nouvel outil pour se prémunir contre le risque des pannes généralisées (blackouts) des réseaux électriques. Il s'agit de l'analyse en ligne de sécurité. A l'heure actuelle, en l'absence d'un coordinateur de sécurité central ou d'échanges complets de données en ligne entre tous les GRTs, l'analyse en ligne de sécurité des grands systèmes électriques interconnectés se fait d'une manière décentralisée au niveau du GRT de chaque zone de réglage. Le problème majeur de l'analyse décentralisée des systèmes interconnectés réside dans le fait que chaque GRT n'est pas capable d'évaluer la vulnérabilité de son système à l'égard des contingences externes originaires des zones de réglage voisines. Dans cette thèse, nous proposons comme solution à ce problème un nouveau cadre de coopération et de coordination entre les GRTs. Dans ce cadre, les GRTs s'échangent en ligne et hors ligne les données nécessaires permettant à chacun d'entre eux premièrement d'évaluer l'impact de ses contingences externes sur la sécurité de sa zone, deuxièmement de concevoir, en utilisant des techniques d'apprentissage automatique, des filtres qu'il utilise ensuite en ligne pour le filtrage rapide de ses contingences externes de sorte que seules les contingences externes potentiellement dangereuses soient sélectionnées pour une analyse détaillée en ligne.