Journal articles: 'Interconnect line'

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Majumder, Manoj Kumar, Nisarg D. Pandya, B. K. Kaushik, and S. K. Manhas. "Signal Integrity Analysis in Single and Bundled Carbon Nanotube Interconnects." Journal of Nanoscience 2013 (August 4, 2013): 1–6. http://dx.doi.org/10.1155/2013/407301.

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Carbon nanotube (CNT) can be considered as an emerging interconnect material in current nanoscale regime. They are more promising than other interconnect materials such as Al or Cu because of their robustness to electromigration. This research paper aims to address the crosstalk-related issues (signal integrity) in interconnect lines. Different analytical models of single- (SWCNT), double- (DWCNT), and multiwalled CNTs (MWCNT) are studied to analyze the crosstalk delay at global interconnect lengths. A capacitively coupled three-line bus architecture employing CMOS driver is used for accurate estimation of crosstalk delay. Each line in bus architecture is represented with the equivalent RLC models of single and bundled SWCNT, DWCNT, and MWCNT interconnects. Crosstalk delay is observed at middle line (victim) when it switches in opposite direction with respect to the other two lines (aggressors). Using the data predicted by ITRS 2012, a comparative analysis on the basis of crosstalk delay is performed for bundled SWCNT/DWCNT and single MWCNT interconnects. It is observed that the overall crosstalk delay is improved by 40.92% and 21.37% for single MWCNT in comparison to bundled SWCNT and bundled DWCNT interconnects, respectively.

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Kahng, Andrew B., Sudhakar Muddu, and Egino Sarto. "Tuning Strategies for Global Interconnects in High-Performance Deep-Submicron ICs." VLSI Design 10, no. 1 (January 1, 1999): 21–34. http://dx.doi.org/10.1155/1999/38974.

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Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of line thicknesses, widths and spacings in multi-layer interconnect to simultaneously optimize signal distribution, signal performance, signal integrity, and interconnect manufacturability and reliability. This is a key activity in most leading-edge design projects, but has received little attention in the literature. Our work provides the first technology-specific studies of interconnect tuning in the literature. We center on global wiring layers and interconnect tuning issues related to bus routing, repeater insertion, and choice of shielding/spacing rules for signal integrity and performance. We address four basic questions. (1) How should width and spacing be allocated to maximize performance for a given line pitch? (2) For a given line pitch, what criteria affect the optimal interval at which repeaters Should be inserted into global interconnects? (3) Under what circumstances are shield wires the optimum technique for improving interconnect performance? (4) In global interconnect with repeaters, what other interconnect tuning is possible? Our study of question (4) demonstrates a new approach of offsetting repeater placements that can reduce worst-case cross-chip delays by over 30% in current technologies.

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List, R. Scott, Abha Singh, Andrew Ralston, and Girish Dixit. "Integration of Low-k Dielectric Materials Into Sub-0.25-μm Interconnects." MRS Bulletin 22, no. 10 (October 1997): 61–69. http://dx.doi.org/10.1557/s0883769400034229.

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As the dimensions of ultralarge-scale-integration devices scale to smaller feature sizes and larger die dimensions, the resistance-capacitance (RC) delay of the metal interconnect will increasingly limit the performance of high-speed logic chips. This is because the transistor capacitance and resistance both scale to lower values as the feature size is reduced, while both the line-to-line capacitance and resistance of the metal-interconnect lines increase as their dimensions decrease. For interconnects 5-mm long, the crossover feature size at which the interconnect delay dominates the transistor delay is approximately 0.5 μm. Since this interconnect RC delay increases roughly quadratically with decreasing feature size versus the historical quadratic reduction in transistor delay, device designers currently face difficult barriers to continued performance increases with scaling. Figure 1 presents the components of the RC delay for a single-transistor/single-interconnect combination with 0.35-μm feature sizes. The total delay can be broken into four additive components: the transistor delay R0C0, the interconnect delay rLcL, and the two transistor/interconnect cross terms where R0 and C0 are the transistor resistance and capacitance, r and c are the specific resistance and capacitance, and L is the interconnect length. As can be seen for interconnect lengths less than about 100-μm long, the intrinsic transistor delay dominates. However for interconnect lengths between approximately 100 μm and 10 mm, the resistance of the transistor coupled with the capacitance of the interconnect dominates the combined delay, resulting in a linear increase in delay with increasing line length.

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O'Reilly, Michael, Michael J. Renn, and Stephen Barnes. "Aerosol Jet Printer as an Alternative to Wire Bond and TSV Technology for 3D Interconnect Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (January 1, 2011): 001250–68. http://dx.doi.org/10.4071/2011dpc-wa11.

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Optomec's Aerosol Jet print platform provides an evolutionary alternative to both wire bond and TSV technology, providing high density 3-dimensional interconnect capabilities which enable multi-functional integrated circuits to be stacked and vertically interconnected in high performance System-in-Package (SiP) solutions. The die stacks can include 8 or more die, with a total stack height of ~ 1 mm. The printing system has a working distance of several mm which means that no Z-height adjustments are required for the interconnect printing. Closely coupled pneumatic atomizers with multiplexed print nozzles are used to achieve production throughput of greater than 15,000 interconnects per hour. The Aerosol Jet deposits silver nanoparticle ink connections on staggered multi-chip die stacks. High aspect ratio interconnects with <30-micron line width and 6-micron line heights have been demonstrated at sub 60-micron pitches with resistivity <1x10−7 ohm*m. Pre-production yields exceeding 80% have been consistently realized. This paper will be further expanded to include pre-production qualification results, final production packaging, and further definition of the Aerosol Jet print platform integrated within a high throughput, manufacturing ready automation solution.

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Praveen Kumar, Ch, E. Sreenivasa Rao, and P. Chandra Sekhar. "Novel Approach to Analyze Crosstalk for a Multi-Line Bus System at 32-nm Technology." Journal of Circuits, Systems and Computers 29, no. 13 (March 3, 2020): 2050216. http://dx.doi.org/10.1142/s0218126620502163.

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This research paper presents a novel approach to analyze the crosstalk-induced delay of multi-layered graphene nanoribbon (MLGNR) and multi-walled carbon nanotube (MWCNT) interconnects. A multi-line driver-interconnect-load (DIL) system is employed to analyze the crosstalk-induced delay for different switching transitions. The interconnect lines of the proposed DIL are said to be operated by either a resistive or a CMOS, or a CNFET driver for different switching transitions at 32-nm technology. Using the unique CNFET driver, the victim line of the multi-level MLGNR/MWCNT-based bus system experiences a delay almost 57.25% and 31.62% lesser in comparison to a resistive driver and a CMOS interconnect driver, respectively. Additionally, the overall worst-case delays are reduced by 89.45% and 98.98% for MLGNR in comparison to an equivalent MWCNT at 100[Formula: see text][Formula: see text]m and 1,000[Formula: see text][Formula: see text]m interconnect lengths, respectively.

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Murthy, N. S., and M. Kavicharan. "A Survey on FDTD-Based Interconnect Modeling." Journal of Circuits, Systems and Computers 24, no. 01 (November 10, 2014): 1530001. http://dx.doi.org/10.1142/s0218126615300019.

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This paper presents a selective survey of finite difference time domain (FDTD)-based interconnects modeling for signal integrity analysis problems. In spite of 47 years of its existence, researchers have focused on FDTD method with further modifications and enhancements for the signal integrity analysis of interconnects over the past two decades only. Because of the remarkable amount of interconnect-based FDTD-related research activity, tracking the FDTD literature can be a tedious and challenging task. This survey presents some of the significant methods and approaches employed to analyze the developments achieved up to the present-day signal integrity related research. These methods are based on solving telegrapher's equations which represent the transmission line behavior of interconnects. Recent research concentrates on developing novel methods for accurate interconnect modeling, extraction of interconnect parameters and incorporation of more lumped elements into FDTD. In this paper an attempt has been made to compare and summarize some of the well-known FDTD-based methods, which were used in interconnect related research.

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Leon, R., J. A. Colon, K. C. Evans, D. T. Vu, V. Blaschke, B. Bavarian, E. T. Ogawa, and P. S. Ho. "Void evolution and its dependence on segment length in Cu interconnects." Journal of Materials Research 19, no. 11 (November 1, 2004): 3135–38. http://dx.doi.org/10.1557/jmr.2004.0408.

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Void evolution during electromigration was studied by recording void nucleation, growth, and displacements at various intervals during thermal (240 °C) and electrical stress tests (2 × 106 amps/cm2) of Cu interconnects. Structural data was collected for various serially arranged line segment lengths and correlated with resistance and increases in resistance due to electromigration-induced thinning and voiding. These results allowed determination of void growth rates in Cu interconnects. Void nucleation and growth show a clear dependence on segment length. Void formation did not occur at the via/interconnect interface, which improved interconnect reliability by allowing extensive voiding before catastrophic failure.

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KAVICHARAN, M., N. S. MURTHY, and N. BHEEMA RAO. "EFFICIENT DELAY AND CROSSTALK ESTIMATION MODELS FOR CURRENT-MODE HIGH SPEED INTERCONNECTS UNDER RAMP INPUT." Journal of Circuits, Systems and Computers 23, no. 06 (May 14, 2014): 1450082. http://dx.doi.org/10.1142/s0218126614500820.

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In this paper, closed-form models for the computation of finite ramp responses of current-mode resistance inductance capacitance (RLC) interconnects in VLSI circuits are presented. These models are based on extended Eudes model and Scaling and Squaring algorithm which allow numerical estimation of delay in lossy very large scale integration (VLSI) interconnects. The existing Eudes model for interconnect transfer function approximation is extended to higher-order and then Scaling and Squaring method is applied for further improving the accuracy of delay estimation. With the equivalent lossy interconnect transfer function, finite ramp responses are obtained and line delay is estimated for various line lengths, per unit inductances and load capacitances. The estimated 50% delay values are compared with HSPICE W-element model. The worst case errors observed in the estimated delay values are 14.3% for Eudes model and 2% for extended Eudes model while the proposed Scaling and Squaring based model with 1% error is in very good agreement with HSPICE for line lengths 0.1–0.5 cm. The estimated crosstalk induced delay values of proposed model maximum error percentage is nearly half of the extended Eudes model. For both single and three coupled interconnect lines, the proposed model is in good agreement with HSPICE.

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Farrokhi, Maryam, Rahim Faez, Saeed Haji Nasiri, and Bita Davoodi. "Effect of Varying Dielectric Constant on Relative Stability for Graphene Nanoribbon Interconnects." Applied Mechanics and Materials 229-231 (November 2012): 201–4. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.201.

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The remarkable properties of graphene nanoribbons (GNRs) make them attractive for nano-scale devices applications, especially for transistor and interconnect. Furthermore, for reduction interconnects signal delay, low dielectric constant materials are being introduced to replace conventional dielectrics in next generation IC technologies. With these regards, studding the effect of varying dielectric constant (ɛr) on relative stability of graphene nanoribbons interconnect is an important viewpoint in performance evaluation of system. In this paper, Nyquist stability analysis based on transmission line modeling (TLM) for graphene nanoribbon interconnects is investigated. In this analysis, the dependence of the degree of relative stability for multilayer GNR (MLGNR) interconnects on the dielectric constant has been acquired. It is shown that, increasing the dielectric constant of each ribbon, MLGNR interconnects become more stable.

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10

Salinas, J., Yinan Shen, and F. Lombardi. "A sweeping line approach to interconnect testing." IEEE Transactions on Computers 45, no. 8 (1996): 917–29. http://dx.doi.org/10.1109/12.536234.

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11

Cho, Jae Young, Hyo Jong Lee, Hyoung Bae Kim, and Jerzy A. Szpunar. "Texture Investigation in Cu Damascene Interconnects during Annealing." Materials Science Forum 495-497 (September 2005): 1377–82. http://dx.doi.org/10.4028/www.scientific.net/msf.495-497.1377.

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Textural changes of Cu interconnects having a different line width were investigated after annealing. Texture was measured by XRD (x-ray diffraction) at different depth of the interconnect line and on the surface of interconnects using EBSD (electron backscattered diffraction) techniques. To analyze the relationship between the stress distribution and textural evolution observed in the different samples, the stresses were calculated for the different line width at 200°C using FEM (finite element modeling) along the width and depth of the line. In this investigation, it was found that the inhomogeneity of stress distribution in Cu interconnects is an important factor necessary for understanding textural transformation during annealing. Textural evolution in damascene interconnects lines during annealing is discussed, based on the state of stress in Cu electrodeposits.

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EL-MOURSY, MAGDY A., and HEBA A. SHAWKEY. "INTERCONNECT MODELING WITH THE EXISTENCE OF LINE INDUCTANCE." Journal of Circuits, Systems and Computers 22, no. 02 (February 2013): 1250082. http://dx.doi.org/10.1142/s021812661250082x.

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Simple uniform reduced order model is used to model RLC interconnect lines. Waveform characterization is used to evaluate the accuracy of the adopted model. Few number of sections are shown to achieve high accuracy of modeling the RLC interconnect. As compared to RC lines, less than five times the number of sections is sufficient to model RLC lines. The model is shown to be accurate for wide range of relative impedance of the driver, the line, and the load. Look-up tables are provided to simplify the process of choosing the best interconnect section model to characterize an RLC interconnect line. The tables are shown to be accurate for wide range of relative impedance. The presented model reduces the simulation time while keeping the simulation accuracy. The simulation time can be reduced by up to 72% with less than 10% reduction in accuracy using the provided tables. The tables provide a simple and quick mean to characterize an RLC interconnect which is necessary for performance evaluation in digital circuits.

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Du, Ming, Pei Jun Ma, and Yue Hao. "The Impact of Anneal on Electromigration of Copper Interconnect and the Optimized Anneal Technology Study." Advanced Materials Research 482-484 (February 2012): 1188–91. http://dx.doi.org/10.4028/www.scientific.net/amr.482-484.1188.

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The theoretical and experimental work is executed for study the impact of anneal on the grain size, electromigration (EM) reliability of copper (Cu) interconnect system, and subsequently find the optimized anneal condition. EM accelerated failure tests are carried on the Cu interconnect samples with 0.2μm line width, which are produced at different anneal conditions. It is shown that anneal can lead the grains to grow to become larger, and lessen the EM diffuse path. As a result, the EM diffuse active energy (Ea) of Cu interconnect is enhanced, and the ability against the EM of Cu interconnect is improved. By comparing the EM character of Cu interconnects produced at different anneal conditions, results can be obtained as below: the anneal time should be maintained 40 minutes at least in order to achieve fully anneal and excellent ability against the EM; the anneal temperature should be set about 350°C approximately, because high temperature (beyond 400°C) anneal can induce the other reliability issues, which will have a strong negative impact on the EM reliability. The results in this paper are significance for Cu interconnect technology optimize and are beneficial to improve the EM reliability of the Cu interconnect system.

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Masu, Kazuya, Shuhei Amakawa, Hiroyuki Ito, and Noboru Ishihara. "Interconnect Design Challenges in Nano CMOS Circuit." Key Engineering Materials 470 (February 2011): 224–30. http://dx.doi.org/10.4028/www.scientific.net/kem.470.224.

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In the conventional scaling scheme, interconnect delay cannot be reduced and the global interconnect delay become worse if the length of the wire is not scaled. The conventional approaches of global interconnect design are (1)introduction of inverse scaling concept where the upper metal layers have larger cross sections than lower metal layers, (2)insertion of repeaters, and (3) architecture level approach of multi/many core. In order to improve global interconnect delay even in aggressively miniaturized circuit, we have developed the transmission lien interconnect. This paper describes the novel analytical interconnect length distribution and discussion on future interconnect design direction. Then, recent our developments of the transmission line interconnect are described and performance comparison with another global wiring scheme such as optical interconnection is discussed.

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Xu, Peng, Zhongliang Pan, and Zhenhua Tang. "The Ultra-Low-k Dielectric Materials for Performance Improvement in Coupled Multilayer Graphene Nanoribbon Interconnects." Electronics 8, no. 8 (July 31, 2019): 849. http://dx.doi.org/10.3390/electronics8080849.

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The ultra-low-k dielectric material replacing the conventional SiO2 dielectric medium in coupled multilayer graphene nanoribbon (MLGNR) interconnects is presented. An equivalent distributed transmission line model of coupled MLGNR interconnects is established to derive the analytical expressions of crosstalk delay, transfer gain, and noise output for 7.5 nm technology node at global level, which take the in-phase and out-of-phase crosstalk into account. The results show that by replacing the SiO2 dielectric mediums with the nanoglass, the maximum reduction of delay time and peak noise voltage are 25.202 ns and 0.102 V for an interconnect length of 3000 µm, respectively. It is demonstrated that the ultra-low-k dielectric materials can significantly reduce delay time and crosstalk noise and increase transfer gain compared with the conventional SiO2 dielectric medium. Moreover, it is found that the coupled MLGNR interconnect under out-of-phase mode has a larger crosstalk delay and a lesser transfer gain than that under in-phase mode, and the peak noise voltage increases with the increase of the coupled MLGNR interconnect length. The results presented in this paper would be useful to aid in the enhancement of performance of on-chip interconnects and provide guidelines for signal characteristic analysis of MLGNR interconnects.

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Thompson, Carl V., and James R. Lloyd. "Electromigration and IC Interconnects." MRS Bulletin 18, no. 12 (December 1993): 19–25. http://dx.doi.org/10.1557/s088376940003904x.

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A modern integrated circuit (IC) is composed of 106 or more electronic devices. They are connected to form a circuit through the use of metallic films patterned into strips which function as wires to interconnect devices. These wires are usually simply referred to as interconnects. In an IC occupying the surface of a 1 cm2 Si chip, there can be 10 m of total interconnect length. This length is in the form of more than 106 line segments contacting pairs of devices and different segments of the circuit. This enormous number of wires is made possible by their small widths. Interconnect widths as small as 0.55 μm are currently used in commercial circuits, and circuits and processes leading to smaller and smaller widths are continuously in development.During operation of an IC, interconnects carry current densities as high as 4 × 105 A/cm2. This should be compared with a current density of 102 A/cm2, the maximum allowed for house wiring. Thin-film conductors can carry these high current densities only because of the relatively good heat sinking provided by the Si substrate.

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Abbasi, Ruby. "Reduction of Transmission Line Losses Using VLSI Interconnect." Procedia Engineering 30 (2012): 10–19. http://dx.doi.org/10.1016/j.proeng.2012.01.828.

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Khalaj-Amirhosseini, M., and A. Cheldavi. "Matched interconnect design using ground-surrounded microstrip line." IEE Proceedings - Circuits, Devices and Systems 152, no. 1 (2005): 71. http://dx.doi.org/10.1049/ip-cds:20040499.

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Eisenstadt, W. R., and Y. Eo. "S-parameter-based IC interconnect transmission line characterization." IEEE Transactions on Components, Hybrids, and Manufacturing Technology 15, no. 4 (1992): 483–90. http://dx.doi.org/10.1109/33.159877.

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Jones, Robert E., and Michael L. Basehore. "Stress analysis of encapsulated fine‐line aluminum interconnect." Applied Physics Letters 50, no. 12 (March 23, 1987): 725–27. http://dx.doi.org/10.1063/1.98263.

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Nigussie, Ethiopia, Teijo Lehtonen, Sampo Tuuna, Juha Plosila, and Jouni Isoaho. "High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling." VLSI Design 2007 (April 30, 2007): 1–13. http://dx.doi.org/10.1155/2007/46514.

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High-performance long-range NoC link enables efficient implementation of network-on-chip topologies which inherently require high-performance long-distance point-to-point communication such as torus and fat-tree structures. In addition, the performance of other topologies, such as mesh, can be improved by using high-performance link between few selected remote nodes. We presented novel implementation of high-performance long-range NoC link based on multilevel current-mode signaling and delay-insensitive two-phase 1-of-4 encoding. Current-mode signaling reduces the communication latency of long wires significantly compared to voltage-mode signaling, making it possible to achieve high throughput without pipelining and/or using repeaters. The performance of the proposed multilevel current-mode interconnect is analyzed and compared with two reference voltage mode interconnects. These two reference interconnects are designed using two-phase 1-of-4 encoded voltage-mode signaling, one with pipeline stages and the other using optimal repeater insertion. The proposed multilevel current-mode interconnect achieves higher throughput and lower latency than the two reference interconnects. Its throughput at 8 mm wire length is 1.222 GWord/s which is 1.58 and 1.89 times higher than the pipelined and optimal repeater insertion interconnects, respectively. Furthermore, its power consumption is less than the optimal repeater insertion voltage-mode interconnect, at 10 mm wire length its power consumption is 0.75 mW while the reference repeater insertion interconnect is 1.066 mW. The effect of crosstalk is analyzed using four-bit parallel data transfer with the best-case and worst-case switching patterns and a transmission line model which has both capacitive coupling and inductive coupling.

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Alhendi, Mohammed, Ludovico Cestarollo, Gurvinder S. Khinda, Darshana L. Weerawarne, and Mark D. Poliks. "Laser Sintering of Aerosol Jet Printed Interconnects on Flexible Substrate." International Symposium on Microelectronics 2019, no. 1 (October 1, 2019): 000404–8. http://dx.doi.org/10.4071/2380-4505-2019.1.000404.

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Abstract Laser sintering of interconnects printed on flexible substrate with silver nanoparticle ink is studied as an alternative to convection oven sintering. Interconnects of 80 μm and 250 μm line width are printed using an aerosol jet printer and sintered using an 830 nm continuous wave laser. A conductivity that is 4.5× higher than that of an oven sintered interconnect is achieved at optimal laser power and sintering speed set using a full factorial statistical design.

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Renn, Michael J., Bruce H. King, Michael O'Reilly, Jeff S. Leal, and Suzette K. Pangrle. "Aerosol Jet® Printing of High Density, 3-D Interconnects for Multi-Chip Packaging." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (January 1, 2010): 002131–52. http://dx.doi.org/10.4071/2010dpc-tha15.

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Optomec's patented Aerosol Jet technology is a maskless, non-contact material deposition system used to enable 3-dimensional semiconductor packaging. This presentation highlights results of printing high density, 3-D interconnects on stacked die modules which incorporate video, communication and memory chips. Such packages are critical for meeting the increasing functional requirements of SmartPhones, personal entertainment, and other mobile devices. The Aerosol Jet system is used to deposit silver nanoparticle ink connections along the staircase sidewall of staggered multi-chip die stacks. High aspect ratio interconnects with 30-micron line width and greater than 10-micron line height are demonstrated at a pitch of 61-microns. After printing, the silver inks are cured at ~200°C for ~30 minutes, which gives interconnect resistances below one-Ohm (< 5 micron Ohm*cm). The stacks can include up to 8 die, with a total stack height below 1 mm. The printing system has a working distance of several mm which means that no Z-height adjustments are required for the interconnect printing. Multiplexed print nozzles are used to achieve production throughputs of greater than two interconnects per second per nozzle. Based on cost and functional advantages, the Aerosol Jet process is emerging as an effective alternative to traditional wire bond and through-silicon-via (TSV) technologies.

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Olson, Tim. "Transforming Electronic Interconnect." International Symposium on Microelectronics 2017, S1 (October 1, 2017): 000080–108. http://dx.doi.org/10.4071/isom-2017-slide-4.

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From nanometers at the transistor level to 100's of microns at the ball grid array (BGA) connections, electronic interconnect of semiconductors spans orders of magnitude as it forms the central nervous system of today's advanced electronic products. Tectonic shifts are currently underway within the industries providing electronic interconnect. Traditional supply chain boundaries produce back end of line (BEOL) structures within wafer foundries ranging from 10's of nanometers to 10's of microns. First-level interconnect, or packaging, the classical purvey of semiconductor assembly and test services (SATS) providers operates in 10's to 100's of microns. Second-level interconnect, or board level assembly, historically rests with electronic manufacturing systems (EMS) providers measuring their work in 100's of microns and above. The transformation underway in electronic interconnect will redefine historical supply chain boundaries as it blurs the lines between foundries, SATS and EMS providers. At the heart of the transformation is ‘fan-out’ technology moving from initial capacities in wafer form to an emerging format of large panels. Breaking through capital cost, reliability and yield concerns with novel solutions will open the door for widespread industry growth of fan-out.

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Zhangming Zhu, Dajing Wan, and Yintang Yang. "An Interconnect-Line-Size Optimization Model Considering Scattering Effect." IEEE Electron Device Letters 31, no. 7 (July 2010): 641–43. http://dx.doi.org/10.1109/led.2010.2047238.

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Kumar Sharma, Devendra, Brajesh Kumar Kaushik, and R. K. Sharma. "Delay model for dynamically switching coupled on-chip interconnects." Journal of Engineering, Design and Technology 12, no. 3 (July 1, 2014): 364–73. http://dx.doi.org/10.1108/jedt-08-2013-0056.

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Purpose – The purpose of this paper is to propose an analytical model for estimating propagation delay in coupled resistance-inductance-capacitance (RLC) interconnects. Design/methodology/approach – With higher frequency of operation, longer length of interconnect and fast transition time of the signal, the resistor capacitor (RC) models are not sufficient to estimate the delay accurately. To mitigate this problem, accurate delay models for coupled interconnects are required. In this paper, an analytical model for estimation of interconnect delay is developed for simultaneously switching lines. Two distributed RLC lines coupled inductively and capacitively are considered. To validate the proposed model, SPICE results are compared with the proposed analytical results. Each line in the coupled structure is terminated by a capacitive load of 30fF. The driving signal is considered symmetrical with equal rise and fall time of 5 ps and OFF/ON time of 45 ps. The model is validated for both in-phase and out of phase switching of lines. Findings – It is observed that the model works well for both the phases of inputs switching. The derived expressions of delay exhibit complete physical insight, and the results obtained are in excellent agreement with SPICE results. Comparison of analytical delay with SPICE delay shows an average error of < 2.7 per cent. Originality/value – The analytical expressions for interconnect delay are derived for the first time under simultaneously switching scenario. This model is useful to estimate delay across the inductively and capacitively coupled interconnects.

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CHEN, GUOQING, and EBY G. FRIEDMAN. "TRANSIENT RESPONSE OF A DISTRIBUTED RLC INTERCONNECT BASED ON DIRECT POLE EXTRACTION." Journal of Circuits, Systems and Computers 18, no. 07 (November 2009): 1263–85. http://dx.doi.org/10.1142/s0218126609005654.

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With higher operating frequencies, transmission lines are required to model global on-chip interconnects. In this paper, an accurate and efficient solution for the transient response at the far end of a transmission line based on a direct pole extraction of the system is proposed. Closed form expressions of the poles are developed for two special interconnect systems: an RC interconnect and an RLC interconnect with zero driver resistance. By performing a system conversion, the poles of an interconnect system with general circuit parameters are solved. The Newton–Raphson method is used to further improve the accuracy of the poles. Based on these poles, closed form expressions for the step and ramp response are determined. Higher accuracy can be obtained with additional pairs of poles. The computational complexity of the model is proportional to the number of pole pairs. With two pairs of poles, the average error of the 50% delay is 1% as compared with Spectre simulations. With ten pairs of poles, the average error of the 10%-to-90% rise time and the overshoots is 2% and 1.9%, respectively. Frequency dependent effects are also successfully included in the proposed method and excellent match is observed between the proposed model and Spectre simulations.

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GUPTA, ROHINI, JOHN WILLIS, and LAWRENCE T. PILEGGI. "LOW POWER DESIGN OF OFF-CHIP DRIVERS AND TRANSMISSION LINES: A BRANCH AND BOUND APPROACH." International Journal of High Speed Electronics and Systems 07, no. 02 (June 1996): 249–67. http://dx.doi.org/10.1142/s0129156496000104.

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As electronic systems grow in functional complexity, hence size, the design is often forced into a multi-chip solution. For such systems, the power dissipation due to the off-chip drivers (OCDs) and the off-chip interconnect capacitance can contribute to a significant portion of the overall system power. Often, however, this excessive power dissipation is unwarranted, since a smaller OCD can be used to drive the transmission line load, hence reducing the net capacitance being switched. The objective of this paper is to enable power dissipation trade-off decisions during the high-level phases of design and to minimize the power dissipation of OCDs and their associated interconnect. First, a termination metric is described that uses width optimization of RLC interconnects. Then, in terms of a proposed linear driver model, the low power design objective is posed as an integer programming problem and a branch and bound enumeration algorithm is presented. The driver and interconnect sizes are determined which will preserve signal quality, dispense with additional termination components, meet delay requirements, and minimize the overall power dissipation.

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Gnidzinska, K., G. De Mey, and A. Napieralski. "Heat dissipation and temperature distribution in long interconnect lines." Bulletin of the Polish Academy of Sciences: Technical Sciences 58, no. 1 (March 1, 2010): 119–24. http://dx.doi.org/10.2478/v10175-010-0012-8.

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Heat dissipation and temperature distribution in long interconnect linesThermal and time delay aspects of long interconnect lines have been investigated. To design a modern integrated circuit we need to focus on very long global interconnects in order to achieve the desired frequency and signal synchronization. The long interconnection lines introduce significant time delays and heat generation in the driver transistors. Introducing buffers helps to spread the heat production more homogenously along the line but consumes extra power and chip area. To ensure the functionality of the circuit, it is compulsory to give priority to the time delay aspect and then the optimized solution is found by making the power dissipation as homogenous as possible and consequently the temperature distribution T (relative to ambient) as low as possible. The technology used for simulations is 65 nm node. The occurring phenomena have been described in a quantitative and qualitative way.

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Bykhovsky, Dima, Michael Rosenblit, and Shlomi Arnon. "Two-sided through-wafer interconnect for optical spiral delay line." Journal of Modern Optics 65, no. 1 (September 19, 2017): 98–103. http://dx.doi.org/10.1080/09500340.2017.1377305.

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Qingjian Wu and E. S. Kuh. "An accurate time domain interconnect model of transmission line networks." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 43, no. 3 (March 1996): 200–208. http://dx.doi.org/10.1109/81.486444.

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Ravelo, Blaise. "Negative Group-Delay Phenomenon Analysis With Distributed Parallel Interconnect Line." IEEE Transactions on Electromagnetic Compatibility 58, no. 2 (April 2016): 573–80. http://dx.doi.org/10.1109/temc.2016.2516899.

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TSUCHIYA, A., M. HASHIMOTO, and H. ONODERA. "Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A, no. 12 (December 1, 2006): 3585–93. http://dx.doi.org/10.1093/ietfec/e89-a.12.3585.

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Huang, C. C., J. L. Huang, Y. L. Wang, and S. C. Chang. "Fluorine-Doped Carbide Dielectric Barrier to Improve Copper Interconnect Line-to-Line Voltage Breakdown." Electrochemical and Solid-State Letters 10, no. 3 (2007): G8. http://dx.doi.org/10.1149/1.2431243.

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Chen, Fen, Paul S. McLaughlin, and Kaushik Chanda. "Nondestructive electrical characterization of integrated interconnect line-to-line spacing for advanced semiconductor chips." Applied Physics Letters 91, no. 19 (November 5, 2007): 192109. http://dx.doi.org/10.1063/1.2806916.

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Kumar, Ch Praveen, E. Sreenivasa Rao, and P. Chandra Sekhar. "A Novel Approach to Reduce the Crosstalk in Graphene Based Interconnects Using Ternary Logic." Journal of Computational and Theoretical Nanoscience 17, no. 12 (December 1, 2020): 5483–94. http://dx.doi.org/10.1166/jctn.2020.9443.

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This paper presents a novel approach to reduce the impact of crosstalk in multi-layered GNR (MLGNR), single walled CNT (SWCNT), multiwalled CNT (MWCNT) and mixed CNT bundle (MCB) based three-line bus architecture system. The proposed system primarily comprises of active shielding, repeater insertion and asymmetric triggering of the input signal. At the far end of the bus architecture, the crosstalk induced noise and propagation delay of MLGNR, SWCNT, MWCNT and MCB interconnects have been analyzed with and without the impact of shielding. A standard ternary inverter (STI) driver model is used to obtain the ternary logic at the output. Using the specified output, a temperature dependent comparative analysis is also performed for MLGNR and bundled CNT interconnects with and without shielding. Using industry standard HSPICE circuit simulations, it can be observed that the MLGNR offers a lower paracitic values even in higher temperature in comparison to the SWCNT, MWCNT and MCB interconnects. It primarily leads to a lesser delay and crosstalk using a bus interconnect system. The analysis has also extended for delay and crosstalk analysis for different interconnect lengths and temperatures with an insertion of shielding, repeaters and asymmetric triggering of bus architecture system. Under these conditions, it is also proved that an MLGNR based bus architecture offers a lesser crosstalk induced delay and noise compared to CNT bundle interconnects.

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Farrokhi, Maryam, Rahim Faez, Saeed Haji Nasiri, and Bita Davoodi. "Effect of Varying Aspect Ratio on Relative Stability for Graphene Nanoribbon Interconnects." Applied Mechanics and Materials 229-231 (November 2012): 205–9. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.205.

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Achieving dense off-chip interconnection with satisfactory electrical performance is emerging as a major challenge in advanced system engineering. Graphene nanoribbons (GNRs) have been recently proposed as one of the potential candidate materials for both transistors and interconnect. In addition, development is still underway for alternative materials and processes for high aspect ratio (AR) contacts. Studding the effect of varying aspect ratio on relative stability of graphene nanoribbon interconnects is an important viewpoint in performance evaluation of system. In this paper, Nyquist stability analysis based on transmission line modeling (TLM) for GNR interconnects is investigated. In this analysis, the dependence of the degree of relative stability for multilayer GNR (MLGNR) interconnects on the aspect ratio has been acquired. It is shown that, with increasing the aspect ratio of each ribbon, MLGNR interconnects become more unstable.

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Sharma, Rohit, T. Chakravarty, Sunil Bhooshan, and A. B. Bhattacharyya. "Characteristic Impedance of a Microstrip-Like Interconnect Line in Presence of Ground Plane Aperture." International Journal of Microwave Science and Technology 2007 (February 7, 2007): 1–5. http://dx.doi.org/10.1155/2007/41951.

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We propose new empirical expressions for the characteristic impedance of a microstrip-like interconnect line in presence of ground plane aperture. The existing characteristic impedance expressions are modified so as to include the effect of the ground plane aperture. The variation in the characteristic impedance vis-à-vis the aperture size is established. The proposed expressions are general and valid for a range of dielectric materials concerning MICs, RFICs, and PCBs. The results are validated by measurements performed on a vector network analyzer.

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Banan, Behnam, Farhad Shokraneh, Pierre Berini, and Odile Liboiron-Ladouceur. "Electrical performance analysis of a CPW capable of transmitting microwave and optical signals." International Journal of Microwave and Wireless Technologies 9, no. 8 (June 5, 2017): 1679–86. http://dx.doi.org/10.1017/s1759078717000575.

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A study on the microwave performance of a metallic transmission line capable of simultaneously transmitting microwave and optical signals is presented targeting millimeter-long interconnects. Conventional analytical solution is used to find the optimal structure for a given characteristic impedance. Then, functionality of the link is validated through S-parameter measurements for 3–13 mm long lines. The waveguide parameters, such as resistance, inductance, capacitance, and conductance are extracted based on a lumped circuit model. The modeling enables structure optimization for interconnect bandwidth density of 1 Gb/s/μm and more.

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Rebelli, Shashank, and Bheema Rao Nistala. "A novel MRTD model for signal integrity analysis of resistive driven coupled copper interconnects." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 37, no. 1 (January 2, 2018): 189–207. http://dx.doi.org/10.1108/compel-12-2016-0521.

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Purpose This paper aims to model the coupled on-chip Copper (Cu) interconnects by using the multiresolution time-domain (MRTD) method. Design/methodology/approach The proposed model is a wavelet-based numerical method for analyzing signal integrity and propagation delay of coupled on-chip interconnects. Moreover, the dependency of crosstalk noise and delay on coupling parasitics (L12, C12) are analyzed. Findings The proposed MRTD method captures the behaviour of propagation delay and peak crosstalk noise on victim line against coupling parasitics, which is in close agreement with that of H simulation program with integrated circuit emphasis (HSPICE). The average error for the proposed model is less than 1 per cent with respect to HSPICE for the estimation of peak crosstalk noise voltage. Practical implications Simulations are performed using HSPICE and compared with those performed using the proposed MRTD method for global interconnect length with 130-nm technology, where the computations of the proposed model are carried out using Matlab. Originality/value The MRTD method with its unique features is tailored for modelling interconnects. To build further credence to this and its profound existence in the latest state-of-art works, simulations of crosstalk noise and propagation delay, for coupled Cu interconnect lines, using MRTD and finite-difference time-domain (FDTD) are executed. The results illustrated the dominance of MRTD method over FDTD in terms of accuracy.

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Wang, Qing Hua, Hui Min Xie, Zhen Xing Hu, Jing Zhang, Jun Sun, and Gang Liu. "Residual Thermo-Creep Deformation of Copper Interconnects by Phase-Shifting SEM Moiré Method." Applied Mechanics and Materials 83 (July 2011): 185–90. http://dx.doi.org/10.4028/www.scientific.net/amm.83.185.

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The thermo-creep deformation of interconnects related to the residual stress, directly affects their performance and lifetime. In this paper, we proposed an optical method to measure the residual thermo-creep deformation of copper interconnects. This method takes advantages of grating fabrication and the phase-shifting scanning electron microscope (SEM) moiré method. The residual thermo-creep deformation can be acquired through deformation transformation. A one-way grating with frequency of 5000 lines/mm is fabricated on the surface of the copper line in a focused ion-beam (FIB) system. The principal direction of the grating is along the axis of the copper line. The sample is heated in a high temperature furnace under 90 °C for 70 min. The SEM moiré patterns before and after heating are recorded by a field emission SEM in low vacuum. Through the random phase-shifting algorithm, the residual thermo-creep deformation of the copper interconnect line is found to be 500 με. The cause of the tensile strain is analyzed. This work offers an effective technique for measuring the creep deformation of the film lines.

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Ito, Hiroyuki, Shinichiro Gomi, Hideyuki Sugita, Kenichi Okada, and Kazuya Masu. "Twisted Differential Transmission Line Structure for Global Interconnect in Si LSI." Japanese Journal of Applied Physics 44, no. 4B (April 21, 2005): 2774–79. http://dx.doi.org/10.1143/jjap.44.2774.

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Celik, M., A. C. Cangellaris, and A. Yaghnour. "An all-purpose transmission-line model for interconnect simulation in SPICE." IEEE Transactions on Microwave Theory and Techniques 45, no. 10 (1997): 1857–67. http://dx.doi.org/10.1109/22.641783.

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Hildebrand, L. T., and J. Joubert. "An interconnect configuration between a microstrip line and a rectangular waveguide." Microwave and Optical Technology Letters 14, no. 1 (January 1997): 1–3. http://dx.doi.org/10.1002/(sici)1098-2760(199701)14:1<1::aid-mop1>3.0.co;2-p.

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Kaur, Jasmeet, Sandeep Singh Gill, and Navneet Kaur. "Optimization of CMOS repeater driven interconnect RC line using genetic algorithm." Journal of Shanghai Jiaotong University (Science) 22, no. 2 (March 31, 2017): 167–72. http://dx.doi.org/10.1007/s12204-017-1817-5.

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Huang, Ya Ting, Chun Ling Meng, Nian Peng Wu, Xiu Ping Dong, and Xin Chun Lu. "Finite Element Analysis of Failure in Cu Interconnect Megasonic Cleaning." Key Engineering Materials 562-565 (July 2013): 1471–76. http://dx.doi.org/10.4028/www.scientific.net/kem.562-565.1471.

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Megasonic cleaning has been one of the most successful techniques for Cu/low-k interconnects post-CMP cleaning. The structural deformation and stress of Cu and low-k materials in megasonic cleaning are examined with finite element method (FEM). The maximum stress is concentrated in the binding area between Cu and low-k. With decrease of Cu line width, the maximum stress increases and the max value exceeds the yield strength of Cu which results in the plastic deformation. The increasing frequency will change the bubble collision times. Therefore the fatigue is potential. The maximum displacement moves from center to the sides of top surface with increase of line width. When the line width is 25nm, the deformation is the largest.

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Dohle, Rainer, Stefan Härter, Jörg Goßler, and Jörg Franke. "Accelerated Life Tests of Flip-Chips With Solder Bumps Down to 30 μm Diameter." International Symposium on Microelectronics 2011, no. 1 (January 1, 2011): 000985–96. http://dx.doi.org/10.4071/isom-2011-tha3-paper5.

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In this study, accelerated life tests with ultra fine-pitch flip-chips with solder bumps down to 30 microns diameter have been performed. Tests commonly used like temperature cycling, high temperature storage, and humidity bias tests are not sufficient for such small packaging feature sizes any more. As solder bump sizes continue to decrease, along with the shrinkage of the solder pads and the scaling of line/space geometries, thermal diffusion has even more impact on reliability and lifetime of the solder connections, and current densities within single solder bumps increase. Therefore, electromigration of flip-chip interconnects is a significant reliability concern, especially when it comes to further miniaturization for high reliability applications. Since electromigration is a function of interconnect sizes and metallurgies, new interconnect developments need to be characterized for electromigration reliability. Flip-chips 10 mm × 10 mm × 0.8 mm in size with a die layout providing a pitch of 100 μm for solder bump sizes of 60 μm, 50 μm, 40 μm, or 30 μm diameter, respectively, have been used [1]. The SnAgCu alloy solder spheres were placed on a NiAu UBM realized in an electroless nickel process [2]. A daisy chain connection is integrated for each of the solder sphere sizes and each chip can separately be connected for online measurements during electromigration or reliability testing. A variety of current density and temperature combinations which is individually adapted to the respective solder sphere diameter has been used. Lifetime data were collected using online measurement through the daisy chains. Cross sectioning has been employed to analyze the influence of thermal diffusion as well as electromigration on the failure mechanism of the highly miniaturized solder joints. A prediction model for flip-chip interconnects with solder spheres down to 30 μm diameter will be outlined using Black’s equation.

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Kim, Joonhyun, and Yungseon Eo. "IC Package Interconnect Line Characterization Based on Frequency-Variant Transmission Line Modeling and Experimental S-Parameters." IEEE Transactions on Components, Packaging and Manufacturing Technology 9, no. 6 (June 2019): 1133–41. http://dx.doi.org/10.1109/tcpmt.2019.2898671.

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Lee, Wei William, and Paul S. Ho. "Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications." MRS Bulletin 22, no. 10 (October 1997): 19–27. http://dx.doi.org/10.1557/s0883769400034151.

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Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

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Barbara, Bruce. "Ultra-High Density System-in-Package (SiP) for the Lowest Size Weight and Power (SWAP)." International Symposium on Microelectronics 2016, no. 1 (October 1, 2016): 000309–13. http://dx.doi.org/10.4071/isom-2016-wp32.

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Abstract Fan out wafer level packages have emerged across the market in an effort to reduce size and weight of electronics used in portable and wearable applications in the commercial, industrial, and the hi-reliability products space. If it is not a stationary platform, weight and volume reduction are imperative. For the stationary platforms, size and power are most critical. Integration of multiple complex heterogeneous IC components can only be done if there are a sufficient number of interconnect layers. Additionally, multiple interconnects are needed for transmission line creation and shielding. This paper provides an introduction to Aurora Semiconductor's high density packaging technology i.e. iUHD (integrated Ultra High Density) and compares it with other alternative technologies. The Aurora iUHD technology is a 2.5D/3D FOWLCSP including embedded components, TSV, multi-layer top and bottom interconnects.

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Journal articles on the topic 'Interconnect line'

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