Dissertations / Theses: 'Interconnect noise'

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Yang, Yaochao. "Design tradeoffs for noise control in signal integrity for MOS-based interconnect systems." Diss., The University of Arizona, 1995. http://hdl.handle.net/10150/187407.

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Three design tradeoff relations for noise control, namely control for ground bounce noise, control for crosstalk noise, and control for reflection noise, in signal integrity for MOS-based systems are discussed here. Both long-channel modeled MOST (MOS1) and short-channel modeled MOST (MOS3) are used to derived tradeoffs between performance parameters and electrical parameters for a lumped modeled ground-path inductance. Quantitative expressions relating driver size, loading capacitance, edge speed of input signal, parasitic inductance, and a maximum number of allowable simultaneously switching drivers to the worst-case, maximum ground bounce and the signal switching (delay) time are shown to agree with SPICE simulations for both MOS1 and MOS3 devices. Dependent upon the strength of line coupling, two design guidelines to design interconnect systems for targets of 4% far-end overshoot, 10% far-end crosstalk, and a pre-specified far-end response time are introduced to upgrade package performance and packaging density. A low-frequency approximation associated with a second-order Butterworth response is the foundation to control far-end overshoot for the single-mode excitation, and/or for the mixed-mode excitation with weakly coupled lines. An average-transfer-function method is introduced for calculating the required output impedance of source (driver) when multiple modes are excited for strongly coupled lines. It is shown that the far-end response can be significantly improved with reliable operation if the output impedance is designed to be less than the line impedance according to the proposed approach. The near-end and the far-end crosstalk are derived for capacitive far-end and resistive (unmatched) near-end terminations on both the driven and the quiet lines. A simple far-end crosstalk estimate assuming a low line loss, weak line coupling, and a small capacitive load is first derived based on multiple reflections of backward coupling noise from mis-matched terminations. This simple estimate ensures controlled crosstalk for weakly coupled cases. Derivations in the frequency and the time domain of two limits, namely the high-frequency and the low-frequency approximation, for the far-end crosstalk then are followed for heavily-loaded, lossy lines, and/or strong line coupling. Compared to SPICE calculations, It is shown that these two limits can serve as a upper bound and a lower bound for the far-end crosstalk estimate. To estimate the signal delay time, a simple expression that combines the propagation delay time and the far-end Z(0)G(L) time is formulated first. The Elmore delay time for a single line provides a good delay estimate for a signal propagating on loosely coupled lines. For strongly coupled lines, a modified Elmore delay time with a coupling factor is derived, which agrees well with SPICE calculations. Design curves for targets of 4% far-end overshoot and 10% far-end crosstalk are given, and design guidelines, based on a second-order polynomial approximation and least-squares data fitting, are introduced for strongly-coupled lines. SPICE simulations for systems designed using these guidelines agree very well with the design targets, namely a 4% far-end overshoot and a 10% far-end crosstalk. Based upon the assumption that both unsealed and scaled systems satisfy the proposed design guidelines, possible scaling tradeoffs for down-sized (scaled) systems also are examined extensively.

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Taki, Mohamed. "Identification and simulation of critical interconnect paths with respect to transient noise on PCB-level." Aachen Shaker, 2008. http://d-nb.info/992686016/04.

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Taki, Mohamed [Verfasser]. "Identification and Simulation of Critical Interconnect Paths with Respect to Transient Noise on PCB-Level / Mohamed Taki." Aachen : Shaker, 2009. http://d-nb.info/1161310754/34.

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4

Hanchate, Narender. "A game theoretic framework for interconnect optimization in deep submicron and nanometer design." [Tampa, Fla] : University of South Florida, 2006. http://purl.fcla.edu/usf/dc/et/SFE0001523.

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Pamunuwa, Dinesh. "Modelling and Analysis of Interconnects for Deep Submicron Systems-on-Chip." Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3659.

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The last few decades have been a very exciting period in thedevelopment of micro-electronics and brought us to the brink ofimplementing entire systems on a single chip, on a hithertounimagined scale. However an unforeseen challenge has croppedup in the form of managing wires, which have become the mainbottleneck in performance, masking the blinding speed of activedevices. A major problem is that increasingly complicatedeffects need to be modelled, but the computational complexityof any proposed model needs to be low enough to allow manyiterations in a design cycle.

This thesis addresses the issue of closed form modelling ofthe response of coupled interconnect systems. Following astrict mathematical approach, second order models for thetransfer functions of coupled RC trees based on the first andsecond moments of the impulse response are developed. The2-pole-1-zero transfer function that is the best possible fromthe available information is obtained for the signal path fromeach driver to the output in multiple aggressor systems. Thisallows the complete response to be estimated accurately bysumming up the individual waveforms. The model represents theminimum complexity for a 2-pole-1-zero estimate, for this classof circuits.

Also proposed are new techniques for the optimisation ofwires in on-chip buses. Rather than minimising the delay overeach individual wire, the configuration that maximises thetotal bandwidth over a number of parallel wires isinvestigated. It is shown from simulations that there is aunique optimal solution which does not necessarily translate tothe maximum possible number of wires, and in fact deviatesconsiderably from it when the resources available for repeatersare limited. Analytic guidelines dependent only on processparameters are derived for optimal sizing of wires andrepeaters.

Finally regular tiled architectures with a commoncommunication backplane are being proposed as being the mostefficient way to implement systems-on-chip in the deepsubmicron regime. This thesis also considers the feasibility ofimplementing a regular packet-switched network-on-chip in atypical future deep submicron technology. All major physicalissues and challenges are discussed for two differentarchitectures and important limitations are identified.

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Bhaduri, Debayan. "Tools and Techniques for Evaluating Reliability Trade-offs for Nano-Architectures." Thesis, Virginia Tech, 2002. http://hdl.handle.net/10919/9918.

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It is expected that nano-scale devices and interconnections will introduce unprecedented level of defects in the substrates, and architectural designs need to accommodate the uncertainty inherent at such scales. This consideration motivates the search for new architectural paradigms based on redundancy based defect-tolerant designs. However, redundancy is not always a solution to the reliability problem, and often too much or too little redundancy may cause degradation in reliability. The key challenge is in determining the granularity at which defect tolerance is designed, and the level of redundancy to achieve a specific level of reliability. Analytical probabilistic models to evaluate such reliability-redundancy trade-offs are error prone and cumbersome, and do not scalewell for complex networks of gates. In this thesiswe develop different tools and techniques that can evaluate the reliability measures of combinational circuits, and can be used to analyze reliability-redundancy trade-offs for different defect-tolerant architectural configurations. In particular, we have developed two tools, one of which is based on probabilistic model checking and is named NANOPRISM, and another MATLAB based tool called NANOLAB. We also illustrate the effectiveness of our reliability analysis tools by pointing out certain anomalies which are counter-intuitive but can be easily discovered by these tools, thereby providing better insight into defecttolerant design decisions. We believe that these tools will help furthering research and pedagogical interests in this area, expedite the reliability analysis process and enhance the accuracy of establishing reliability-redundancy trade-off points.
Master of Science

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Saint-Laurent, Martin. "Modeling and Analysis of High-Frequency Microprocessor Clocking Networks." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7271.

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Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems. The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems.

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Chandrasekhar, Janani. "Signal to power coupling and noise induced jitter in differential signaling." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24778.

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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.
Committee Chair: Swaminathan Madhavan; Committee Member: Chatterjee Abhijit; Committee Member: Davis Jeffrey.

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Iglesias, Olmedo Miguel. "Impairment Mitigation in High Capacity and Cost-efficient Optical Data Links." Doctoral thesis, KTH, Optik och Fotonik, OFO, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-208101.

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The work presented in this thesis fits within the broader area of fiber optics communications. This is an important area of research as it provides a breeding ground for the present and future technologies supporting the Internet. Due to the ever-increasing bandwidth demands worldwide, the network infrastructures that make up the Internet are continuously being upgraded. This thesis aims to identify key segments of the Internet that are deemed to become the Internet's bottleneck if new technology does not replace the current one. These are datacenter intra and inter-connects, and metropolitan core area networks. In each category, we provide a comprehensive overview of the state of the art, identify key impairments affecting data transmission, and suggest solutions to overcome them. For datacenter intra and inter-connects, the key impairments are lack of bandwidth from electro-optic devices, and dispersion. Solutions attempting to tackle these impairments must be constrained by cost and power consumption. The provided solution is MultiCAP, an alternative advanced modulation format that is more tolerable to dispersion and provides bandwidth management features, while being flexible enough to sacrifice performance in order to gain simplicity. MultiCAP was the first advanced modulation format to achieve over 100~Gb/s in 2013 for a data-center interconnect and set the world record on data transmission over a single VCSEL in 2014 for a short reach data link. On metro-core networks, the challenge is to efficiently mitigate carrier induced frequency noise generated by modern semiconductor lasers. We point out that, when such lasers are employed, the commonly used laser linewidth fails to estimate system performance, and we propose an alternative figure of merit we name "Effective Linewidth". We derive this figure of merit analytically, explore it by numerical simulations and experimentally validate our results by transmitting a 28~Gbaud DP-16QAM over an optical link.

QC 20170602

GRIFFON

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10

Chun, Carl S. P. (Shun Ping). "Investigation of Integrated Circuits for High Datarate Optical Links." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4935.

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Because of the need to move large amounts of data effienciently, optical based communications are a critical component of modern telecommunications. And as a key enabler of optical communications, electrical components play a critical role in optical data links. Optoelectronic integrated circuits provide the bridge between the optical and electrical realms. Electronic integrated circuits are also integral parts of the optical link, interfacing with post processing circuitry and compensating for any limitations along the link. In this investigation, three circuits for optical data link applications are studied. Two optoelectronic integrated circuit front-ends for freespace and long haul applications, respectively and an active filter for near end cross talk cancellation associated with high data rate transmission. The first circuit is an 8x8 monolithic receiver array for a Spatial Division Multiplexing optical link. A compact and low power 8x8 array was designed and demonstrated a channel that received data at rates of 1Gb/s. It is the first completely monolithic demonstration of a 2D receiver array within a conventional ion implanted GaAs MESFET process. The second circuit demonstrated a long wavelength (1.55 m) optoelectronic receiver for long haul applications. The circuit utilized a TWA topology, which maximizes the available bandwidth from the GaAs MESFET process. It incorporated a thin-film inverted MSM photodetector to achieve nearly monolithic integration. The final circuit is a tunable high pass active filter in 0.18 m CMOS technology. As part of a NEXT noise canceller architecture, it will provide the means to extend data transmission in FR-4 legacy backplanes into the tens of Gb/s datarate.

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11

Verolet, Théo. "Hybrid semiconductor lasers for advanced coherent formats in datacenter interconnects." Thesis, université Paris-Saclay, 2020. http://www.theses.fr/2020UPAST006.

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Alors que le trafic de donnée intra-datacenter augmente exponentiellement, de nouvelles générations de transpondeurs optiques sont étudiées. Ces transpondeurs doivent délivrer un fort débit, tout en restant faible consommation. Les technologies cohérentes –sur lesquelles sont établies les liens intercontinentaux- doivent voir leur taille et bilan énergétique réduits. L’utilisation de formats cohérents avancés améliorera les performances des systèmes cohérents tout en les gardant compacts et efficaces énergétiquement. Cependant ces formats peuvent être déployés seulement si des lasers faibles bruits sont utilisés. C’est dans ce cadre que cette thèse étudie la réduction du bruit de phase de trois types de diodes lasers. Premièrement, nous étudions un nouveau type de laser à rétroaction distribué ayant une faible largeur de raie. Des simulations montrant les paramètres de conceptions optimaux de ce type de laser III-V/Si sont présentées. Dans le chapitre suivant, nous analysons les propriétés de reconfiguration rapide de lasers accordables faible bruit. Ici, nous proposons d’abord une nouvelle méthode de mesures permettant d’analyser précisément un saut de mode, ensuite nous présentons des résultats record de transmission cohérentes de paquets optiques. Dans un dernier chapitre, nous montrons que la rétroaction optique permet de stabiliser un laser à verrouillage de mode. Après avoir analysé les différents régimes de fonctionnement, nous confirmons les hautes performances de lien de communication cohérente utilisant ces lasers peigne de fréquence
As data traffic is exponentially increasing in datacenters, new generation of mass producible optical transceivers delivering high data throughput at very low energy consumption are required. Optical coherent technology has been widely used in the past decade to support intercontinental data traffic, as it benefits from higher performance over direct modulation systems though at the cost of complexity and price. To be efficiently used in datacenters, the size and energy consumption of coherent transceivers need to be scaled down while keeping relatively high data throughput. This could be achieved using higher order coherent formats, improving the transmission link spectral efficiency. However, these advanced communication formats can only be supported by low noise lasers. This thesis hence focuses on the phase noise optimization of three types of compact laser diodes using passive/active integration suitable for datacenter interconnects. First, a novel design of III-V/Si narrow linewidth high quality factor DFB laser based on a chirped grating is thoroughly studied. Detailed numerical simulations that yield grating parameters leading to optimal performances are presented for the first time to our knowledge. In a second study, we investigate the fast switching properties of a newly designed narrow linewidth extended cavity III-V/Si laser. After detailing the laser operating principles, we propose an experimental method to precisely characterize laser switching dynamics. Record coherent slot switching experiments are then demonstrated using this new laser. In the final part, we first investigate optical feedback regimes in single section quantum dash MLL and show that coherent feedback can induce a drastic phase noise reduction of the MLL longitudinal modes. The potential use of this comb source in a DWDM coherent link is demonstrated through highly spectrally efficient transmission experiments

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12

Song, Indal. "Multi-Gbit/s CMOS Transimpedance Amplifier with Integrated Photodetector for Optical Interconnects." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4902.

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Trends toward increased integration and miniaturization of optical system components have created pressure to consolidate widely disparate analog and digital functions onto fewer and fewer chips with a goal of eventually built into a single mixed-signal chip. Yet, because of those performance requirements, the frontend circuit has traditionally used III-V compound semiconductor technologies, but the low-level of integration with other digital ICs limits the sustainability of such end products for short-distance applications. On the other hand, their CMOS counter parts, despite having such advantages as low power consumption, high yield that lowers the cost of fabrication, and a higher degree of integration, have not performed well enough to survive in such a noisy environment without sacrificing other important attributes. In this research, a high-speed CMOS preamplifier was designed and fabricated through TSMC 0.18/spl mu/m mixed-signal non-epi CMOS technology, and a 20/spl mu/m diameter InGaAs thin-film Inverted-MSM photodetector with a responsivity of 0.15A/W at a wavelength of 1550/spl mu/m was post-integrated onto the circuit. The circuit has a overall transimpedance gain of 60dB/spl Omega/, and bit-error-rate data and eye-diagram measurement results taken as high as 10Gbit/s are reported in this dissertation.

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13

Lalgudi, Subramanian N. "Transient simulation of power-supply noise in irregular on-chip power distribution networks using latency insertion method, and causal transient simulation of interconnects characterized by band-limited data and terminated by arbitrary terminations." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/22561.

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14

Mao, Jifeng. "Modeling of simultaneous switching noise in on-chip and package power distribution networks using conformal mapping, finite difference time domain and cavity resonator methods." Diss., Available online, Georgia Institute of Technology, 2005, 2004. http://etd.gatech.edu/theses/available/etd-10062004-125025/.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.
Madhavan Swaminathan, Committee Chair ; Sung Kyu Lim, Committee Member ; Abhijit Chatterjee, Committee Member ; David C. Keezer, Committee Member ; C. P. Wong, Committee Member. Vita. Includes bibliographical references.

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15

Bharath, Krishna. "Signal and power integrity co-simulation using the multi-layer finite difference method." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28155.

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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Madhavan Swaminathan; Committee Member: Andrew F. Peterson; Committee Member: David C. Keezer; Committee Member: Saibal Mukhopadyay; Committee Member: Suresh Sitaraman.

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16

Li, Shu-Min, and 李淑敏. "Noise-Aware Buffer Planning for Interconnect-Driven Floorplanning." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/23041553233418613042.

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碩士
國立交通大學
資訊科學系
89
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance and signal integrity. Crosstalk-induced noise has been attracting increasing attention when technology improves, spacing diminishes and coupling capacitance/inductance increases. Buffer insertion/sizing is one of the most effective and popular techniques to reduce interconnect delay and decouple coupling effects. It is traditionally applied to post-layout optimization. However, it is obviously infeasible to insert/size hundreds of thousands buffers during the post-layout stage when most routing regions are occupied. Therefore, it is desirable to incorporate buffer planning into floorplanning to ensure timing closure and design convergence. In this thesis, we first derive formulae of buffer insertion for timing and noise optimization, and then apply the formulae to compute the feasible regions for inserting buffers to meet both timing and noise constraints. Especially, we derive a general formula to release the previous simplified assumption that buffers are inserted in equal distance. By applying degrees of freedom, our theorem proves and explains why and how buffers inserted in equal distance can optimize delay, and this is the special case with the degree of freedom equals one. Experimental results show that our approach achieves an average success rate of 80.8% of nets meeting both timing and noise constraints and consumes an average extra area of only 0.54% over the given floorplan, compared with the average success rate of only 72.8% meeting timing constraints and an extra area of 1.20% by [13].

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17

Taki, Mohamed [Verfasser]. "Identification and simulation of critical interconnect paths with respect to transient noise on PCB-level / von Mohamed Taki." 2008. http://d-nb.info/992032326/34.

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18

Datta, Basab. "On-chip Thermal Sensing In Deep Sub-micron Cmos." 2007. https://scholarworks.umass.edu/theses/52.

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ON-CHIP THERMAL SENSING IN DEEP SUB-MICRON CMOS August 2007 BASAB DATTA B.S., G.G.S. INDRAPRASTHA UNIVERSITY, NEW DELHI M.S.E.C.E, UNIVERSITY OF MASSACHUSETTS AMHERST Directed by: Professor Wayne P. Burleson Aggressive technology scaling and an increasing demand for high performance VLSI circuits has resulted in higher current densities in the interconnect lines and increasingly higher power dissipation in the substrate. Because a significant fraction of this power is converted to heat, an exponential rise in heat density is also experienced. Different activities and sleep modes of the functional blocks in high performance chips cause significant temperature gradients in the substrate and this can be expected to further increase in the GHz frequency regime. The above scenario motivates the need for a large number of lightweight, robust and power-efficient thermal sensors for accurate thermal mapping and thermal management. We propose the use of Differential Ring Oscillators (DRO) for thermal sensing at the substrate level, utilizing the temperature dependence of the oscillation frequency. They are widely used in current VLSI for frequency synthesis and on-die process characterization; hence provide scope of reusability in design. The DRO oscillation frequency decreases linearly with increase in temperature due to the decrease in current in the signal paths. In current starved inverter topology using the 45nm technology node, the DRO based thermal sensor has a resolution of 2°C and a low active power consumption of 25µW, which can be reduced further by 60-80% by power-gating the design. Current thermal scaling trends in multilevel low-k interconnect structures suggest an increasing heat density as we move from substrate to higher metal levels. Thus, the deterioration of interconnect performance at extreme temperatures has the capability to offset the degradation in device performance when operating at higher than normal temperatures. We propose using lower-level metal interconnects to perform the thermal sensing. A resolution of ~5°C is achievable for both horizontal and vertical gradient estimation (using current generation time-digitizers). The time-digitization unit is an essential component needed to perform interconnect based thermal sensing in deep nanometer designs but it adds area and power overhead to the sensor design and limits the resolution of the wire-based sensor. We propose a novel sensor design that alleviates complexities associated with time-to-digital conversion in wire-based thermal sensing. The IBOTS or Interconnect Based Oscillator for Thermal Sensing makes use of wire-segments between individual stages of a ring-oscillator to perform thermal sensing using the oscillator frequency value as the mapping to corresponding wire temperature. The frequency output can be used to generate a digital code by interfacing the IBOTS with a digital counter. In 45nm technology, it is capable of providing a resolution of 1°C while consuming an active power of 250-360µW.

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Lee, Herng-Jer, and 李恆哲. "Model-Order Reduction and Crosstalk Noise Estimation in High-Speed VLSI Interconnects." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/18130747435326238393.

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博士
長庚大學
電機工程研究所
92
With the advance of modern VLSI techniques, interconnects have no longer been ignored in high-speed VLSI designs. To address issues of signal/power integrity effectively, interconnects are often modeled as lumped or distributed R(L)C circuits. Owing to the increasing wire density and the required modeling accuracy, the wire model for practical chip designs may be with a huge scale. This causes that using traditional circuit simulators, such as SPICE, to simulate such circuits become inefficient and impractical. In addition, the importance of on-chip inductance effects has grown continuously since nano-meter technology has emerged over the last few years. It has been observed that crosstalk noise estimations made by considering inductance effects may yield more pessimistic results than those made without considering coupling inductance effects. In summary, the aim of this dissertation is to develop model-order reduction techniques to obtain effective interconnect models efficiently for interconnect circuit simulations and noise estimations. First, recursive formulae of moments of coupled RC trees are extended to those for coupled RLC trees by considering both self inductances, mutual inductances and distributed lines. Combining with the Krylov subspace orthogonal projection, stable-pole models can be efficiently build for estimating the crosstalk noise peak. Next, a new moment computation technique for partitioning a general lumped R(L)C interconnect network with resistor loops into a spanning tree and resistor links are proposed. By combining the conventional moment computation algorithms and the reduced ordered binary decision diagram (ROBDD), the proposed method can compute moments efficiently. In addition, an efficient model-order reduction technique is proposed. The approach is extended from the previous projection-based moment matching method with considering both the original circuit network and its corresponding adjoint network. By exploring symmetric properties of the MNA formulation, the computational cost of constructing the congruence transformation matrix can be reduced by 50% compared with the conventional methods. Finally, another model reduction method, the adaptive-order rational Arnoldi method (AORA), is provided to be applied to high-speed VLSI interconnect models. It is based on an extension of the classical multi-point Pade approximation, using the rational Arnoldi iteration approach. In each iteration of the proposed method, the expansion frequency corresponding to the maximum output moment error is chosen. Consequently, the corresponding reduced-order model will yield the greatest improvement in output moments among all reduced-order models of the same order.

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Chang, Huang-Choung, and 張晃崇. "Copper-Metallized Interconnects on GaAs Low Noise Pseudomorphic High Electron Mobility Transistors." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/g3278r.

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Kayili, Levent. "Abnormal Group Delay and Detection Latency in the Presence of Noise for Communication Systems." Thesis, 2010. http://hdl.handle.net/1807/24255.

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Although it has been well established that abnormal group delay is a real physical phenomenon and is not in violation of Einstein causality, there has been little investigation into whether or not such abnormal behaviour can be used to reduce signal latency in practical communication systems in the presence of noise. In this thesis, we use time-varying probability of error to determine if abnormal group delay “channels” can offer reduced signal latency. Since the detection system plays a critical role in the analysis, three important detection systems are considered: the correlation, matched filter and envelope detection systems. Our analysis shows that for both spatially negligible microelectronic systems and spatially extended microwave systems, negative group delay “channels” offer reduced signal latency as compared to conventional “channels”. The results presented in the thesis can be used to design a new generation of electronic and microwave interconnects with reduced or eliminated signal latency.

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Dissertations / Theses on the topic 'Interconnect noise'

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