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Journal articles on the topic 'Interconnect noise'

Author: Grafiati

Published: 4 June 2021

Last updated: 14 February 2022

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1

Xu, Peng, Zhongliang Pan, and Zhenhua Tang. "The Ultra-Low-k Dielectric Materials for Performance Improvement in Coupled Multilayer Graphene Nanoribbon Interconnects." Electronics 8, no. 8 (July 31, 2019): 849. http://dx.doi.org/10.3390/electronics8080849.

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The ultra-low-k dielectric material replacing the conventional SiO2 dielectric medium in coupled multilayer graphene nanoribbon (MLGNR) interconnects is presented. An equivalent distributed transmission line model of coupled MLGNR interconnects is established to derive the analytical expressions of crosstalk delay, transfer gain, and noise output for 7.5 nm technology node at global level, which take the in-phase and out-of-phase crosstalk into account. The results show that by replacing the SiO2 dielectric mediums with the nanoglass, the maximum reduction of delay time and peak noise voltage are 25.202 ns and 0.102 V for an interconnect length of 3000 µm, respectively. It is demonstrated that the ultra-low-k dielectric materials can significantly reduce delay time and crosstalk noise and increase transfer gain compared with the conventional SiO2 dielectric medium. Moreover, it is found that the coupled MLGNR interconnect under out-of-phase mode has a larger crosstalk delay and a lesser transfer gain than that under in-phase mode, and the peak noise voltage increases with the increase of the coupled MLGNR interconnect length. The results presented in this paper would be useful to aid in the enhancement of performance of on-chip interconnects and provide guidelines for signal characteristic analysis of MLGNR interconnects.

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2

Das, Debaprasad, and Hafizur Rahaman. "Investigating the Applicability of Graphene Nanoribbon as Signal and Power Interconnects for Nanometer Designs." Journal of Circuits, Systems and Computers 25, no. 02 (December 23, 2015): 1650001. http://dx.doi.org/10.1142/s0218126616500018.

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In this work, we have investigated the applicability of graphene nanoribbon (GNR) as the interconnects for 16-nm ITRS technology node. GNR is proposed as the possible alternative to the traditional copper (Cu)-based interconnect systems in nanometer regime. In this paper, we have performed important studies on GNR for its applicability as power and signal interconnects. For the application of power interconnects, we have investigated the power supply voltage drop (IR drop) and simultaneous switching noise (SSN) in graphene-based interconnect system. We have performed crosstalk noise and overshoot/undershoot analyses for the application of signal interconnects. The results are compared with that of the traditional Cu-based interconnects. The results show that GNR is better than Cu as far as IR drop, SSN, gate oxide reliability and hot carrier reliability are concerned. Our investigation reveals that GNR can be better than the Cu interconnects from all aspects with a multilayer GNR structure. The present graphene-based interconnect technology needs to be advanced, so that the metal–graphene contact resistance is minimized and multilayer GNR structure with large number of graphene layers is supported.

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3

Chanu, Waikhom Mona, and Debaprasad Das. "Modeling and Performance Analysis of MLGNR Interconnects." Journal of Circuits, Systems and Computers 27, no. 14 (August 23, 2018): 1850214. http://dx.doi.org/10.1142/s0218126618502146.

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In this work, we have presented the temperature-dependent analytical time domain model for top-contact multilayer graphene nanoribbon (TC-MLGNR) and side-contact multilayer graphene nanoribbon (SC-MLGNR) interconnects for 16[Formula: see text]nm technology node. Using this analytical model, the effective mean free path (MFP) is calculated for different temperatures and then the resistance of GNR interconnect is calculated. The lower resistance of MLGNR is one of the important factors to reduce interconnect delay. The equivalent capacitance for TC-MLGNR is also calculated. It is observed that the performance of graphene interconnects seriously deteriorates due to the presence of the interlayer capacitance. The presence of this interlayer capacitance increases the equivalent capacitance which is the dominant factor that inhibits the performance of TC-MLGNR interconnects. Further, the delay ratio between copper and TC-MLGNR for different interconnect lengths and for three different temperatures (233[Formula: see text]K, 300[Formula: see text]K, 378[Formula: see text]K) is calculated. It is observed that for longer interconnect lengths, the improvement in delay in TC-MLGNR is less as compared to traditional copper-based interconnect at low temperature. Further, power delay product (PDP) of copper and TC-MLGNR for different interconnect lengths and for three different temperatures is also calculated. It is shown that TC-MLGNR interconnects have better PDP than copper interconnects. The crosstalk analysis is performed to estimate the noise and overshoot/undershoot in TC-MLGNR and SC-MLGNR interconnects. It is shown that SC-MLGNR interconnect has better performance as far as the crosstalk is concerned as compared to that of Cu and TC-MLGNR interconnects.

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4

Vrudhula, S., D. T. Blaauw, and S. Sirichotiyakul. "Probabilistic analysis of interconnect coupling noise." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22, no. 9 (September 2003): 1188–203. http://dx.doi.org/10.1109/tcad.2003.816212.

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5

Tsong-Ming Chen and A. M. Yassine. "Electrical noise and VLSI interconnect reliability." IEEE Transactions on Electron Devices 41, no. 11 (1994): 2165–72. http://dx.doi.org/10.1109/16.333837.

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6

Rebelli, Shashank, and Bheema Rao Nistala. "A novel MRTD model for signal integrity analysis of resistive driven coupled copper interconnects." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 37, no. 1 (January 2, 2018): 189–207. http://dx.doi.org/10.1108/compel-12-2016-0521.

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Purpose This paper aims to model the coupled on-chip Copper (Cu) interconnects by using the multiresolution time-domain (MRTD) method. Design/methodology/approach The proposed model is a wavelet-based numerical method for analyzing signal integrity and propagation delay of coupled on-chip interconnects. Moreover, the dependency of crosstalk noise and delay on coupling parasitics (L12, C12) are analyzed. Findings The proposed MRTD method captures the behaviour of propagation delay and peak crosstalk noise on victim line against coupling parasitics, which is in close agreement with that of H simulation program with integrated circuit emphasis (HSPICE). The average error for the proposed model is less than 1 per cent with respect to HSPICE for the estimation of peak crosstalk noise voltage. Practical implications Simulations are performed using HSPICE and compared with those performed using the proposed MRTD method for global interconnect length with 130-nm technology, where the computations of the proposed model are carried out using Matlab. Originality/value The MRTD method with its unique features is tailored for modelling interconnects. To build further credence to this and its profound existence in the latest state-of-art works, simulations of crosstalk noise and propagation delay, for coupled Cu interconnect lines, using MRTD and finite-difference time-domain (FDTD) are executed. The results illustrated the dominance of MRTD method over FDTD in terms of accuracy.

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7

Bhattacharya, Sandip, Debaprasad Das, and Hafizur Rahaman. "Analysis of Simultaneous Switching Noise and IR-Drop in Side-Contact Multilayer Graphene Nanoribbon Power Distribution Network." Journal of Circuits, Systems and Computers 27, no. 01 (August 23, 2017): 1850001. http://dx.doi.org/10.1142/s0218126618500019.

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The work in this paper presents the analyses of temperature-dependent simultaneous switching noise (SSN) and IR-Drop in multilayer graphene nanoribbon (MLGNR) power interconnects for 16[Formula: see text]nm ITRS technology node. A [Formula: see text] standard cell-based integrated circuit is designed to analyze the SSN and IR-Drop using the proposed temperature-dependent model of MLGNR and Cu interconnect for 10[Formula: see text][Formula: see text]m interconnect length at temperatures (233[Formula: see text]K, 300[Formula: see text]K and 378[Formula: see text]K). Our analysis shows that MLGNR exhibits ([Formula: see text]–[Formula: see text]) less SSN and ([Formula: see text]–[Formula: see text]) less IR-Drop as compared with traditional Cu-based power interconnects. Our analysis also shows that the average percentage of reduction in peak SSN is 52–32% (at 233[Formula: see text]K), 53–32% (at 300[Formula: see text]K) and 52–30% (at 378[Formula: see text]K) less in MLGNR compared with traditional Cu-based power interconnect and the average percentage of reduction in peak IR-Drop in MLGNR is 54–31% (at 233[Formula: see text]K), 57–29% (at 300[Formula: see text]K) and 57–26% (at 378[Formula: see text]K) less than that of Cu-based power interconnects.

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8

Kumar, Ch Praveen, E. Sreenivasa Rao, and P. Chandra Sekhar. "A Novel Approach to Reduce the Crosstalk in Graphene Based Interconnects Using Ternary Logic." Journal of Computational and Theoretical Nanoscience 17, no. 12 (December 1, 2020): 5483–94. http://dx.doi.org/10.1166/jctn.2020.9443.

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This paper presents a novel approach to reduce the impact of crosstalk in multi-layered GNR (MLGNR), single walled CNT (SWCNT), multiwalled CNT (MWCNT) and mixed CNT bundle (MCB) based three-line bus architecture system. The proposed system primarily comprises of active shielding, repeater insertion and asymmetric triggering of the input signal. At the far end of the bus architecture, the crosstalk induced noise and propagation delay of MLGNR, SWCNT, MWCNT and MCB interconnects have been analyzed with and without the impact of shielding. A standard ternary inverter (STI) driver model is used to obtain the ternary logic at the output. Using the specified output, a temperature dependent comparative analysis is also performed for MLGNR and bundled CNT interconnects with and without shielding. Using industry standard HSPICE circuit simulations, it can be observed that the MLGNR offers a lower paracitic values even in higher temperature in comparison to the SWCNT, MWCNT and MCB interconnects. It primarily leads to a lesser delay and crosstalk using a bus interconnect system. The analysis has also extended for delay and crosstalk analysis for different interconnect lengths and temperatures with an insertion of shielding, repeaters and asymmetric triggering of bus architecture system. Under these conditions, it is also proved that an MLGNR based bus architecture offers a lesser crosstalk induced delay and noise compared to CNT bundle interconnects.

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9

LI, Katherine Shu-Min, Yingchieh HO, and Liang-Bi CHEN. "Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E96.A, no. 12 (2013): 2467–74. http://dx.doi.org/10.1587/transfun.e96.a.2467.

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10

Liu, Xiaoxiao, Guangsheng Ma, Jingbo Shao, Zhi Yang, and Guanjun Wang. "Interconnect crosstalk noise evaluation in deep-submicron technologies." Microelectronics Reliability 49, no. 2 (February 2009): 170–77. http://dx.doi.org/10.1016/j.microrel.2008.11.013.

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11

Hunagund, P. V., and A. B. Kalpana. "Crosstalk Interconnect Noise Optimization Technique Using Wire Spacing and Sizing for High Speed Integrated Circuits." International Journal of Engineering and Technology 3, no. 6 (2011): 684–88. http://dx.doi.org/10.7763/ijet.2011.v3.305.

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12

Elgamel, M. A., and M. A. Bayoumi. "Interconnect noise analysis and optimization in deep submicron technology." IEEE Circuits and Systems Magazine 3, no. 4 (October 2003): 6–17. http://dx.doi.org/10.1109/mcas.2003.1267064.

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13

Neri, B., C. Ciofi, and V. Dattilo. "Noise and fluctuations in submicrometric Al-Si interconnect lines." IEEE Transactions on Electron Devices 44, no. 9 (1997): 1454–59. http://dx.doi.org/10.1109/16.622601.

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14

Ki-Wook Kim, Seong-Ook Jung, U. Narayanan, C. L. Liu, and Sung-Mo Kang. "Noise-aware interconnect power optimization in domino logic synthesis." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11, no. 1 (February 2003): 79–89. http://dx.doi.org/10.1109/tvlsi.2002.801630.

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15

Kaushik, B. K., S. Sarkar, R. P. Agarwal, and R. C. Joshi. "Voltage scaling – a novel approach for crosstalk reduction in global VLSI interconnects." Microelectronics International 24, no. 1 (January 2, 2007): 40–45. http://dx.doi.org/10.1108/13565360710725937.

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PurposeTo analyze the effect of voltage scaling on crosstalk.Design/methodology/approachVoltage scaling has been often used for reducing power dissipation of CMOS driven interconnects. An undesired effect observed due to voltage scaling is increase in propagation delay. Thus, a trade off lies between power dissipation and propagation delay with voltage scaling. However, voltage scaling can result in overall reduction of power delay product. Therefore, their lies an optimized supply voltage where‐in power dissipation and propagation delay can be optimized. Many of the previous researches have discussed about power dissipation and propagation delay only with voltage scaling. This paper for first time shows the effect on crosstalk in voltage scaled interconnects. In this paper, we primarily study the noise for an input signal having transition time of 50 ps. The simulations are run for interconnect length of 2 and 4 mm. These parameters are varied for four different cases of stimulations to aggressor and victim lines viz. VA (input at aggressor node A) and VB (input at victim node B) switching in same direction; VA is switching and VB at static low; VA and VB are switching in opposite direction; VA is switching and VB at static high.FindingsIt is quite encouraging to observe that irrespective of interconnect length and technology node used, an optimized voltage scaling reduces normalized crosstalk level.Originality/valueVoltage scaling can be effectively used for crosstalk reduction by the new era VLSI interconnect designers. This paper shows simulation results for crosstalk reduction in different nano‐sized CMOS driven RLC‐modeled interconnects.

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16

Jin, Xin, Kuanchen Xiong, Roderick Marstell, Nicholas C. Strandwitz, James C. M. Hwang, Marco Farina, Alexander Göritz, Matthias Wietstruck, and Mehmet Kaynak. "Scanning microwave microscopy of buried CMOS interconnect lines with nanometer resolution." International Journal of Microwave and Wireless Technologies 10, no. 5-6 (April 17, 2018): 556–61. http://dx.doi.org/10.1017/s1759078718000181.

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This paper reports scanning microwave microscopy of CMOS interconnect aluminum lines both bare and buried under oxide. In both cases, a spatial resolution of 190 ± 70 nm was achieved, which was comparable or better than what had been reported in the literature. With the lines immersed in water to simulate high-k dielectric, the signal-to-noise ratio degraded significantly, but the image remained as sharp as before, especially after averaging across a few adjacent scans. These results imply that scanning microwave microscopy can be a promising technique for non-destructive nano-characterization of both CMOS interconnects buried under oxide and live biological samples immersed in water.

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17

Liu, Xiao Xiao, Jing Bo Shao, and Ling Ling Zhao. "An Efficient Methodology for Estimating Interconnect Crosstalk Noise in Deep-Submicron Technologies." Advanced Materials Research 989-994 (July 2014): 2647–50. http://dx.doi.org/10.4028/www.scientific.net/amr.989-994.2647.

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To solve the crosstalk noise question in deep-submicron technologies, an efficient methodology for estimating interconnect crosstalk noise is proposed in this paper. PCA and ICA techniques are applied to reduce correlations of process variations, and moment matching scheme is used to obtain the PDF of crosstalk noise in victim coupled with multiple aggressors. Experimental results show that our method maintains the efficiency of past approaches, and significantly improves on their accuracy.

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18

Ekekwe, Ndubuisi. "Power dissipation and interconnect noise challenges in nanometer CMOS technologies." IEEE Potentials 29, no. 3 (May 2010): 26–31. http://dx.doi.org/10.1109/mpot.2010.935825.

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19

Saint-Laurent, Martin. "A Model for Interlevel Coupling Noise in Multilevel Interconnect Structures." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, no. 5 (May 2007): 834–44. http://dx.doi.org/10.1109/tcad.2006.884485.

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20

Saint-Laurent, Martin. "A model for interlevel coupling noise in multilevel interconnect structures." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, no. 5 (May 2007): 834–44. http://dx.doi.org/10.1109/tcad.2007.8361578.

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21

Shin, H., Z. Xu, K. Miyashiro, and M. F. Chang. "Estimation of signal-to-noise ratio improvement in RF-interconnect." Electronics Letters 38, no. 25 (2002): 1666. http://dx.doi.org/10.1049/el:20021167.

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22

Li, Jianwei, Gang Dong, and Zeng Wang. "Statistical Interconnect Crosstalk Noise Model and Analysis for Process Variations." Chinese Journal of Electronics 24, no. 1 (January 1, 2015): 83–87. http://dx.doi.org/10.1049/cje.2015.01.014.

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23

Nageswara Rao, K., G. Veerendra Nath, and K. Hari Kishore. "Crosstalk noise minimization in novel through silicon via structures." International Journal of Engineering & Technology 7, no. 2.8 (March 19, 2018): 56. http://dx.doi.org/10.14419/ijet.v7i2.8.10325.

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In recent trends, through silicon via (TSV) is essential Technologies for 3-D IC integration because of its short interconnects length and high interconnect density. Beyond the existing structure of TSV, this paper provides a novel structure to investigate the crosstalk effect and same is simulated by using a SPICE simulator and 3-D field solver. The structure of the TSV comprises of copper surrounding by insulating liner, and silicon substrate. In existing structures, silicon dioxide (Sio2) is used as insulating liner because of its material compatibility with silicon substrate. Several researches provide the problem of using Sio2 is due to its high dielectric constant; as a consequence delay will increase. Therefore, Sio2 is not appropriate for high performance applications. In this work, a novel TSV structure is reported to improve the TSV performance which uses poly-propylene polymer liner instead of oxide liner. Signal TSV is enclosed by using a poly-propylene liner and amid the analysis with doping region is created around the ground TSV. For comparison purposes, conventional and proposed TSV structures are simulated. The proposed TSV’s structure simulation results in 30% decrease in crosstalk over existing TSV structures.

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24

Lanni, L., B. G. Malm, C. M. Zetterling, and M. Östling. "A 4H-SiC Bipolar Technology for High-Temperature Integrated Circuits." Journal of Microelectronics and Electronic Packaging 10, no. 4 (October 1, 2013): 155–62. http://dx.doi.org/10.4071/imaps.390.

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A 4H-SiC bipolar technology suitable for high-temperature integrated circuits is tested with two interconnect systems based on aluminum and platinum. Successful operation of low-voltage bipolar transistors and digital integrated circuits based on emitter coupled logic (ECL) is reported from 27°C up to 500°C for both the metallization systems. When operated on −15 V supply voltage, aluminum and platinum interconnect OR-NOR gates showed stable noise margins of about 1 V and asymmetric propagation delays of about 200 and 700 ns in the whole temperature range for both OR and NOR output. The performance of aluminum and platinum interconnects was evaluated by performing accelerated electromigration tests at 300°C with current density of about 1 MA/cm2 on contact chains consisting of 10 integrated resistors. Although in both cases the contact chains failed after less than one hour, different failure mechanisms were observed for the two metallization systems: electromigration for the aluminum system and poor step coverage and via filling for the platinum system.

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25

Fu, Bo, and Paul Ampadu. "An Energy-Efficient Multiwire Error Control Scheme for Reliable On-Chip Interconnects Using Hamming Product Codes." VLSI Design 2008 (December 31, 2008): 1–14. http://dx.doi.org/10.1155/2008/109490.

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We propose an energy-efficient error control scheme for on-chip interconnects capable of correcting a combination of multiple random and burst errors. The iterative decoding method, interleaver, using two-dimensional Hamming product codes and a simplified type-II hybrid ARQ, achieves several orders of magnitude improvement in residual flit-error rate for multiwire errors and up to 45% improvement in throughput in high noise environments. For a given system reliability requirement, the proposed error control scheme yields up to 50% energy improvement over other error correction schemes. The low overhead of our approach makes it suitable for implementation in on-chip interconnect switches.

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26

Sonkin, Eduard, Dan Sadot, and Gilad Katz. "MZM Optimization of PAM-4 Transmission in Data Center Interconnect." Applied Sciences 9, no. 4 (February 14, 2019): 637. http://dx.doi.org/10.3390/app9040637.

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An analog optimization of 4-level pulse amplitude modulation (PAM-4) signal is proposed, together with maximum likelihood sequence estimation digital signal processing. The proposed optimizations are verified by experimental demonstration at 53 Gbaud, indicating an improvement of 4–5 dB in the optical signal to noise sensitivity.

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27

Bai, X., R. Chandra, S. Dey, and P. V. Srinivas. "Interconnect Coupling-Aware Driver Modeling in Static Noise Analysis for Nanometer Circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, no. 8 (August 2004): 1256–63. http://dx.doi.org/10.1109/tcad.2004.831568.

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28

Chen, H. H., and J. S. Neely. "Interconnect and circuit modeling techniques for full-chip power supply noise analysis." IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B 21, no. 3 (1998): 209–15. http://dx.doi.org/10.1109/96.704931.

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29

CHEN, HOWARD H., and C. K. WONG. "63-LAYER TCM WIRING WITH THREE-DIMENSIONAL CROSSTALK CONSTRAINTS." International Journal of High Speed Electronics and Systems 06, no. 03 (September 1995): 497–508. http://dx.doi.org/10.1142/s012915649500016x.

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In the state-of-the-art thermal conduction module (TCM) design, as many as 63 thinfilm and glass-ceramic layers can be used to interconnect 121 chips.1,2 The total amount of noise on the package consists of not only the crosstalk between adjacent signal lines in the X and Y directions, but also the coupled noise between adjacent pins and vias in the Z direction. This paper describes the wiring and layer assignment strategies to minimize both the XY and Z-direction coupled noise in TCM design.

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30

Shahriar, Md, Md Khalid, and Abid Ahmed. "Crosstalk Noise Modeling analysis for RC Interconnect in Deep Sub-Micron VLSI Circuit." Communications on Applied Electronics 7, no. 4 (July 26, 2017): 33–38. http://dx.doi.org/10.5120/cae2017652647.

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31

Hanchate, N., and N. Ranganathan. "Simultaneous interconnect delay and crosstalk noise optimization through gate sizing using game theory." IEEE Transactions on Computers 55, no. 8 (August 2006): 1011–23. http://dx.doi.org/10.1109/tc.2006.131.

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32

Pillement, Sébastien, Olivier Sentieys, and Jean-Marc Philippe. "Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect." Microelectronics Journal 41, no. 8 (August 2010): 480–86. http://dx.doi.org/10.1016/j.mejo.2009.11.001.

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Lee, Wei William, and Paul S. Ho. "Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications." MRS Bulletin 22, no. 10 (October 1997): 19–27. http://dx.doi.org/10.1557/s0883769400034151.

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Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

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Sato, T., D. Sylvester, Yu Cao, and Chenming Hu. "Accurate in situ measurement of peak noise and delay change induced by interconnect coupling." IEEE Journal of Solid-State Circuits 36, no. 10 (2001): 1587–91. http://dx.doi.org/10.1109/4.953489.

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35

Lanni, L., B. G. Malm, C. M. Zetterling, and M. Östling. "A 4H-SiC Bipolar Technology for High-temperature Integrated Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, HITEN (January 1, 2013): 000282–89. http://dx.doi.org/10.4071/hiten-wp13.

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A 4H-SiC bipolar technology suitable for high-temperature integrated circuits is tested with two interconnect systems based on Aluminium and Platinum. Successful operation of low-voltage bipolar transistor and digital integrated circuits based on emitter coupled logic (ECL) is reported from 27 up to 500 °C for both the metallization systems. When operated on −15 V supply voltage, Aluminium and Platinum OR-NOR gates showed stable noise margins of about 1 V and asymmetric propagation delays of about 200 and 700 ns in the whole temperature range for both OR and NOR output. The performance of Aluminium and Platinum interconnect were evaluated by performing accelerated electromigration tests at 300 °C with current density of about 1 MA/cm2 on contact chains consisting of 10 integrated resistors.

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36

Dove, Lewis. "Multi-Layer Ceramic Packaging for High Frequency Mixed-Signal VLSI ASICS." Journal of Microelectronics and Electronic Packaging 6, no. 1 (January 1, 2009): 38–41. http://dx.doi.org/10.4071/1551-4897-6.1.38.

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Mixed-signal Application Specific Integrated Circuits (ASICs) have traditionally been used in test and measurement applications for a variety of functions such as data converters, pin electronics circuitry, drivers, and receivers. Over the past several years, the complexity, power density, and bandwidth of these chips has increased dramatically. This has necessitated dramatic changes in the way these chips have been packaged. As the chips have become true VLSI (Very Large Scale Integration) ICs, the number of I/Os have become too large to interconnect with wire bonds. Thus, it has become necessary to utilize flip chip interconnects. Also, the bandwidth of the high-speed signal paths and clocks has increased into the multi Gbit or GHz ranges. This requires the use of packages with good high-frequency performance which are designed using microwave circuit techniques to optimize signal integrity and to minimize signal crosstalk and noise.

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Ryan, E. Todd, Andrew J. McKerrow, Jihperng Leu, and Paul S. Ho. "Materials Issues and Characterization of Low-k Dielectric Materials." MRS Bulletin 22, no. 10 (October 1997): 49–54. http://dx.doi.org/10.1557/s0883769400034205.

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Continuing improvement in device density and performance has significantly affected the dimensions and complexity of the wiring structure for on-chip interconnects. These enhancements have led to a reduction in the wiring pitch and an increase in the number of wiring levels to fulfill demands for density and performance improvements. As device dimensions shrink to less than 0.25 μm, the propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant. Accordingly the interconnect delay now constitutes a major fraction of the total delay limiting the overall chip performance. Equally important is the processing complexity due to an increase in the number of wiring levels. This inevitably drives cost up by lowering the manufacturing yield due to an increase in defects and processing complexity.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILDs) and alternative architectures have surfaced to replace the current Al(Cu)/SiO2 interconnect technology. These alternative architectures will require the introduction of low-dielectric-constant k materials as the interlayer dielectrics and/or low-resistivity conductors such as copper. The electrical and thermomechanical properties of SiO2 are ideal for ILD applications, and a change to material with different properties has important process-integration implications. To facilitate the choice of an alternative ILD, it is necessary to establish general criterion for evaluating thin-film properties of candidate low-k materials, which can be later correlated with process-integration problems.

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Nieuwoudt, Arthur, Jamil Kawa, and Yehia Massoud. "Crosstalk-Induced Delay, Noise, and Interconnect Planarization Implications of Fill Metal in Nanoscale Process Technology." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18, no. 3 (March 2010): 378–91. http://dx.doi.org/10.1109/tvlsi.2008.2010830.

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Sato, T., Yu Cao, K. Agarwal, D. Sylvester, and Chenming Hu. "Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22, no. 5 (May 2003): 560–72. http://dx.doi.org/10.1109/tcad.2003.810750.

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Chen, Bin, Yi Lei, Gabriele Liga, Chigo Okonkwo, and Alex Alvarado. "Hard-Decision Coded Modulation for High-Throughput Short-Reach Optical Interconnect." Entropy 22, no. 4 (March 31, 2020): 400. http://dx.doi.org/10.3390/e22040400.

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Coded modulation (CM), a combination of forward error correction (FEC) and high order modulation formats, has become a key part of modern optical communication systems. Designing CM schemes with strict complexity requirements for optical communications (e.g., data center interconnects) is still challenging mainly because of the expected low latency, low overhead, and the stringent high data rate requirements. In this paper, we propose a CM scheme with bit-wise hard-decision FEC and geometric shaping. In particular, we propose to combine the recently introduced soft-aided bit-marking decoding algorithm for staircase codes (SCCs) with geometrically-shaped constellations. The main goal of this CM scheme is to jointly boost the coding gain and provide shaping gain, while keeping the complexity low. When compared to existing CM systems based on M-ary quadrature-amplitude modulation (MQAM, M = 64 , 128 , 256 ) and conventional decoding of SCCs, the proposed scheme shows improvements of up to 0 . 83 dB at a bit-error rate of 10 - 6 in the additive white Gaussian noise channel. For a nonlinear optical fiber system, simulation results show up to 24 % reach increase. In addition, the proposed CM scheme enables rate adaptivity in single-wavelength systems, offering six different data rates between 450 Gbit/s and 666 Gbit/s.

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Darveaux, Robert. "Escalating Challenges in Developing Complex Solutions for Next Generation Package and Interconnect Technologies." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, DPC (January 1, 2012): 001306–53. http://dx.doi.org/10.4071/2012dpc-keynote_fc_wlp_amkor.

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There are several application and device trends driving IC package development today. Among the most prevalent are:- Form factor reduction for handheld devices- Increased functionality requiring higher bandwidth- Higher power dissipation- Higher operating frequencies resulting in reduced electrical noise margins- Increased use of sensors- Full conversion to green material sets- Silicon node progression. These trends occur concurrently in many applications, which often results in conflicting requirements. In addition, the market continues to apply relentless pricing pressure on the supply chain. Hence, simple, cost-effective solutions are mandatory. This presentation will highlight packaging technology developments that address the device and application trends listed above. Several innovative packaging platforms will be discussed:- Copper pillar CSP and BGA- Through Mold Via Package on Package (TMV ® PoP)- Flip Chip Molded BGA (FCMBGA)- Wafer Level CSP- Through Silicon Via CSP and BGA. In each case a clear value proposition will be presented, along with key supporting data. It is truly an exciting time to be part of the industry solving complex packaging and interconnect challenges.

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Hanchate, Narender, and Nagarajan Ranganathan. "A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing." ACM Transactions on Design Automation of Electronic Systems 11, no. 3 (July 2006): 711–39. http://dx.doi.org/10.1145/1142980.1142988.

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Novais, Ashley, Carlos Calaza, José Fernandes, Helder Fonseca, Patricia Monteiro, João Gaspar, and Luis Jacinto. "Hybrid Multisite Silicon Neural Probe with Integrated Flexible Connector for Interchangeable Packaging." Sensors 21, no. 8 (April 8, 2021): 2605. http://dx.doi.org/10.3390/s21082605.

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Multisite neural probes are a fundamental tool to study brain function. Hybrid silicon/polymer neural probes combine rigid silicon and flexible polymer parts into one single device and allow, for example, the precise integration of complex probe geometries, such as multishank designs, with flexible biocompatible cabling. Despite these advantages and benefiting from highly reproducible fabrication methods on both silicon and polymer substrates, they have not been widely available. This paper presents the development, fabrication, characterization, and in vivo electrophysiological assessment of a hybrid multisite multishank silicon probe with a monolithically integrated polyimide flexible interconnect cable. The fabrication process was optimized at wafer level, and several neural probes with 64 gold electrode sites equally distributed along 8 shanks with an integrated 8 µm thick highly flexible polyimide interconnect cable were produced. The monolithic integration of the polyimide cable in the same fabrication process removed the necessity of the postfabrication bonding of the cable to the probe. This is the highest electrode site density and thinnest flexible cable ever reported for a hybrid silicon/polymer probe. Additionally, to avoid the time-consuming bonding of the probe to definitive packaging, the flexible cable was designed to terminate in a connector pad that can mate with commercial zero-insertion force (ZIF) connectors for electronics interfacing. This allows great experimental flexibility because interchangeable packaging can be used according to experimental demands. High-density distributed in vivo electrophysiological recordings were obtained from the hybrid neural probes with low intrinsic noise and high signal-to-noise ratio (SNR).

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Deutsch, A., H. H. Smith, B. J. Rubin, B. L. Krauter, and G. V. Kopcsay. "New Methodology for Combined Simulation of Delta-I Noise Interaction With Interconnect Noise for Wide, On-Chip Data-Buses Using Lossy Transmission-Line Power-Blocks." IEEE Transactions on Advanced Packaging 29, no. 1 (February 2006): 11–20. http://dx.doi.org/10.1109/tadvp.2005.862647.

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Kim, Taehoon, and Yungseon Eo. "Analytical CAD Models for the Signal Transients and Crosstalk Noise of Inductance-Effect-Prominent Multicoupled $RLC$ Interconnect Lines." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27, no. 7 (July 2008): 1214–27. http://dx.doi.org/10.1109/tcad.2008.923094.

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Verma, S. K., and B. K. Kaushik. "Bus encoder design for crosstalk and power reduction in RLC modelled VLSI interconnects." Journal of Engineering, Design and Technology 13, no. 3 (July 6, 2015): 486–98. http://dx.doi.org/10.1108/jedt-05-2013-0040.

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Purpose – This paper aims to reduce the worst-case crosstalk effects for resistance, inductance and capacitance (RLC) interconnects using the bus encoding technique. In current nanoscale technology, power dissipation, propagation delay and crosstalk performance of interconnects determine the overall performance of a chip. Signal integrity issues due to crosstalk in the form of voltage glitches, overshoots, undershoots, undesirable noise, propagation speed ups and downs, etc. are some of the major deterrents for high-performance RLC modelled (VLSI) interconnects. This research paper primarily proposes two novel encoding methods (I and II) for RLC modelled interconnects to reduce the effect of crosstalk, simultaneous switching noise (SSN) and power consumption. Design/methodology/approach – The proposed methods are based on the bus encoding method that is effective and well-suited for the reduction of the crosstalk noise. This method encodes or transforms incoming data in a manner that encoded data contain minimum or no crosstalk effects. The proposed encoding method uses the bus invert (BI) method. The proposed encoding methods are able to avoid the worst-case crosstalks while consuming lesser power during transmission in VLSI interconnects. Findings – It is observed that the proposed encoders reduced/eliminated the worst-case crosstalk by reducing SSN. The encoding method I also reduces Type 0 crosstalk by 100 per cent, while Type 1 crosstalk is reduced by 36.4 per cent and Type 2 is reduced by 16.8 per cent. The average simultaneous switching is reduced by 51.1 per cent. Similarly, encoding method II reduces switching activity by 10.3 per cent, whereas the coupling activity is reduced by 35.4 per cent. Furthermore, encoding method II also reduced Type 0, Type 1 and Type 2 crosstalk by 100, 36.9 and 27.1 per cent, respectively. Hence, the proposed encoding methods reduced the worst-case crosstalk completely. Research limitations/implications – In VLSI technology, the reduction in feature size and the increase in operating frequency are quite rapid. This leads to higher propagation delay, crosstalk and power dissipation through the interconnects. Most of the previously proposed encoders/decoders have turned out to be unsuitable for RLC modelled interconnects. Hence, the proposed encoder would be extremely useful for crosstalk reduction in newer operating conditions. Practical implications – The encoding method I identifies the harsh crosstalks, that is Type 0 and Type 1, in the inverted and non-inverted forms of incoming data with respect to the previous data. The data having minimum crosstalk in the inverted and non-inverted forms are only sent through the transmission line. The encoding method I also removes the worst-case crosstalk and simultaneously reduces other mild crosstalks. The removal of worst-case crosstalk improves the overall performance of the interconnect. The encoding method II identifies Type 2 crosstalk along with Type 0 and Type 1 similar to encoding method I. Furthermore, the encoding method II exhibits an improvement over method I in terms of reduction in crosstalk and power dissipation. Originality/value – This paper proposes a novel encoding method to reduce worst-case crosstalk effects that reduces SSN. The proposed encoding methods achieve their purpose of crosstalk reduction for several technology nodes.

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Dhaou, Imed Ben, Keshab K. Parhi, and Hannu Tenhunen. "Energy Efficient Signaling in Deep-submicron Technology." VLSI Design 15, no. 3 (January 1, 2002): 563–86. http://dx.doi.org/10.1080/1065514021000012192.

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In deep-submicron technology, global interconnect capacitances have started reaching several orders of magnitude greater than the intrinsic capacitances of the CMOS gates. The dynamic power consumption of a CMOS gate driving a global wire is the sum of the power dissipated due to (dis)charging (i) the intrinsic capacitance of the gate, and (ii) the wire capacitance. The latter is referred to as on-chip signaling power consumption. In this paper, a scheme has been proposed for combating crosstalk noise and reducing power consumption while driving the global wire at an optimal delay. This scheme is based on reduced voltage-swing signaling combined with buffer-insertion and resizing. The buffers are inserted and resized to compensate for the speed degradation caused by scaling the supply voltage and eradicating the crosstalk noise. A new buffer insertion algorithm called VIJIM has been described here, along with accurate delay and crosstalk-noise estimation algorithms for distributed RLC wires. The experimental results show that the VIJIM algorithm inserts fewer buffers into non-critical nets than does the existing buffer-insertion algorithms. In a 0.25 mm CMOS process, the experimental results show that energy savings of over 60% can be achived if the supply voltage is reduced from 2.5 to 1.5 V.

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Bjune, Caroline K., Thomas F. Marinis, Tirunelveli S. Sriram, Jeanne M. Brady, James Moran, Philip D. Parks, Alik S. Widge, Darin D. Dougherty, and Emad N. Eskandar. "Packaging Architecture for an Implanted System that Monitors Brain Activity and Applies Therapeutic Stimulation." International Symposium on Microelectronics 2015, no. 1 (October 1, 2015): 000548–54. http://dx.doi.org/10.4071/isom-2015-tha13.

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Deep brain stimulation therapies for Parkinson's disease utilize hardware, which from a packaging perspective, resembles that used in cardiac pacemakers. A hermetic package that contains stimulation electronics and a primary battery supply is implanted under the scalp in a recess cut into the skull. Stimulation probes, each with up to four electrodes, are inserted into the brain and connected to the electronics package via a plug and cable system. By contrast, the closed loop neural stimulator being developed under the DARPA SUBNETS program utilizes probes, which each carry up to 64 electrodes that can be switched between recording and stimulation functions. This capability necessitates locating low noise amplifiers, switching and communication electronics in close proximity to each probe. Each of these satellite electronics packages requires ten electrical connections to the hub package, which significantly increases the complexity of the interconnect system relative to current practice. The power requirements of this system preclude the use of a primary battery supply so instead, a large lithium ion battery is used with a recharging coil and electronics. The hub system is fabricated as a separate connector header, electronics package and battery pack that are interconnected by a flex circuit to allow it to conform to the skull for implanting. In this paper, we will describe the various packaging components of the system and the design considerations that drove our technology choices.

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Wu, Fu Pei, Yun Yi Geng, and Sheng Ping Li. "A Robust Location Algorithm for PCB's Solder Joints." Key Engineering Materials 562-565 (July 2013): 1373–79. http://dx.doi.org/10.4028/www.scientific.net/kem.562-565.1373.

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Printed circuit boards (PCBs) are being widely used in the electronic packages. Solder joints are often used to interconnect chip resistors and other components onto PCBs. The defects of solder joints will increase quality costs and deteriorate performance. If solder joints cant be located accuracy, AOI system will not inspect solder joints at the right place of solder joints and must lead to misjudgement. Especially, the misjudgement will increase dramatically under uncertain noise disturbance to micro-size solder joints due to inaccuracy location. In this work, an eliminating uncertain noise method is proposed and a robust location algorithm for PCBs solder joints is present. Firstly, some location windows are set based on technology parameters of chip and its solder joints, and solder joints feature image is obtained from it solder joint image based on series of image pre-processing. Secondly, the layout frame outside solder joints, which is viewed as a noise disturbance to location, is extracted as a binary image and is projected to X axis and Y axis, then the smaller region, which include solder joints but no the layout frame, is obtained based on calculating the sum features function of layout frame. Thirdly, the blob feature image of solder joints is extracted from its gray images of red, green, blue layers; it may have some noise blob around solder joints feature, then an evaluation function is develop to judge blob, which maybe belongs to noise or solder joints feature, and only solder joints feature are remained. Fourthly, with the help of setting solder joints windows, the integrated projection method is developed to locate solder joints. Finally, the proposed location method is compared with other two algorithms in the experiment. Experiments result illustrates that the smaller the solder joint size, the better location accuracy and efficiency is obtained than other two mothers.

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WANG, XINSHENG, YIZHE HU, LIANG HAN, JINGHU LI, CHENXU WANG, and MINGYAN YU. "A LOW POWER AND VARIATION-INSENSITIVE CURRENT-MODE SIGNALING SCHEME." Journal of Circuits, Systems and Computers 22, no. 08 (September 2013): 1350068. http://dx.doi.org/10.1142/s0218126613500680.

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Process and supply variations all have a large influence on current-mode signaling (CMS) circuits, limiting their application on the fields of high-speed low power communication over long on-chip interconnects. A variation-insensitive CMS scheme (CMS-Bias) was offered, employing a particular bias circuit to compensate the effects of variations, and was robust enough against inter-die and intra-die variations. In this paper, we studied in detail the principle of variation tolerance of the CMS circuit and proposed a more suitable bias circuit for it. The CMS-Bias with the proposed bias circuit (CMS-Proposed) can acquire the same variation tolerance but consume less energy, compared with CMS-Bias with the original bias circuit (CMS-Original). Both the CMS schemes were fabricated in 180 nm CMOS technology. Simulation and measured results indicate that the two CMS interconnect circuits have the similar signal propagation delay when driving signal over a 10 mm line, but the CMS-Proposed offers about 9% reduction in energy/bit and 7.2% reduction in energy-delay-product (EDP) over the CMS-Original. Simulation results show that the two CMS schemes only change about 5% in delay when suffering intra-die variations, and have the same robustness against inter-die variations. Both simulation and measurements all show that the proposed bias circuits, employing self-biasing structure, contribute to robustness against supply variations to some extent. Jitter analysis presents the two CMS schemes have the same noise performance.

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