Dissertations / Theses on the topic 'Interconnects (Integrated circuit technology) Copper Electrodiffusion'

"More Than Moore's Law" is the driving principle for the electronic packaging industry. This principle focuses on system integration instead of transistor density in order to achieve faster, thinner, and smarter electronic devices at a low cost. A core area of electronics packaging is interconnection technology, which enables ultra-miniaturization and high functional density. Solder bump technology is one of the original, and most common interconnection methods for flip chips. With growing demand for finer pitch and higher number of I/Os, solder bumps have been forced to smaller dimensions and therefore, are subjected to higher current densities. However, the technology is now reaching its fundamental limitations in terms of pitch, processability, and current-handling due to electromigration. Electromigration in solder bumps is one of the major causes of device failures. It is accelerated by many factors, one of which is current crowding. Current crowding is the non-uniform distribution of current at the interface of the solder bump and under-bump metallurgy, resulting in an increase in local current density and temperature. These factors, along with the formation of intermetallic compounds, can lead to voiding and ultimately failure. Electromigration in solder bumps has prevented pitch-scaling below 180-210 microns, producing a shift in the packaging industry to other interconnection approaches, specifically copper pillars with solder. This research aims to explore the electromigration resistance of an adhesive-based copper-to-copper (Cu-Cu) interconnection method without solder, which is thermo-compression bonded at a low temperature of 180C. While solder bumps are more susceptible to electromigration, Cu is capable of handling two orders of magnitude higher current density. This makes it an ideal candidate for next generation flip chip interconnections. Using finite element analysis, the current crowding and joule heating effects were evaluated for a 30 micron diameter Cu-Cu interconnection in comparison with two existing flip chip interconnection techniques, Cu pillar with solder and Pb-free solder. A test vehicle (TV) was fabricated for experimental analysis with 760 bumps arranged in an area-array format with a bump diameter of 30 micron. Thermo-mechanical reliability of the test vehicle was validated under thermal cycling from -55C to 125C. The Cu-Cu interconnections were then subjected to high current and temperature stress from 1E4 to 1E6 amps per square centimeter at a temperature of 130C. The results establish the high thermo-mechanical reliability and high electromigration resistance of the proposed Cu-Cu interconnection technology.

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Meindl, James; Committee Co-Chair: Davis, Jeffrey; Committee Member: Callen, Russell; Committee Member: Gaylord, Thomas; Committee Member: Kohl, Paul; Committee Member: Mukhopadhyay, Saibal. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Thesis (M. S.)--Chemical Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Kohl, Paul; Committee Member: Bidstrup Allen, Sue Ann; Committee Member: Fuller, Thomas; Committee Member: Hesketh, Peter; Committee Member: Hess, Dennis; Committee Member: Meindl, James.

One-dimensional (1D) nanomaterial self-assembly offers an excellent approach to the fabrication of highly complex nanodevices. Despite considerable effort and research, precisely controlling the orientation and positioning of nanowires (NWs) on a large-scale area and assembling into a functional device is still a state of the art problem. This thesis focuses on the dimensionally controlled copper nanowires (Cu NWs) synthesis, and magnetic field assisted self-assembly of cupronickel nanowires (Cu/Ni NWs) into interconnect structures on a carbon doped silicon dioxide (CDO) wafer. CDO is a low dielectric constant (k) material used for copper interconnects in multilayered complex integrated circuits (ICs). Here, a strong affinity of copper (Cu) and nickel (Ni) to thiol (-SH) functional groups were exploited to strongly adhere the nanowires (Cu/Ni NWs) onto the CDO substrate. Thiol (-SH) functionalization of the CDO surface was achieved via a series of reactions involving (1) esterification of the surface exposed ≡Si-OH functional group to its triflate (≡Si-O-Tf), (2) reduction of triflate to ≡Si-H using DIBAL-H, and (3) hydrosilylation of ≡Si-H using 2-propene thiol (≡Si-(CH2)3-SH) in a photochemical reaction. The thiol functionalization of CDO surface enhances the interaction of Cu/Ni NWs with strong chemical bonds. The same reaction scheme was also used in the functionalization of the hydrophilic (Si-OH) surface to the hydrophobic long alkyl chain derivatized (≡Si-CH2-(CH2)16-CH3) surface. This long alkyl chain modified surface acts as an excellent moisture resistant film, which helps to maintain the low-k value of CDO. The dimensionally controlled Cu NWs were synthesized by a wet chemical approach. Optimization of the reducing agent, hydrazine (N2H4), controlled the surface morphology of nanowires (NWs). Interestingly, the high concentration of reducing agent produced particle decorated and/or with a rough NW surface, and conversely decreasing its concentration resulted in a comparatively thin, particle-free and smooth surface. The reaction temperature affected the aspect ratio (Length/Diameter) of the NWs. As the reaction temperature increased from 60 to 90 °C, the aspect ratio decreased from 140 to 21. Controlling the orientation of Cu NWs in a magnetic field was accomplished by coating them with a thin layer (~20 nm) of ferromagnetic nickel (Ni). This Ni-coated NWs showed an excellent degree of alignment (half-width ≈10 degrees) in the direction of an applied magnetic field over a large surface area at field strength as low as 2500 Gauss. Also, the Ni coating helped in protecting the copper core from oxidation resulting in better electrical wire-to-wire contacts. A nanowire-based interconnect channel was fabricated by combining magnetic field assisted alignment and deposition of aligned NWs on a thiol-modified and photolithography patterned CDO substrate. The NWs, deposited in the trenches, strongly bonded to the thiol-derivatized CDO substrate while an acetone wash removed loosely bound NWs on the photoresist surface. In electrical characterization, the directionally well-aligned Cu/Ni NWs channel displayed surprisingly two-fold higher conductivity than randomly arranged NWs channel.

The international technology roadmap for semiconductors (ITRS) 2012 report foresees the use of porous dielectric materials with a low dielectric constant in conjunction with copper interconnects as a way to reduce the resistive-capacitive (RC) delay in microelectronic applications. However, the introduction of pores in the dielectric not only serves as stress raisers but also diminishes the structural strength of the material. The challenge therefore with the implementation of low-k dielectrics for high-performance flip-chip packages is to create a reliable die to organic substrate interconnect solution which induces low stresses on the die to prevent the cohesive cracking and the interfacial delamination of the dielectric material. Potential interconnect solutions that meet this challenge are MEMS-like compliant freestanding micro-structures. These structures are designed to work as spring-like elements which allow the free lateral and out-of-plane motion between the silicon die and the organic substrate under assembly conditions as well as under thermal or power cycling. Thus, the focus of this research is to design, fabricate, and characterize electrically and mechanically an innovative compliant interconnect approach that addresses these challenges. The proposed interconnect is scalable in dimensions and pitch, and consists multiple electrical paths which will provide redundancy against interconnect failure. The multi-path design employs parallel electrical paths which effectively split a larger cross-sectional area into several smaller areas making the overall design more compliant than otherwise. This research proposes wafer-level, high-yield, CMOS-compatible fabrication procedure using sequential photolithography and copper electroplating. The proposed interconnects are symmetric and are amenable to easy reflow assembly to substrates. The mechanical compliance of the fabricated structures is studied through nano-indentation, while the electrical characteristics are assessed through fabricated prototypes. The xvi thermo-mechanical reliability of compliant interconnects is also demonstrated. Lastly, the dimensional scalability of the interconnects is also demonstrated.

Thesis (M. S.)--Materials Science and Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Rao R. Tummala; Committee Co-Chair: Ashok Saxena; Committee Member: Karl Jacob; Committee Member: Suresh Sitaraman; Committee Member: Thomas H. Sanders, Jr.

Although copper (Cu) is the preferred interconnect material due to its lower resistivity than aluminum (Al), Cu subtractive etching processes have not been developed at temperatures less than 180 °C, primarily due to the inability to form volatile etch products at low temperature. The conventional damascene technology avoids the need for subtractive etching of Cu by electroplating Cu into previously etched dielectric trenches/vias, followed by a chemical/mechanical planarization (CMP) process. However, a critical "size effect" limitation has arisen for damascene technology as a result of the continuing efforts to adhere to "Moore's Law". The size effect relates to the fact that the resistivity of damascene-generated lines increases dramatically as the line width approaches the sub-100 nm regime, where feature size is similar to the mean free path of electrons in Cu (40 nm). As a result, an alternative Cu patterning process to that of damascene may offer advantages for device speed and thus operation. This thesis describes investigations into the development of novel, fully-plasma based etch processes for Cu at low temperatures (10 °C). Initially, the investigation of a two-step etch process has been studied. This etch approach was based on a previous thermodynamic analysis of the Cu-Cl-H system by investigators at the University of Florida. In the first step, Cu films are exposed to a Cl₂ plasma to preferentially form CuCl₂, which is believed to be volatilized as Cu₃Cl₃ by subsequent exposure to a hydrogen (H₂) plasma (second step). Patterning of Cu films masked with silicon dioxide (SiO₂) layers in an inductively coupled plasma (ICP) reactor indicates that the H₂ plasma step in the two-step process is the limiting step in the etch process. This discovery led to the investigation of a single step Cu etch process using a pure H₂ plasma. Etching of blanket Cu films and Cu film patterning at 10°C, display an etch rate ~ 13 nm/min; anisotropic etched features are also observed. Comparison of H₂ plasma etching to sputtering of Cu films in argon (Ar) plasmas, indicates that both a chemical component and a physical component are involved in the etching mechanism. Additional studies using helium plasmas and variation of power applied to the plasma and etching surface demonstrate that the etch rate is controlled by reactive hydrogen species, ion bombardment flux and likely photon flux. Optical Emission Spectroscopy (OES) of the H₂ plasma during the Cu etching process detects Cu emission lines, but is unable to identify specific Cu etch products that desorb from the etching surface. Variation of Cu etch rates as a function of temperature suggests a change in mechanism for the removal of Cu over the temperature of -150 °C to 150 °C. OES analyses also suggest that the Cl₂ plasma step in the two-step process can inhibit Cu etching, since the subsequent H₂ (second) plasma step shows a time delay in film removal. Preliminary results of the etching of the SiO₂ mask material in H₂ plasmas with various intentionally introduced contaminants demonstrate the robustness of the H₂ plasma Cu etch process.

As multistep, multilayer processing in semiconductor industry becomes more complex, the role of cleaning solutions and etching chemistries are becoming important in enhancing yield and in reducing defects. This thesis demonstrates successful formulations that exhibit copper and tungsten compatibility, and are capable of Inter Layer Dielectric (ILD) cleaning and selective Ti etching. The corrosion behavior of electrochemically deposited copper thin films in deareated and non-dearated cleaning solution containing hydrofluoric acid (HF) has been investigated. Potentiodynamic polarization experiments were carried out to determine active, active-passive, passive, and transpassive regions. Corrosion rates were calculated from tafel slopes. ICP-MS and potentiodynamic methods yielded comparable Cu dissolution rates. Interestingly, the presence of hydrogen peroxide in the cleaning solution led to more than an order of magnitude suppression of copper dissolution rate. We ascribe this phenomenon to the formation of interfacial CuO which dissolves at slower rate in dilute HF. A kinetic scheme involving cathodic reduction of oxygen and anodic oxidation of Cu0 and Cu+1 is proposed. It was determined that the reaction order kinetics is first order with respect to both HF and oxygen concentrations. The learnings from copper corrosion studies were leveraged to develop a wet etch/clean formulation for selective titanium etching. The introduction of titanium hard-mask (HM) for dual damascene patterning of copper interconnects created a unique application in selective wet etch chemistry. A formulation that addresses the selectivity requirements was not available and was developed during the course of this dissertation. This chemical formulation selectively strips Ti HM film and removes post plasma etch polymer/residue while suppressing the etch rate of tungsten, copper, silicon oxide, silicon carbide, silicon nitride, and carbon doped silicon oxide. Ti etching selectivity exceeding three orders of magnitude was realized. Surprisingly, it exploits the use of HF, a chemical well known for its SiO2 etching ability, along with a silicon precursor to protect SiO2. The ability to selectively etch the Ti HM without impacting key transistor/interconnect components has enabled advanced process technology nodes of today and beyond. This environmentally friendly formulation is now employed in production of advanced high-performance microprocessors and produced in a 3000 gallon reactor.

Thesis (Ph. D.)--State University of New York at Binghamton, Department of Systems Science and Industrial Engineering, Thomas J. Watson School of Engineering and Applied Science, 2008.
Includes bibliographical references.

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.
Committee Chair: Jeffrey A. Davis; Committee Co-Chair: James D. Meindl; Committee Member: Azad J. Naeemi; Committee Member: Dennis W. Hess; Committee Member: George F. Riley; Committee Member: Linda S. Milor. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Small form-factor packages with high integration density are driving the innovations in chip-to-package interconnections. Metallurgical interconnections have evolved from the conventional eutectic and lead-free solders to fine pitch copper pillars with lead-free solder cap. However, scaling down the bump pitch below 50-80µm and increasing the interconnect density with this approach creates a challenge in terms of accurate solder mask lithography and joint reliability with low stand-off heights. Going beyond the state of the art flip-chip interconnection technology to achieve ultra-fine bump pitch and high reliability requires a fundamentally- different approach towards highly functional and integrated systems. This research demonstrates a low-profile copper-to-copper interconnect material and process approach with less than 20µm total height using adhesive bonding at lower temperature than other state-of-the-art methods. The research focuses on: (1) exploring a novel solution for ultra-fine pitch (< 30µm) interconnections, (2) advanced materials and assembly process for copper-to-copper interconnections, and (3) design, fabrication and characterization of test vehicles for reliability and failure analysis of the interconnection. This research represents the first demonstration of ultra-fine pitch Cu-to-Cu interconnection below 200°C using non-conductive film (NCF) as an adhesive to achieve bonding between silicon die and organic substrate. The fabrication process optimization and characterization of copper bumps, NCF and build-up substrate was performed as a part of the study. The test vehicles were studied for mechanical reliability performance under unbiased highly accelerated stress test (U-HAST), high temperature storage (HTS) and thermal shock test (TST). This robust interconnect scheme was also shown to perform well with different die sizes, die thicknesses and with embedded dies. A simple and reliable, low-cost and low-temperature direct Cu-Cu bonding was demonstrated offering a potential solution for future flip chip packages as well as with chip-last embedded active devices in organic substrates.

Multi-chip integration with emerging technologies such as a 3D IC stack or 2.5D interposer is primarily enabled by the off-chip interconnections. The I/O density, speed and bandwidth requirements for emerging mobile and high-performance systems are projected to drive the interconnection pitch to less than 20 microns by 2015. A new class of low-temperature, low-pressure, high-throughput, cost-effective and maufacturable technologies are needed to enable such fine-pitch interconnections. A range of interconnection technologies are being pursued to achieve these fine-pitch interconnections, most notably direct Cu-Cu interconnections and copper pillars with solder caps. Direct Cu-Cu bonding has been a target in the semiconductor industry due to the high electrical and thermal conductivity of copper, its high current-carrying capability and compatibility with CMOS BEOL processes. However, stringent coplanarity requirements and high temperature and high pressure bonding needed for assembly have been the major barriers for this technology. Copper-solder interconnection technology has therefore become the main workhouse for off-chip interconnections, and has recently been demonstrated at pitches as low as 40 microns. However, the current interconnection approaches using copper-solder structures are not scalable to finer feature sizes due to electromigration, and reliability issues arising with decreased solder content. Solid Liquid Inter-Diffusion (SLID) bonding is a promising solution to achieve ultra-fine-pitch and ultra-short interconnections with a copper-solder system, as it relies on the conversion of the entire solder volume into thermally-stable and highly electromigration-resistant intermetallics with no residual solder. Such a complete conversion of solders to stable intermetallics, however, relies on a long assembly time or a subsequent post-annealing process. To achieve pitches lower than 30 micron pitch, this research aims to study two ultra-short copper-solder interconnection approaches: (i) copper pillar and solder cap technology, and (ii) a novel technology which will enable interconnections with improved electrical performance by fast and complete conversion of solders to stable intermetallics (IMCs) using Solid Liquid Diffusion (SLID) bonding approach. SLID bonding, being a liquid state diffusion process, combined with a novel, alternate layered copper-solder bump structure, leads to higher diffusion rates and a much faster conversion of solder to IMCs. Moreover this assembly bonding is done at a much lower temperature and pressure as compared to that used for Cu-Cu interconnections. FEM was used to study the effect of various assembly and bump-design characteristics on the post-assembly stress distribution in the ultra-short copper-solder joints, and design guidelines were evolved based on these results. Test vehicles, based on these guidelines, were designed and fabricated at 50 and 100 micron pitch for experimental analysis. The bumping process was optimized, and the effect of current density on the solder composition, bump-height non-uniformity and surface morphology of the deposited solder were studied. Ultra-short interconnections formed using the copper pillar and solder cap technology were characterized. A novel multi-layered copper-solder stack was designed based on diffusion modeling to optimize the bump stack configuration for high-throughput conversion to stable Cu3Sn intermetallic. Following this modeling, a novel bumping process with alternating copper and tin plating layers to predesigned thicknesses was then developed to fabricate the interconnection structure. Alternate layers of copper and tin were electroplated on a blanket wafer, as a first demonstration of this stack-technology. Dies with copper-solder test structures were bonded using SLID bonding to validate the formation of stable intermetallics.

The microelectronics industry has been managing the RC delay problem arising from aggressive line scaling, by replacing aluminum (Al) by copper (Cu) and oxide dielectric by low-k dielectric. Electromigration (EM) turned out to be a serious reliability problem for Cu interconnects due to the implementation of mechanically weaker low-k dielectrics. In addition, line width and via size scaling resulted in the need of a novel diffusion barrier, which should be uniform and thin. The objective of this dissertation is to investigate the impacts of Ta barrier process, such as barrier-first and pre-clean first, and scaling of barrier and line/via on EM reliability of Cu/low-k interconnects. For this purpose, EM statistical test structures, having different number of line segments, line width, and via width, were designed. The EM test structures were fabricated by a dualdamascene process with two metal layers (M1/Via/M2), which were then packaged for EM tests. The package-level EM tests were performed in a specially designed vacuum chamber with pure nitrogen environment. The novel barrier deposition process, called barrier-first, showed a higher (jL)[subscript c] product and prolonged EM lifetime, compared with the conventional Ta barrier deposition process, known as pre-clean first. This can be attributed to the improved uniformity and thickness of the Ta layer on the via and trench, as confirmed by TEM. As for the barrier thickness effect, the (jL)c product decreased with decreasing thickness, due to reduced Cu confinement. A direct correlation between via size and EM reliability was found; namely, EM lifetime and statistics degraded with via size. This can be attributed to the fact that critical void length to cause open circuit is about the size of via width. To investigate further line scaling effect on EM reliability, SiON (siliconoxynitride) trenchfilling process was introduced to fabricate 60-nm lines, corresponding to 45-nm technology, using a conventional, wider line lithograph technology. The EM lifetime of 60-nm fine lines with SiON filling was longer than that of a standard damascene structure, which can be attributed to a distinct via/metal-1 configuration in reducing process-induced defects at the via/metal-1 interface.
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M. Tech. Metallurgical Engineering.
Aims at improving Cu interconnection problem by homogeneous distribution of ruthenium and tantalum in Cu matrix for excellent interconnection in electronics packaging. The aim will be achieved through the following objectives.Development of appropriate technology for homogenizing submicron metal powders with suitable methods for controlling grain growth during sintering. Study the mechanisms of synergistic incorporation of Ru, and Ta on improving copper interconnection properties. To investigate metallurgical interactions and phenomena occurring during sintering. To investigate specific property and behaviour advantages intrinsic due to the composites and material mix.