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Journal articles on the topic 'Interconnects (Integrated circuit technology) Copper'

Author: Grafiati

Published: 4 June 2021

Last updated: 18 February 2022

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1

Sahoo, Manodipan, and Hafizur Rahaman. "Analysis of Crosstalk-Induced Effects in Multilayer Graphene Nanoribbon Interconnects." Journal of Circuits, Systems and Computers 26, no. 06 (2017): 1750102. http://dx.doi.org/10.1142/s021812661750102x.

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Crosstalk effects in multilayer graphene nanoribbon (GNR) interconnects for the future nanoscale integrated circuits are investigated with the help of ABCD parameter matrix approach for intermediate- and global-level interconnects at 11[Formula: see text]nm and 8[Formula: see text]nm technology nodes. The worst-case crosstalk-induced delay and peak crosstalk noise voltages are derived for both neutral and doped zigzag GNR interconnects and compared to those of conventional copper interconnects. The worst-case crosstalk delays for perfectly specular, doped multilayer GNR interconnects are less

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Plovie, Bart, Sheila Dunphy, Kristof Dhaenens, et al. "2.5D Smart Objects Using Thermoplastic Stretchable Interconnects." International Symposium on Microelectronics 2015, no. 1 (2015): 000868–73. http://dx.doi.org/10.4071/isom-2015-thp51.

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This contribution describes the technology used to produce thermoplastically deformable electronics, based on flexible circuit board technology, to achieve low-cost 2.5D free-form rigid smart objects. These one-time deformable circuits employ a modified version of the previously developed meander-based “polymer-last” technology for dynamically stretchable elastic circuits. This is readily achieved by substituting the dynamically stretchable elastomeric materials (e.g. silicone) with thermoplastic polymers (e.g. polycarbonate). Afterwards the circuit is given its final form using widely availab

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Karthikeyan, A., and P. S. Mallick. "Optimization Techniques for CNT Based VLSI Interconnects — A Review." Journal of Circuits, Systems and Computers 26, no. 03 (2016): 1730002. http://dx.doi.org/10.1142/s0218126617300021.

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Interconnects plays an important role in integrated circuits. Copper is used as an interconnect material, but beyond 22[Formula: see text]nm technology node it faces many problems due to grain boundary scattering, and therefore carbon nanotubes are the most promising future interconnect materials. Various techniques and approaches such as driver sizing, repeater sizing, repeater insertion, wire sizing, wire spacing, shielding, boos table repeater were used by various researchers. Many of these techniques can be utilized for future CNT based VLSI interconnects as well. This paper presents a det

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Kureshi, Abdul Kadir, and Mohd Hasan. "Analysis of CNT Bundle and Its Comparison with Copper Interconnect for CMOS and CNFET Drivers." Journal of Nanomaterials 2009 (2009): 1–6. http://dx.doi.org/10.1155/2009/486979.

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In nanoscale regime as the CMOS process technology continues to scale, the standard copper (Cu) interconnect will become a major hurdle for onchip communication due to high resistivity and electromigration. This paper presents the comprehensive evaluation of mixed CNT bundle interconnects and investigates their prospects as a low power high-speed interconnect for future nanoscale-integrated circuits. The performance of mixed CNT bundle interconnect is examined with carbon nanotube field effect transistor (CNFET) as a driver and compared with the traditional interconnect, that is, CMOS driver o

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Sahoo, Manodipan, and Hafizur Rahaman. "Modeling of Crosstalk Induced Effects in Copper-Based Nanointerconnects: An ABCD Parameter Matrix-Based Approach." Journal of Circuits, Systems and Computers 24, no. 02 (2014): 1540007. http://dx.doi.org/10.1142/s0218126615400071.

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Aggressive miniaturization has led to severe performance and signal integrity issues in copper-based interconnects in the nanometric regime. As a consequence, development of a proper analytical model for such interconnects is extremely important. In this work, an ABCD parameter matrix-based model is presented for fast and accurate estimation of crosstalk delay and noise for identically coupled copper-based nanointerconnect systems. Using the proposed model, the crosstalk delay and noise are estimated in copper based nanointerconnects for intermediate and global interconnects at the future inte

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Rebelli, Shashank, and Bheema Rao Nistala. "A novel MRTD model for signal integrity analysis of resistive driven coupled copper interconnects." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 37, no. 1 (2018): 189–207. http://dx.doi.org/10.1108/compel-12-2016-0521.

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Purpose This paper aims to model the coupled on-chip Copper (Cu) interconnects by using the multiresolution time-domain (MRTD) method. Design/methodology/approach The proposed model is a wavelet-based numerical method for analyzing signal integrity and propagation delay of coupled on-chip interconnects. Moreover, the dependency of crosstalk noise and delay on coupling parasitics (L12, C12) are analyzed. Findings The proposed MRTD method captures the behaviour of propagation delay and peak crosstalk noise on victim line against coupling parasitics, which is in close agreement with that of H sim

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Sharma, Himanshu, and Karmjit Singh Sandha. "Impact of Intercalation Doping on the Conductivity of Multi-Layer Graphene Nanoribbon (MLGNR) in On-Chip Interconnects." Journal of Circuits, Systems and Computers 29, no. 12 (2020): 2050185. http://dx.doi.org/10.1142/s0218126620501856.

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Graphene nanoribbons are considered potentially suitable and have exhibited excellent results in on-chip interconnects. In order to evaluate the different circuit impedance parameters of multi-layer graphene nanoribbons (MLGNRs), an electrical equivalent single conductor (ESC) along with an analytical model is proposed. On the basis of an electrical model, the impact of intercalation doping on the performance of MLGNRs at 32, 22, and 16[Formula: see text]nm technology nodes is discussed in this paper. Moreover, it is also discussed that the increase in intercalation doping increases the Fermi

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Khursheed, Afreen, and Kavita Khare. "Designing dual-chirality and multi-Vt repeaters for performance optimization of 32 nm interconnects." Circuit World 46, no. 2 (2020): 71–83. http://dx.doi.org/10.1108/cw-06-2019-0060.

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Purpose This paper is an unprecedented effort to resolve the performance issue of very large scale integrated circuits (VLSI) interconnects encountered because of the scaling of device dimensions. Repeater interpolation technique is an effective approach for enhancing speed of interconnect network. Proposed buffers as repeater are modeled by using dual chirality multi-Vt technology to reduce delay besides mitigating average power consumption. Interconnects modeled with carbon nanotube (CNT) technology are compared with copper interconnect for various lengths. Buffer circuits are designed with

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9

Neirynck, J. M., R. J. Gutmann, and S. P. Murarka. "Copper/Benzocyclobutene Interconnects for Sub‐100 nm Integrated Circuit Technology: Elimination of High‐Resistivity Metallic Liners and High‐Dielectric Constant Polish Stops." Journal of The Electrochemical Society 146, no. 4 (1999): 1602–7. http://dx.doi.org/10.1149/1.1391812.

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10

Wang, Juan, Ru Wang, and Guo Dong Chen. "Evaluation of the Stability on the New Alkaline Copper Bulk Slurry." Key Engineering Materials 645-646 (May 2015): 352–55. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.352.

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At present, the chemical mechanical polishing is the only means for global planarization of an integrated circuit. After the node of the integrated circuit processing comes into 45nm, the diameter of wafer is 300mm, and the copper interconnect layer is above the 10 layer. In the same time the new low dielectric constant materials are used to the integrated circuit processing. That requires the property of the slurry used in the chemical mechanical polishing stricter. So the domestic and international companies carry out a series research works. Based on investigation and research for many year

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Lamy, Yann, Haykel Ben Jamaa, Hughes Metras, Stéphane Bernabé, Sylvie Menezo, and Laurent Fulbert. "Heterogeneous Integration of Photonic Integrated Circuits Using 3D Assembly Techniques: Silicon Technology and Packaging." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, DPC (2014): 002057–86. http://dx.doi.org/10.4071/2014dpc-tha31.

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The large internet companies' investments indicate an ongoing increase of data-based business volume through the next decades with the rise of the internet of things and the continuous growth of communication and data facilities. The two-figure yearly growth rate of exchanged data volume within data centers is challenging the actual short distance communication paradigms. With datacenter architectures getting larger and “flatter”, the availability of high bandwidth, low power and low cost optical links ranging from less than 1 meter to 1 kilometer is a key issue. It is therefore expected that

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Merschky, Michael, Fabian Michalik, Martin Thoms, et al. "Using a Metal Oxide Adhesion Layer and Wet Chemical Cu Metallization for Fine Line Pattern Formation on Glass." International Symposium on Microelectronics 2017, no. 1 (2017): 000458–63. http://dx.doi.org/10.4071/isom-2017-wp51_084.

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Abstract With the trends towards miniaturization and heterogeneous integration, both IC and advanced substrate manufacturers are striving to meet the needs of next generation platforms, to increase the density of interconnects, and generate conductors featuring finer lines and spaces. Advanced manufacturing technologies such as Semi-Additive-Processing (SAP) and Advanced Modified-Semi-Additive-Processing (amSAP) were devised, realized and implemented in order to meet these requirements. Line and space (L/S) requirements of copper conductors will be below 5/5μm for advanced substrates, with 2/2

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Flemming, Jeb, Kyle McWethy, Tim Mezel, Luis Chenoweth, and Carrie Schmidt. "Photosensitive Glass-Ceramics for Heterogeneous Integration." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (2019): 000880–907. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_wp1_036.

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The push for heterogeneous integration requires very unique material properties with respect to processing, material constants, and integration capabilities with other materials (such as copper, III–V, magnetics, etc.). Current common circuit board materials such as ceramics and laminates, as well as silicon substrates, suffer from a variety of limitations. For ceramics and laminates, these constraints include: (1) the inability to produce narrow line widths &lt;100 m with narrow gaps between lines &lt;100 m; (2) high surface roughness (on the order of 2μm RMS); (3) layer-to-layer misa

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McNally, P. J., J. Kanatharana, B. H. W. Toh, et al. "Geometric linewidth and the impact of thermal processing on the stress regimes induced by electroless copper metallization for Si integrated circuit interconnect technology." Journal of Applied Physics 96, no. 12 (2004): 7596–602. http://dx.doi.org/10.1063/1.1811780.

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15

Marsan-Loyer, C., D. Danovitch, and N. Boyer. "Addressing Flux Dip Challenges for 3-D Integrated Large Die, Ultrafine Pitch Interconnect." Journal of Microelectronics and Electronic Packaging 14, no. 1 (2017): 32–38. http://dx.doi.org/10.4071/imaps.348081.

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The requirement for closely coupled, highly integrated circuits in the semiconductor industry has spawned alternative packaging innovations such as 2.5-D/3-D integration. The incredible potential of this alternative comes with great challenges, not the least of which is the unprecedented reduction in package interconnection pitch. Market acceptance of new fine-pitch microelectronic products is strongly dependent on the development of flawless assembly processes that align with the traditional Moore-like expectation of higher performance without cost penalty. One such process is the application

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Marsan-Loyer, C., D. Danovitch, and N. Boyer. "Addressing Flux Dip Challenges for 3D Integrated Large Die, Ultra-fine Pitch Interconnect." International Symposium on Microelectronics 2016, no. 1 (2016): 000054–59. http://dx.doi.org/10.4071/isom-2016-tp25.

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Abstract The requirement for closely coupled, highly integrated circuits in the semiconductor industry has spawned alternative packaging innovations such as 2.5D/3D integration. The incredible potential of this alternative comes with great challenges, not the least of which is the unprecedented reduction in package interconnection pitch. Market acceptance of new fine-pitch microelectronic products is strongly dependent upon the development of flawless assembly processes that align with the traditional Moore-like expectation of higher performance without cost penalty. One such process is the ap

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17

Bai, Jiang Hao, Xiao Dong Xiong, Jun Feng Luo, Guo Jin Xu, and Yong Jun Li. "Progress of Microstructure and Texture of High Purity Tantalum Sputtering Target." Materials Science Forum 1035 (June 22, 2021): 704–11. http://dx.doi.org/10.4028/www.scientific.net/msf.1035.704.

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In recent years, the IC (integrated circuit) industry has developed rapidly and the chip process technology has developed in the direction of higher density. Because of its good chemical stability, tantalum is used as a sputtering coating material for the diffusion barrier in the copper interconnect process. The uniform microstructure of the tantalum target directly affects the sputtering performance. The fabrication of high-quality thin films requires the tantalum target to have fine and uniform crystal grains and random grain orientation distribution. However, due to the characteristics of t

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Light, Edward D., Victor Lieu, and Stephen W. Smith. "New Fabrication Techniques for Ring-Array Transducers for Real-Time 3D Intravascular Ultrasound." Ultrasonic Imaging 31, no. 4 (2009): 247–56. http://dx.doi.org/10.1177/016173460903100403.

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We have previously described miniature 2D array transducers integrated into a Cook Medical, Inc. vena cava filter deployment device. While functional, the fabrication technique was very labor intensive and did not lend itself well to efficient fabrication of large numbers of devices. We developed two new fabrication methods that we believe can be used to efficiently manufacture these types of devices in greater than prototype numbers. One transducer consisted of 55 elements operating near 5 MHz. The interelement spacing is 0.20 mm. It was constructed on a flat piece of copper-clad polyimide an

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Doppelt, Pascal, and Thomas H. Baum. "Chemical Vapor Deposition of Copper for IC Metallization: Precursor Chemistry and Molecular Structure." MRS Bulletin 19, no. 8 (1994): 41–48. http://dx.doi.org/10.1557/s0883769400047722.

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In the microelectronics industry, integrated circuit (IC) device performance is continually increasing while the critical feature sizes are rapidly decreasing. Since this trend is expected to continue for future generations of ICs, areal density constraints often require that circuit designs utilize multilevel structures with vertical interconnects. It was recently demonstrated that the resistivity of the metal interconnects may limit device performance in multilevel thin-film structures. Although Al metallurgy (Al/2 wt.% Cu alloy) is extensively used for IC metallization today, lower resistiv

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Berry, G. J., J. A. Cairns, and J. Thomson. "New material for the production of fine line interconnects in integrated circuit technology." Journal of Materials Science Letters 14, no. 12 (1995): 844–46. http://dx.doi.org/10.1007/bf00639302.

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Sakata, Shuichi, Akinori Umeno, Kenji Yoshida, and Kazuhiko Hirakawa. "Critical Voltage for Atom Migration in Ballistic Copper Nanojunctions and Its Implications to Interconnect Technology for Very Large Scale Integrated Circuits." Applied Physics Express 3, no. 11 (2010): 115201. http://dx.doi.org/10.1143/apex.3.115201.

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Tehrani, Bijan K., Ryan A. Bahr, and Manos M. Tentzeris. "Inkjet and 3D Printing Technology for Fundamental Millimeter-Wave Wireless Packaging." Journal of Microelectronics and Electronic Packaging 15, no. 3 (2018): 101–6. http://dx.doi.org/10.4071/imaps.660476.

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Abstract This article outlines the design, processing, and implementation of inkjet and 3D printing technologies for the development of fully printed, highly integrated millimeter-wave (mm-wave) wireless packages. The materials, tools, and processes of each technology are outlined and justified for their respective purposes. Inkjet-printed 3D interconnects directly interfacing a packaging substrate with an integrated circuit (IC) die are presented using printed dielectric ramps and coplanar waveguide transmission lines exhibiting low loss (.6–.8 dB/mm at 40 GHz). Stereolithography 3D printing

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Zhao, Wen-Sheng, Kai Fu, Da-Wei Wang, Meng Li, Gaofeng Wang, and Wen-Yan Yin. "Mini-Review: Modeling and Performance Analysis of Nanocarbon Interconnects." Applied Sciences 9, no. 11 (2019): 2174. http://dx.doi.org/10.3390/app9112174.

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As the interconnect delay exceeds the gate delay, the integrated circuit (IC) technology has evolved from a transistor-centric era to an interconnect-centric era. Conventional metallic interconnects face several serious challenges in aspects of performance and reliability. To address these issues, nanocarbon materials, including carbon nanotube (CNT) and graphene, have been proposed as promising candidates for interconnect applications. Considering the rapid development of nanocarbon interconnects, this paper is dedicated to providing a mini-review on our previous work and on related research

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T, Sridhar, and Dr A. S. R Murty. "Low power driver receiver topology with delay optimization for on-chip bus interconnects." International Journal of Engineering & Technology 7, no. 3.29 (2018): 180. http://dx.doi.org/10.14419/ijet.v7i3.29.18554.

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Demands on reducing the delay and power on integrated circuits is increasing with the development of more and more low power devices. The technology scaling and the device design manage static power dissipation. However, the dynamic power dissipation and the delays associated with the bus interconnects have to be addressed separately. A low swing driver-receiver circuit for driving and receiving the signals on the global bus interconnects is presented. Also the capacitively driven interconnects are used for the signal transmission and a series coupling capacitor is introduced at an optimized l

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Spry, David J., Philip G. Neudeck, Liang-Yu Chen, et al. "Processing and Characterization of Thousand-Hour 500 °C Durable 4H-SiC JFET Integrated Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (2016): 000249–56. http://dx.doi.org/10.4071/2016-hitec-249.

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Abstract This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 °C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over ~ 1-μm scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 °C operational testing. These results advance the technology

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Lennon, Alison, Jack Colwell, and Kenneth P. Rodbell. "Challenges facing copper-plated metallisation for silicon photovoltaics: Insights from integrated circuit technology development." Progress in Photovoltaics: Research and Applications 27, no. 1 (2018): 67–97. http://dx.doi.org/10.1002/pip.3062.

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Lu, Tien-Lin, Yu-An Shen, John A. Wu, and Chih Chen. "Anisotropic Grain Growth in (111) Nanotwinned Cu Films by DC Electrodeposition." Materials 13, no. 1 (2019): 134. http://dx.doi.org/10.3390/ma13010134.

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We have reported a method of fabricating (111)-orientated nanotwinned copper (nt-Cu) by direct current electroplating. X-ray analysis was performed for the samples annealed at 200 to 350 °C for an hour. X-ray diffraction indicates that the (200) signal intensity increases while (111) decreases. Abnormal grain growth normally results from transformation of surface energy or strain energy density. The average grain size increased from 3.8 µm for the as-deposited Cu films to 65–70 µm after the annealing at 250 °C for 1 h. For comparison, no significant grain growth behavior was observed by random

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Li, Jian, Tom E. Seidel, and Jim W. Mayer. "Copper-Based Metallization in ULSI Structures: Part II: Is Cu Ahead of Its Time as an On-Chip Interconnect Material?" MRS Bulletin 19, no. 8 (1994): 15–21. http://dx.doi.org/10.1557/s0883769400047692.

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The demand for manufacturing integrated circuit (IC) devices such as dynamic random access memory (DRAM), static random access memory (SRAM), electrically erasable and programmable read only memory (EEPROM) and logic devices with high circuit speed, high packing density and low power dissipation requires the downward scaling of feature sizes in ultralarge-scale integration (ULSI) structures. When chip size becomes smaller, the propagation delay time in a device is reduced. However, the importance of on-chip interconnect RC (resistance capacitance) delay to chip performance, reliability, and pr

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Gao, Yan, Xiu Liu, Jin Jiang He, Hao Zeng, Xiao Dong Xiong, and Yue Wang. "Replacement of High-Purity Copper Target by High-Purity Copper Alloy Target in Very Large Scale Integrated Circuit." Materials Science Forum 848 (March 2016): 430–34. http://dx.doi.org/10.4028/www.scientific.net/msf.848.430.

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With the development of semiconductor technology, the size of complementary metal oxide semiconductor (CMOS) devices has been scaled down to nanoscale dimensions. The technology of copper interconnection is the mainstream technology, so the request of the copper target is more and more rigor. This article analyzes the impact factors on the copper alloy target capability, including oxidation and strength. The aim of this investigation is to set up a bridge between the vendors of copper targets and the foundries of integrated circuit (IC) chip, and the base for the next generation copper targets

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Cherman, Vladimir O., Nga P. Pham, John Slabbekoorn, Alessandro Faes, Benno Margesin, and Harrie A. C. Tilmans. "Performance and Perspectives of Zero-Level MEMS Chip Packages with Vertical Interconnects." Journal of Microelectronics and Electronic Packaging 11, no. 3 (2014): 87–93. http://dx.doi.org/10.4071/imaps.418.

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This paper presents the performance of a MEMS zero-level chip cap package implemented with through-the-cap vertical interconnects. The interconnect as well as the hermetic bond and sealing are established using flip-chip thermo-compression bonding by creating a copper-tin to gold metallic (solder) joint. The hermeticity of the packages is assessed via electrical measurements of encapsulated MEMS resonators and the RF performance of 3D interconnects is evaluated via microwave measurements of integrated coplanar waveguides. Design guidelines imposed by concurrent requirements of the flip-chip as

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Lahbib, Insaf, Sidina Wane, Aziz Doukkali, et al. "Reliability analysis of BiCMOS SiGe:C technology under aggressive conditions for emerging RF and mm-wave applications: proposal of reliability-aware circuit design methodology." International Journal of Microwave and Wireless Technologies 10, no. 5-6 (2018): 690–99. http://dx.doi.org/10.1017/s1759078718000624.

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AbstractIn this contribution, the impact of extreme environmental conditions in terms of energy-level radiation of protons on silicon–germanium (SiGe)-integrated circuits is experimentally studied. Canonical representative structures including linear (passive interconnects/antennas) and non-linear (low-noise amplifiers) are used as carriers for assessing the impact of aggressive stress conditions on their performances. Perspectives for holistic modeling and characterization approaches accounting for various interaction mechanisms (substrate resistivity variations, couplings/interferences, drif

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Gnidzinska, K., G. De Mey, and A. Napieralski. "Heat dissipation and temperature distribution in long interconnect lines." Bulletin of the Polish Academy of Sciences: Technical Sciences 58, no. 1 (2010): 119–24. http://dx.doi.org/10.2478/v10175-010-0012-8.

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Heat dissipation and temperature distribution in long interconnect linesThermal and time delay aspects of long interconnect lines have been investigated. To design a modern integrated circuit we need to focus on very long global interconnects in order to achieve the desired frequency and signal synchronization. The long interconnection lines introduce significant time delays and heat generation in the driver transistors. Introducing buffers helps to spread the heat production more homogenously along the line but consumes extra power and chip area. To ensure the functionality of the circuit, it

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Ofek Almog, Rakefet, Hadar Ben-Yoav, Yelena Sverdlov, Tsvi Shmilovich, Slava Krylov, and Yosi Shacham-Diamand. "Integrated Polypyrrole Flexible Conductors for Biochips and MEMS Applications." Journal of Atomic, Molecular, and Optical Physics 2012 (August 9, 2012): 1–5. http://dx.doi.org/10.1155/2012/850482.

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Integrated polypyrrole, a conductive polymer, interconnects on polymeric substrates were microfabricated for flexible sensors and actuators applications. It allows manufacturing of moving polymeric microcomponents suitable, for example, for micro-optical-electromechanical (MOEMS) systems or implanted sensors. This generic technology allows producing “all polymer” components where the polymers serve as both the structural and the actuating materials. In this paper we present two possible novel architectures that integrate polypyrrole conductors with other structural polymers: (a) polypyrrole em

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Garner, C. Michael. "Lithography for enabling advances in integrated circuits and devices." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 370, no. 1973 (2012): 4015–41. http://dx.doi.org/10.1098/rsta.2011.0052.

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Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and th

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Nolden, Ramona, Kerstin Zöll, and Anne Schwarz-Pfeiffer. "Development of Flexible and Functional Sequins Using Subtractive Technology and 3D Printing for Embroidered Wearable Textile Applications." Materials 14, no. 10 (2021): 2633. http://dx.doi.org/10.3390/ma14102633.

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Embroidery is often the preferred technology when rigid circuit boards need to be connected to sensors and electrodes by data transmission lines and integrated into textiles. Moreover, conventional circuit boards, like Lilypad Arduino, commonly lack softness and flexibility. One approach to overcome this drawback can be flexible sequins as a substrate carrier for circuit boards. In this paper, such an approach of the development of flexible and functional sequins and circuit boards for wearable textile applications using subtractive and additive technology is demonstrated. Applying these techn

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Bhattacharya, Sandip, Debaprasad Das, and Hafizur Rahaman. "Analysis of Simultaneous Switching Noise and IR-Drop in Side-Contact Multilayer Graphene Nanoribbon Power Distribution Network." Journal of Circuits, Systems and Computers 27, no. 01 (2017): 1850001. http://dx.doi.org/10.1142/s0218126618500019.

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The work in this paper presents the analyses of temperature-dependent simultaneous switching noise (SSN) and IR-Drop in multilayer graphene nanoribbon (MLGNR) power interconnects for 16[Formula: see text]nm ITRS technology node. A [Formula: see text] standard cell-based integrated circuit is designed to analyze the SSN and IR-Drop using the proposed temperature-dependent model of MLGNR and Cu interconnect for 10[Formula: see text][Formula: see text]m interconnect length at temperatures (233[Formula: see text]K, 300[Formula: see text]K and 378[Formula: see text]K). Our analysis shows that MLGNR

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B, Srinath, P. Aruna priya, and Chirag Kasliwal. "Analysis of a Multiple Supply Voltage Floorplan Considering Voltage Drop and Electron Migration Risk." International Journal of Engineering & Technology 7, no. 2.24 (2018): 496. http://dx.doi.org/10.14419/ijet.v7i2.24.12145.

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In Contemporary Integrated Circuits (IC), the Voltage drop in the power rails and Electron migration risk (EM) due to high current densities are the most important factors degrading the reliability of the chip. The effect of these factors leads to an imbalance in the flow of charge carriers and voids in interconnects. This paper resolves the above issues, through analyzing and predetermining it in a Multiple Supply Voltage (MSV) design during the floorplanning stage. Simulations were carried out in Cadence digital Encounter system with 180nm technology for the circuit net list of 8 point FFT (

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CHAN, PHILIP C. "DESIGN AUTOMATION FOR MULTICHIP MODULE — ISSUES AND STATUS." International Journal of High Speed Electronics and Systems 02, no. 04 (1991): 263–85. http://dx.doi.org/10.1142/s0129156491000132.

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In this paper we will review the current state of commercial electronic design automation (EDA) tools for the design of multichip modules. MCM can be classified in terms of its substrate technology. The choice of substrate technology has important implications for the selection of design automation tools. A PCB EDA system seems more appropriate for MCMs with stacked via substrate which closely resembles the through-hole printed circuit board (PCB). A chip layout system may be more appropriate for MCMs with low-cost thin-film silicon substrate which typically uses staircase vias. The cofired ce

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Ghannam, Ayad, Alessandro Magnani, David Bourrier, and Thierry Parra. "Wafer Level 3D System Integration using a Novel 3D-RDL Technology." International Symposium on Microelectronics 2015, no. 1 (2015): 000092–97. http://dx.doi.org/10.4071/isom-2015-tp36.

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A new wafer-level 3D system integration process that relies on a novel multi-level 3D redistribution layer technology (3D-RDL) to interconnect chips together as well as to the substrate was developed. The 3D-RDL technology is based on a single electroplating step that allows routing high density, auto-adaptive vertical copper interconnects (20 μm Line/Space “L/S”) at the edge of known-good dies as well as redistribution layer on top of the die and the substrate. Furthermore, this technology enables 3D interconnection of stacked dies using a single 3D-RDL layer. Additionally, high performance 3

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Habu, Tomoyuki, Shinichi Endo, and Shintaro Yabu. "Result of high accelerated stress test of organic substrates made by integrated dry process." International Symposium on Microelectronics 2018, no. 1 (2018): 000153–60. http://dx.doi.org/10.4071/2380-4505-2018.1.000153.

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Abstract The uses of the semiconductor increase by the development of Internet of Things. Miniaturization of the semiconductor wiring to bring speedup, electric power saving advances, and various technologies are developed. The new technology that applied a semiconductor production technology is waited eagerly for the production of the printed circuit board and semiconductor packaging. We presented new dry process “Integrated dry process” using Photodesmear technology and sputter seed process in IMAPS2016 Pasadena. After the micro via formation with the laser, the smear is effective to remove

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Saris, Nur Najahatul Huda, Osamu Mikami, Azura Hamzah, Sumiaty Ambran, and Chiemi Fujikawa. "A V-Shape Optical Pin Interface for Board Level Optical Interconnect." Photonics Letters of Poland 10, no. 1 (2018): 20. http://dx.doi.org/10.4302/plp.v10i1.786.

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This paper introduces a new interface of an optical pin for Printed Circuit Boards (PCBs), the V-shape cut type which is an innovation from the 90-degree cut type optical pin. The effectiveness is determined by optical characteristics through OptiCAD and by experiment. The simulation used a model of ray tracing analysis which is a one to two (split) connection function model. For the experiment, a Polymer Optical Fibre (POF) V-shape optical pin has been fabricated. It was found that the V-shaped optical pin has a multi-branched function and is applicable to optical interconnection. Full Text:

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Hernandez, George A., Daniel Martinez, Stephen Patenaude, Charles Ellis, Michael Palmer, and Michael Hamilton. "Through Si Vias Using Liquid Metal Conductors for Re-workable 3D Electronics." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (2013): 001343–57. http://dx.doi.org/10.4071/2013dpc-wp13.

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This paper describes the design and fabrication of liquid metal interconnects (vias) for 2.5D and 3D integration. The liquid metal is gallium indium eutectic with a melting temperature of approximately 15.7°C that is introduced into via openings of a silicon interposer. This liquid interconnect technology can be integrated with existing interposer technologies, such as capacitors and traditional (solid metal) through-silicon vias (TSVs). In addition, liquid metal interconnects can better accommodate thermal stresses and provide re-workability in case of chip failure. Our research efforts are f

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Sterken, T., M. Op de Beeck, F. Vermeiren та ін. "High Yield Embedding of 30μm Thin Chips in a Flexible PCB using a Photopatternable Polyimide based Ultra-Thin Chip Package (UTCP)". International Symposium on Microelectronics 2012, № 1 (2012): 000940–45. http://dx.doi.org/10.4071/isom-2012-wp52.

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A thin chip package for off-the-shelf ICs is developed which enables the embedding of these chips into a flexible circuit board. The package consists of a copper fan-out on a polyimide substrate, in which the thinned IC (30μm) is embedded. These packages are subsequently integrated in a standard flexible circuit board (FCB). A microcontroller and a proprietary DSP processor are embedded using this technology. The yield of the Ultra-Thin Chip package (UTCP) was measured before embedding in the circuit board, and reaches up to 87% for the packaged microcontrollers (MSP430 family, known-good dies

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Pethuraja, Gopal G., Roger E. Welser, John W. Zeller, et al. "Advanced Flexible CIGS Solar Cells Enhanced by Broadband Nanostructured Antireflection Coatings." MRS Proceedings 1771 (2015): 145–50. http://dx.doi.org/10.1557/opl.2015.589.

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ABSTRACTFlexible copper indium gallium diselenide (CIGS) solar cells on lightweight substrates can deliver high specific powers. Flexible lightweight CIGS solar cells are also primary candidates for building-integrated panels. In all applications, CIGS cells can greatly benefit from the application of broadband and wide-angle AR coating technology. The AR coatings can significantly improve the transmittance of light over the entire CIGS absorption band spectrum. Increased short-circuit current has been observed after integrating AR coated films onto baseline solar panels. NREL’s System Advisor

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Wickham, Martin, Kate Clayton, Ana Robador, and Christine Thorogood. "Organic Hybrids for Circuit Assemblies – Initial environmental testing of a low cost alternative to ceramic substrate based assemblies." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2018, HiTEC (2018): 000022–27. http://dx.doi.org/10.4071/2380-4491-2018-hiten-000022.

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Abstract There are an increasing number of electronics applications in aerospace, automotive, shale/gas and power management, which are required to operate at or above 200 °C. Organic matrix reinforced substrates such as polyimide, have maximum operating temperatures in the region of 175 °C. Reliable operation of electronics at temperatures higher than this requires a combination of performance improvements in components, interconnects and substrates. Ceramic based substrate options are based on alumina substrates with printed inks fired at ~ 600 °C and can be costly, heavy and prone to mechan

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Kumar Sharma, Devendra, Brajesh Kumar Kaushik, and R. K. Sharma. "Impact of driver size and interwire parasitics on crosstalk noise and delay." Journal of Engineering, Design and Technology 12, no. 4 (2014): 475–90. http://dx.doi.org/10.1108/jedt-08-2012-0036.

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Purpose – The purpose of this research paper is to analyze the combined effects of driver size and coupling parasitics on crosstalk noise and delay for static and dynamically switching victim line. Furthermore, this paper shows the effect of inductance on delay and qualitatively optimizes its value to obtain minimum delay. Design/methodology/approach – The interwire parasitics are the primary sources of crosstalk or coupled noise that may lead to critical delays/logic malfunctions. This paper is based on simulating a pair of distributed resistance inductance capacitance (RLC) interconnects cou

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Cho, Sangbeom, Venky Sundaram, Rao Tummala, and Yogendra Joshi. "Multi-scale thermal modeling of glass interposer for mobile electronics application." International Journal of Numerical Methods for Heat & Fluid Flow 26, no. 3/4 (2016): 1157–71. http://dx.doi.org/10.1108/hff-09-2015-0378.

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Purpose – The functionality of personal mobile electronics continues to increase, in turn driving the demand for higher logic-to-memory bandwidth. However, the number of inputs/outputs supported by the current packaging technology is limited by the smallest achievable electrical line spacing, and the associated noise performance. Also, a growing trend in mobile systems is for the memory chips to be stacked to address the growing demand for memory bandwidth, which in turn gives rise to heat removal challenges. The glass interposer substrate is a promising packaging technology to address these e

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Ramm, Peter, Armin Klumpp, Alan Mathewson, Kafil M. Razeeb, and Reinhard Pufall. "The European 3D Heterogeneous Integration Platform (e-BRAINS) - a Particular Focus on Reliability and Low-Temperature Processes for 3D Integrated Sensor Systems." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, DPC (2015): 001847–84. http://dx.doi.org/10.4071/2015dpc-tha11.

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The European 3D heterogeneous integration platform has been established by the consortium of the Integrated Project e-BRAINS [1], where technologies of the following relevant main categories of 3D integration are provided to enable future applications of smart sensor systems:3D System-on-Chip Integration - 3D-SOC: TSV technology for stacking of thinned devices or large IC blocks (global level),3D Wafer-Level-Packaging - 3D-WLP: embedding technology with through-polymer vias (TPV) for stacking of thinned ICs on wafer-level (no TSV), and3D System-in-Package - 3D-SIP: 3D stacking of packaged devi

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Levy, Andrew, Hans Manhaeve, and Ed McBain. "An Innovative 2.5D IC Interconnection Reliability System." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (2013): 002056–89. http://dx.doi.org/10.4071/2013dpc-tha34.

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In this paper we present a new methodology that addresses the quality and reliability problems of applications that deploy “2.5D” packaging technology for integrated circuits (ICs). This technology employs through-silicon vias (TSVs), enabling greatly increased circuit density, performance, and functionality for a given volume. The 2.5D ICs require the use of an interposer to route signals between the chips and the package substrate. While this packaging solution has some distinct advantages over other packaging/mounting technologies, there are disadvantages as well. Qualifying and testing suc

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Chien, Chun-Hsien, Yu-Hua Chen, Yu-Chung Hsieh, et al. "Glass 3D Solenoid Inductors IPD Substrate Manufacturing Assembly and Characterization." International Symposium on Microelectronics 2016, no. 1 (2016): 000013–17. http://dx.doi.org/10.4071/isom-2016-tp13.

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Abstract This paper aims to discuss the integration of 3D solenoid inductors fabricated by using a glass core substrate with through glass via (TGV) technology. Glass materials were chosen for the substrate core based on the natural properties of low insertion loss, adjustable CTE, low surface roughness and high insulation for RF application. The TGV formation and semi-additive conformal copper electroplating were the key processes of the glass core substrate manufacturing. The key benefits of these evaluations are a competitive cost structure for a 508mm × 508mm glass panel IC (integrated cir

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