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Sahoo, Manodipan, and Hafizur Rahaman. "Analysis of Crosstalk-Induced Effects in Multilayer Graphene Nanoribbon Interconnects." Journal of Circuits, Systems and Computers 26, no. 06 (March 5, 2017): 1750102. http://dx.doi.org/10.1142/s021812661750102x.
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Crosstalk effects in multilayer graphene nanoribbon (GNR) interconnects for the future nanoscale integrated circuits are investigated with the help of ABCD parameter matrix approach for intermediate- and global-level interconnects at 11[Formula: see text]nm and 8[Formula: see text]nm technology nodes. The worst-case crosstalk-induced delay and peak crosstalk noise voltages are derived for both neutral and doped zigzag GNR interconnects and compared to those of conventional copper interconnects. The worst-case crosstalk delays for perfectly specular, doped multilayer GNR interconnects are less than 4% of that of copper interconnects for 1[Formula: see text]mm long intermediate interconnects and less than 7% of that of copper interconnects for 5[Formula: see text]mm long global interconnects at 8[Formula: see text]nm node. As far as the worst-case peak crosstalk noise voltage is concerned, neutral GNR interconnects are slightly better performing than their doped counterparts. But from the perspective of overall noise contribution, doped GNR interconnects outperform neutral ones for all the cases. Finally, our analysis shows that from the signal integrity perspective, perfectly specular, doped multilayer zigzag GNR interconnects are a suitable alternative to copper interconnects for the future-generation integrated circuit technology.
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Plovie, Bart, Sheila Dunphy, Kristof Dhaenens, Steven Van Put, Bjorn Vandecasteele, Frederick Bossuyt, and Jan Vanfleteren. "2.5D Smart Objects Using Thermoplastic Stretchable Interconnects." International Symposium on Microelectronics 2015, no. 1 (October 1, 2015): 000868–73. http://dx.doi.org/10.4071/isom-2015-thp51.
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This contribution describes the technology used to produce thermoplastically deformable electronics, based on flexible circuit board technology, to achieve low-cost 2.5D free-form rigid smart objects. These one-time deformable circuits employ a modified version of the previously developed meander-based “polymer-last” technology for dynamically stretchable elastic circuits. This is readily achieved by substituting the dynamically stretchable elastomeric materials (e.g. silicone) with thermoplastic polymers (e.g. polycarbonate). Afterwards the circuit is given its final form using widely available thermoforming techniques, such as vacuum forming, where the material is heated above its glass transition temperature and drawn against a forming tool by a strong vacuum. After cooling down the thermoplastic retains its shape without inducing large internal stresses. The presented method allows for the production of these circuits on a flat substrate, using standard printed circuit board production equipment, with deformation only taking place afterwards; eliminating the need for large investments and reducing the cost of fabrication. Potential advantages over competitive methods are reductions in weight and material usage, decrease of mechanical complexity; lower tooling cost, increased resilience, and a higher degree of manufacturer independence due to adhering to standard industrial practices. This is realized by starting production from a flexible circuit board, manufactured by an industrial supplier using polyimide flexible copper clad laminate, which is attached to a temporary reusable carrier board through means of a silicone based high-temperature pressure sensitive adhesive. Through selective laser structuring the meander and island outlines of the flexible circuit are defined, without causing damage to the carrier board or pressure sensitive adhesive. After removing the residual material the circuit is assembled using high-temperature lead-free solder, made possible by the temporary carrier keeping the circuit in place at these elevated temperatures. The circuit is then transferred into a thermoplastic laminate, which is deformed into its final shape. After demonstrating the need for stretchable electronics for this application, this contribution describes the method used to design, fabricate, and test the first one-time deformable circuits manufactured using the presented technology. Using the initial set of observations a series of preliminary design rules is established, both for the circuit and choice of materials. The feasibility of this manufacturing method was then demonstrated through a small scale production run using lab scale equipment, where a large quantity of high power LEDs was integrated into a one-time deformable device made out of polystyrene and thermoplastic polyurethane. These devices were then tested by exposing them to real world conditions for several days.
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Karthikeyan, A., and P. S. Mallick. "Optimization Techniques for CNT Based VLSI Interconnects — A Review." Journal of Circuits, Systems and Computers 26, no. 03 (November 21, 2016): 1730002. http://dx.doi.org/10.1142/s0218126617300021.
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Interconnects plays an important role in integrated circuits. Copper is used as an interconnect material, but beyond 22[Formula: see text]nm technology node it faces many problems due to grain boundary scattering, and therefore carbon nanotubes are the most promising future interconnect materials. Various techniques and approaches such as driver sizing, repeater sizing, repeater insertion, wire sizing, wire spacing, shielding, boos table repeater were used by various researchers. Many of these techniques can be utilized for future CNT based VLSI interconnects as well. This paper presents a detailed discussion on the techniques and approaches of past, present and future relevant for interconnects of VLSI circuits.
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Kureshi, Abdul Kadir, and Mohd Hasan. "Analysis of CNT Bundle and Its Comparison with Copper Interconnect for CMOS and CNFET Drivers." Journal of Nanomaterials 2009 (2009): 1–6. http://dx.doi.org/10.1155/2009/486979.
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In nanoscale regime as the CMOS process technology continues to scale, the standard copper (Cu) interconnect will become a major hurdle for onchip communication due to high resistivity and electromigration. This paper presents the comprehensive evaluation of mixed CNT bundle interconnects and investigates their prospects as a low power high-speed interconnect for future nanoscale-integrated circuits. The performance of mixed CNT bundle interconnect is examined with carbon nanotube field effect transistor (CNFET) as a driver and compared with the traditional interconnect, that is, CMOS driver on Cu interconnect. All HSPICE simulations are carried out at operating frequency of 1 GHz and it is found that mixed CNT bundle interconnects with CNFET as the driver can potentially provide a substantial delay reduction over traditional interconnects implemented at 32 nm process technology. Similarly, the CNFET driver with mixed CNT bundle as interconnect is more energy efficient than the traditional interconnect at all supply voltages (VDD) from 0.9 V to 0.3 V.
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Sahoo, Manodipan, and Hafizur Rahaman. "Modeling of Crosstalk Induced Effects in Copper-Based Nanointerconnects: An ABCD Parameter Matrix-Based Approach." Journal of Circuits, Systems and Computers 24, no. 02 (November 27, 2014): 1540007. http://dx.doi.org/10.1142/s0218126615400071.
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Aggressive miniaturization has led to severe performance and signal integrity issues in copper-based interconnects in the nanometric regime. As a consequence, development of a proper analytical model for such interconnects is extremely important. In this work, an ABCD parameter matrix-based model is presented for fast and accurate estimation of crosstalk delay and noise for identically coupled copper-based nanointerconnect systems. Using the proposed model, the crosstalk delay and noise are estimated in copper based nanointerconnects for intermediate and global interconnects at the future integrated circuit technology nodes of 21 and 15 nm, respectively. Proposed model has been compared with SPICE and it is found that this model is almost 100% accurate as SPICE with respect to both the crosstalk delay as well as noise. Moreover, this model is as much as ~ 63 and ~ 155 times faster, respectively. From the crosstalk delay and noise analysis of unrepeated interconnects, it is observed that both delay and noise contribution will increase in scaled technology nodes. The same trend is observed also for the repeated interconnects. Also more number of repeaters and higher repeater sizes will be needed for delay minimization as we scale deeper. So as far as crosstalk induced effects are concerned, the copper interconnects will face a huge challenge to overcome in nanometer technology nodes.
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Rebelli, Shashank, and Bheema Rao Nistala. "A novel MRTD model for signal integrity analysis of resistive driven coupled copper interconnects." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 37, no. 1 (January 2, 2018): 189–207. http://dx.doi.org/10.1108/compel-12-2016-0521.
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Purpose This paper aims to model the coupled on-chip Copper (Cu) interconnects by using the multiresolution time-domain (MRTD) method. Design/methodology/approach The proposed model is a wavelet-based numerical method for analyzing signal integrity and propagation delay of coupled on-chip interconnects. Moreover, the dependency of crosstalk noise and delay on coupling parasitics (L12, C12) are analyzed. Findings The proposed MRTD method captures the behaviour of propagation delay and peak crosstalk noise on victim line against coupling parasitics, which is in close agreement with that of H simulation program with integrated circuit emphasis (HSPICE). The average error for the proposed model is less than 1 per cent with respect to HSPICE for the estimation of peak crosstalk noise voltage. Practical implications Simulations are performed using HSPICE and compared with those performed using the proposed MRTD method for global interconnect length with 130-nm technology, where the computations of the proposed model are carried out using Matlab. Originality/value The MRTD method with its unique features is tailored for modelling interconnects. To build further credence to this and its profound existence in the latest state-of-art works, simulations of crosstalk noise and propagation delay, for coupled Cu interconnect lines, using MRTD and finite-difference time-domain (FDTD) are executed. The results illustrated the dominance of MRTD method over FDTD in terms of accuracy.
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Sharma, Himanshu, and Karmjit Singh Sandha. "Impact of Intercalation Doping on the Conductivity of Multi-Layer Graphene Nanoribbon (MLGNR) in On-Chip Interconnects." Journal of Circuits, Systems and Computers 29, no. 12 (February 5, 2020): 2050185. http://dx.doi.org/10.1142/s0218126620501856.
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Graphene nanoribbons are considered potentially suitable and have exhibited excellent results in on-chip interconnects. In order to evaluate the different circuit impedance parameters of multi-layer graphene nanoribbons (MLGNRs), an electrical equivalent single conductor (ESC) along with an analytical model is proposed. On the basis of an electrical model, the impact of intercalation doping on the performance of MLGNRs at 32, 22, and 16[Formula: see text]nm technology nodes is discussed in this paper. Moreover, it is also discussed that the increase in intercalation doping increases the Fermi energy of the layers of the MLGNR, which increases its overall conductivity. The fact that the variation in the Fermi energy will have a considerable impact on the parasitic parameters of the MLGNR interconnect at three different technology nodes (32, 22, and 16[Formula: see text]nm) for variable global lengths (500–2000[Formula: see text][Formula: see text]m) is also analyzed. To estimate and compare the performance in terms of delay and power delay product (PDP) of MLGNRs, the simulation program with integrated circuit emphasis (SPICE) simulation tool is used. The results also show that the increase in the Fermi energy improves the performance of MLGNRs in terms of delay and PDP at three different technology nodes. Furthermore, a comparative analysis of all three technology nodes is performed with the copper interconnect, and it is revealed that the MLGNR interconnect is considered to be a prominent material for the next-generation on-chip very-large-scale integration interconnects.
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Khursheed, Afreen, and Kavita Khare. "Designing dual-chirality and multi-Vt repeaters for performance optimization of 32 nm interconnects." Circuit World 46, no. 2 (January 13, 2020): 71–83. http://dx.doi.org/10.1108/cw-06-2019-0060.
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Purpose This paper is an unprecedented effort to resolve the performance issue of very large scale integrated circuits (VLSI) interconnects encountered because of the scaling of device dimensions. Repeater interpolation technique is an effective approach for enhancing speed of interconnect network. Proposed buffers as repeater are modeled by using dual chirality multi-Vt technology to reduce delay besides mitigating average power consumption. Interconnects modeled with carbon nanotube (CNT) technology are compared with copper interconnect for various lengths. Buffer circuits are designed with both CNT and metal oxide semiconductor technology for comparison by using various combination of (CMOSFET repeater-Cu interconnect) and (CNTFET repeater-CNT interconnect). Compared to conventional buffer, ProposedBuffer1 saves dynamic power by 84.86%, leakage power by 88% and offers reduction in delay by 72%. ProposedBuffer2 brings about dynamic power saving of 99.94%, leakage power saving of 93%, but causes delay penalty. Simulation using Stanford SPICE model for CNT and silicon-field effective transistor berkeley short-channel IGFET Model4 (BSIM4) predictive technology model (PTM) for MOS is done in H simulation program with integrated circuit emphasis for 32 nm. Design/methodology/approach Usually, the dynamic power consumption dominates the total power, while the leakage power has a negligible effect. But with the scaling of device technology, leakage power has become one of the important factors of consideration in low power design techniques. Various strategies are explored to suppress the leakage power in standby mode. The adoption of a multi-threshold design strategy is an effective approach to improve the performance of buffer circuits without compromising on the delay and area overhead. Unlike MOS technology, to implement multi-Vt transistors in case of CNT technology is quite easy. It can be achieved by varying diameter of carbon nanotubes using chirality control. Findings An unprecedented approach is taken for optimizing the delay and power dissipation and hence drastically reducing energy consumption by keeping proper harmony between wire technology and repeater-buffer technology. This paper proposes two novel ultra-low power buffers (PB1 and PB2) as repeaters for high-speed interconnect applications in portable devices. PB1 buffer implemented with high-speed CML technique nested with multi-threshold (Vt) technology sleep transistor so as to improve the speed along with a reduction in standby power consumption. PB2 is judicially implemented by inserting separable sized, dual chirality P type carbon nanotube field effective transistors. The HSpice simulation results justify the correctness of schemes. Originality/value Result analysis points out that compared to conventional Cu interconnect, the CNT interconnects paired with Proposed CNTFET buffer designs are more energy efficient. PB1 saves dynamic power by 84.86%, reduces propagation delay by 72% and leakage power consumption by 88%. PB2 brings about dynamic power saving of 99.4%, leakage power saving of 93%, with improvement in speed by 52%. This is mainly because of the fact that CNT interconnect offers low resistance and CNTFET drivers have high mobility and ballistic mode of operation.
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Neirynck, J. M., R. J. Gutmann, and S. P. Murarka. "Copper/Benzocyclobutene Interconnects for Sub‐100 nm Integrated Circuit Technology: Elimination of High‐Resistivity Metallic Liners and High‐Dielectric Constant Polish Stops." Journal of The Electrochemical Society 146, no. 4 (April 1, 1999): 1602–7. http://dx.doi.org/10.1149/1.1391812.
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Wang, Juan, Ru Wang, and Guo Dong Chen. "Evaluation of the Stability on the New Alkaline Copper Bulk Slurry." Key Engineering Materials 645-646 (May 2015): 352–55. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.352.
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At present, the chemical mechanical polishing is the only means for global planarization of an integrated circuit. After the node of the integrated circuit processing comes into 45nm, the diameter of wafer is 300mm, and the copper interconnect layer is above the 10 layer. In the same time the new low dielectric constant materials are used to the integrated circuit processing. That requires the property of the slurry used in the chemical mechanical polishing stricter. So the domestic and international companies carry out a series research works. Based on investigation and research for many years, the new alkaline copper rough slurry has been developed by the teachers and students in the Hebei University of Technology. The slurry has advantages as disadvantages. The composition of cost-effective slurry is simple and the effect of chemical mechanical polishing is good. But its stability is poor. In order to improve the stability, the compositions of the slurry need to adjust.The new alkaline copper rough slurry composed by abrasive, surface, chelating agent, oxidizing agent and deionized water. Experiments investigate the influence rule of copper polishing rate by the concentration of abrasive, the content of surface, the content of oxidizing agent and the content of chelating agent. The conclusion is arrived. When the concentration of abrasive is 4%, the content of surfactant is 10ml/l, the content of chelating agent is 10ml/l and the content of oxidizing agent is 5ml/l, the copper polishing rate keep 5000 Å /min.
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Lamy, Yann, Haykel Ben Jamaa, Hughes Metras, Stéphane Bernabé, Sylvie Menezo, and Laurent Fulbert. "Heterogeneous Integration of Photonic Integrated Circuits Using 3D Assembly Techniques: Silicon Technology and Packaging." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, DPC (January 1, 2014): 002057–86. http://dx.doi.org/10.4071/2014dpc-tha31.
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The large internet companies' investments indicate an ongoing increase of data-based business volume through the next decades with the rise of the internet of things and the continuous growth of communication and data facilities. The two-figure yearly growth rate of exchanged data volume within data centers is challenging the actual short distance communication paradigms. With datacenter architectures getting larger and “flatter”, the availability of high bandwidth, low power and low cost optical links ranging from less than 1 meter to 1 kilometer is a key issue. It is therefore expected that today's 10 Gb/s transceiver data rate soon increase to 28Gb/s, 40 Gb/s and beyond. For such a channel bandwidth, the copper-based wires are no longer suitable in terms of cost, power and bandwidth density. Optical interconnects are expected to replace copper for short distances below 500 m and down to 1 m within servers and between servers of the same data center. They exhibit much higher scalability and flexibility in terms of bandwidth, reach and lower energy consumption down to 1 pJ/b and below. The integration of optical transceivers close to the computational logic is therefore becoming more and more attractive. The enabling technology for optical interconnect is silicon photonics which is maturing and leveraging the well-established knowledge coming from silicon technology. We today have a complete set of silicon photonics technology modules that cover passive components including multiplexers/demultiplexers, coupling functions, photodetectors, modulators and integrated laser sources. Given the constraints coming from the supply chain, we consider a heterogeneous integration of the photonics (PIC) and the electrical integrated circuits (EIC) within a single package, differentiating from a co-integration of both of them on a single die demonstrated in the past, which is not a viable nor scalable option from the economical point of view. Thereby we leverage our expertise in the 3D integration field, and we use a full set of mature technology modules including through-silicon vias (TSV), wafer thinning and micro-bumping. These modules have only been used in the past within electrical circuits, but their implantation in photonics chips has no showstoppers. The 3D integration enables a stacking of the electrical drivers in the EIC die on top of the photodiodes and modulators in the PIC die. The small micro-bump size reduces the parasitic capacitances and enables an optimized electro-optical co-design. The TSV enable the connection of the stack with the rest of the package and to the second-level interconnect with low inductive losses, thus boosting the system performance. The advanced 3D packaging technique also enables the alignment and attachment of the optical fibers using silicon micro-ferrules. Today's active alignment techniques for optical coupling are time-consuming and expensive, and not compatible with usual micro-electronics techniques. The ongoing development of silicon micro-ferrules with mechanical micro-bumps enables a compatible assembly of the optical plugs with the remaining system and a quick assembly process with standard pick-and-place equipment. The paper will introduce today's system demand in the data base market and its translation into technology requirements. It will then survey our silicon photonics technology modules and actual demonstrations. We will then introduce the packaging constraints and the impact of 3D integration on the system assembly. Finally, we will present our advances in terms of packaging of optical micro-connectors.
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Merschky, Michael, Fabian Michalik, Martin Thoms, Robin Taylor, Diego Reinoso-Cocina, Stephan Hotz, and Patrick Brooks. "Using a Metal Oxide Adhesion Layer and Wet Chemical Cu Metallization for Fine Line Pattern Formation on Glass." International Symposium on Microelectronics 2017, no. 1 (October 1, 2017): 000458–63. http://dx.doi.org/10.4071/isom-2017-wp51_084.
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Abstract With the trends towards miniaturization and heterogeneous integration, both IC and advanced substrate manufacturers are striving to meet the needs of next generation platforms, to increase the density of interconnects, and generate conductors featuring finer lines and spaces. Advanced manufacturing technologies such as Semi-Additive-Processing (SAP) and Advanced Modified-Semi-Additive-Processing (amSAP) were devised, realized and implemented in order to meet these requirements. Line and space (L/S) requirements of copper conductors will be below 5/5μm for advanced substrates, with 2/2μm L/S required for chip to chip connections in the near future. Herein we report about the performance of the new developed ferric sulfate based EcoFlash™ process for SAP and amSAP application with the focus on glass as the substrate and VitroCoat as thin metal oxide adhesion promotion layer. The adhesion promotion layer (about 5–10 nm thickness) is dip-coated by a modified sol-gel process followed by sintering which creates chemical bonds to the glass. The sol-gel dip coating process offers good coating uniformity on both Though-Glass-Via (TGV) and glass surfaces under optimized coating conditions. Uniform coating can be achieved up to aspect ratios of 10:1 by using a 300μm thick glass with 30μm diameter TGV. The thin adhesive layer enables electroless and electrolytic copper plating directly onto glass substrates. Excellent adhesion of electroless plated copper seed layer on glass can be achieved by using the adhesive layer and annealing technology. The thin adhesive layer is non-conductive and can be easily removed from the area between circuit traces together with the electroless copper seed layer by etching with a ferric sulfate based process. We have successfully integrated the adhesion layer and electroless and electrolytic copper plating technologies into semi-additive process and seed layer etching capable producing L/S below 10 μm.
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Flemming, Jeb, Kyle McWethy, Tim Mezel, Luis Chenoweth, and Carrie Schmidt. "Photosensitive Glass-Ceramics for Heterogeneous Integration." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (January 1, 2019): 000880–907. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_wp1_036.
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The push for heterogeneous integration requires very unique material properties with respect to processing, material constants, and integration capabilities with other materials (such as copper, III–V, magnetics, etc.). Current common circuit board materials such as ceramics and laminates, as well as silicon substrates, suffer from a variety of limitations. For ceramics and laminates, these constraints include: (1) the inability to produce narrow line widths <100 m with narrow gaps between lines <100 m; (2) high surface roughness (on the order of 2μm RMS); (3) layer-to-layer misalignments; and (4) lack of high-quality integrated passives. For silicon, these constraints include: (1) high cost; (2) long design/production lead times; and (3) electrical properties of standard doped silicon are not suitable for millimeter-wave applications. A significant drawback of ceramics and laminates is that they cannot be 3D structured with micron-scale precision which is necessary for advanced interconnects for millimeter-wave IC packaging integration (e.g. transistor-to-board interconnects). These characteristics lead to devices with limited integration options, large footprints, and higher power consumption. To overcome the above limitations, 3D Glass Solutions (3DGS) has developed a photo-sensitive glass ceramics as a board-level system substrate. Compared to ceramics, laminates, and silicon, photo-sensitive glass ceramic materials offer higher interconnect densities, lower processing cost, better spatial resolution, as well as improved electrical properties for both RF and millimeter-wave frequencies. Photo-sensitive glass ceramics are ideal systems-level materials for heterogeneous integration programs as they overcome many of the limitations of legacy materials such as ceramics and laminates for broadband applications (DC – 100GHz). Furthermore, the advanced manufacturing ability of photo-sensitive glass ceramics enable a broad category of IP Blocks. The innovations of the 3DGS technology and research effort include:Low loss and low dispersion: photosensitive glass material has a measured loss tangent of 0.008 at GHz frequencies. Furthermore, the thick and highly-conductive metallization layers allow for low-loss transmission lines.High current and power handling: the metallization processes enable lines with a range of thicknesses (<50m) and widths (>2m), which result in both low resistive loss and high current handling. Additionally, the RF power handling is high due to the high breakdown voltage of glass (10kV/100m) and the possibility of coaxial line integration.Thermal management: high-density metal-filled via arrays generate up to 100W/mK thermal transfer in the 3DGS process and provide an additional thermal path for chips that are not mounted directly on a heterogeneous interface heat spreader.Built-in filtering: when a variety of chiplets with unknown design parameters and with signals of varying time constants are interconnected, EMI becomes a significant problem. The 3DGS approach allows for high-quality filtering, coupling and self-assessment functions to be directly integrated within the 2.5D interposer system as IPDs eliminating wire bonding and providing seamless integration with low loss.Scalability: the glass interconnect plane can be fabricated with footprints up to 40mm × 40mm with integrated air cavities for chip placement, through glass vias for I/Os and redistribution metal. In this presentation, 3DGS will present on three Heterogeneous Integration attributes: (1) design considerations, (2) integration of passive devices, and (3) millimeter wave integration. Design Considerations 3DGS is developing an IP Block library with 11 distinct categories. These categories include: (1) metal filled I/Os, (2) copper redistribution layers, (3) thermal management blocks, (4) cavities, (5) metal filled through glass structures, (6) phased array antenna, (7) conductor undercuts, (8) magnetic core devices, (9) capacitors, (10) inductors, and (11) grounding. While each of these unique IP Blocks contributes their own advantages for analog performance, they can all be integrated into a single chip. Integration of Passives Devices The foundation of the work done by 3DGS is on developing a volume manufacturing approach for high uniformity through glass vias (TGVs). All TGVs for I/O applications are 100% copper filled for low-loss, high power, electrical connections. Two major building blocks of 3DGS' Heterogeneous technology are High Quality Factor inductors and capacitors. 3DGS has developed a broad library of inductor components ranging from 0.5 – 200nH. Footprints are determined by inductance sizes but may be as small as 01005. Capacitors are built by placing two slots inside of the glass material, filling the slots with copper, and using the glass' natural Dk to form a capacitor. The benefit of these capacitors include high breakdown voltage (>1,000V), small footprint, high reliability, and Quality factors between 200–300. Inductors and capacitors can be integrated into a single monolithic RF package called an Integrated Passive Device (IPD). The benefits of the IPD include the elimination of RF losses associated with PCB Interconnects, long metal redistribution line lengths, bond pads, solder balls, and inconsistent assembly. This leads to the production of RF devices, capable of operating in the MHz – GHz frequency range with higher overall system Quality Factors, lower ripple, and lower losses. Furthermore, IPDs can be directly integrated into more complex System-in-Package (SiP) architectures. This approach has been used to build an RF ZigBee module in APEX® Glass [1]. The glass SiP module consisted of 35+ SMT components and was itself soldered to a PCB board. The full RF module was then subjected full complement of reliability tests and met the customer's stringent performance goals. Millimeter Wave Integration A major benefit of glass is the ability to produce low loss structures for millimeter wave applications. 3DGS has been designing and producing a variety of millimeter wave band pass filters with a variety of bandwidths ranging from 5–40%. These bandpass filters are compact, fully shielded and low loss (<2.0dB) with high attenuation (>50dB).
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McNally, P. J., J. Kanatharana, B. H. W. Toh, D. W. McNeill, A. N. Danilewsky, T. Tuomi, L. Knuuttila, J. Riikonen, J. Toivonen, and R. Simon. "Geometric linewidth and the impact of thermal processing on the stress regimes induced by electroless copper metallization for Si integrated circuit interconnect technology." Journal of Applied Physics 96, no. 12 (December 15, 2004): 7596–602. http://dx.doi.org/10.1063/1.1811780.
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Marsan-Loyer, C., D. Danovitch, and N. Boyer. "Addressing Flux Dip Challenges for 3-D Integrated Large Die, Ultrafine Pitch Interconnect." Journal of Microelectronics and Electronic Packaging 14, no. 1 (January 1, 2017): 32–38. http://dx.doi.org/10.4071/imaps.348081.
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The requirement for closely coupled, highly integrated circuits in the semiconductor industry has spawned alternative packaging innovations such as 2.5-D/3-D integration. The incredible potential of this alternative comes with great challenges, not the least of which is the unprecedented reduction in package interconnection pitch. Market acceptance of new fine-pitch microelectronic products is strongly dependent on the development of flawless assembly processes that align with the traditional Moore-like expectation of higher performance without cost penalty. One such process is the application of flux to the interconnect surfaces to achieve effective joining. Insufficient flux quantity or flux activity can impede the formation of solid, reliable joints, whereas excessive quantities or activity can cause solder bridging or difficulties with downstream operations such as residue cleaning or underfill reinforcement. This delicate balance, already complex for traditional chip joining, is further challenged by the geometrical and spatial reductions imposed by pitch miniaturization, especially where large die, with over 100,000 interconnects, are concerned. This article presents an overall development protocol to evolving a flux dipping operation to production-level thermocompression assembly of large die (8 × 11 × 0.780 mm) with 11,343 ultrafine pitch (62 μm) copper pillar interconnections. After reviewing the state of the art for fluxing technology and detailing the specific technical issues, we present and defend the chosen flux application approach with its corresponding parameters of interest. Physical and chemical characterization results for selected flux material candidates are reported in conjunction with an analysis of how their properties correlate to the flux dip application parameters. As part of this fundamental understanding, we investigate and report on flux dip coating behavior and how it compares to other industrial dip coating applications. Finally, the results of process assembly experiments in a production-type environment are reviewed and discussed with respect to the previous characterizations. These experiments span downstream assembly process compatibility (i.e., cleaning and underfill) as well as product reliability.
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Marsan-Loyer, C., D. Danovitch, and N. Boyer. "Addressing Flux Dip Challenges for 3D Integrated Large Die, Ultra-fine Pitch Interconnect." International Symposium on Microelectronics 2016, no. 1 (October 1, 2016): 000054–59. http://dx.doi.org/10.4071/isom-2016-tp25.
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Abstract The requirement for closely coupled, highly integrated circuits in the semiconductor industry has spawned alternative packaging innovations such as 2.5D/3D integration. The incredible potential of this alternative comes with great challenges, not the least of which is the unprecedented reduction in package interconnection pitch. Market acceptance of new fine-pitch microelectronic products is strongly dependent upon the development of flawless assembly processes that align with the traditional Moore-like expectation of higher performance without cost penalty. One such process is the application of flux to the interconnect surfaces in order to achieve effective joining. Insufficient flux quantity or flux activity can impede the formation of solid, reliable joints, while excessive quantities or activity can cause solder bridging or difficulties with downstream operations such as residue cleaning or underfill reinforcement. This delicate balance, already complex for traditional chip joining, is further challenged by the geometrical and spatial reductions imposed by pitch miniaturization, especially where large die, with over 100,000 interconnects, are concerned. This paper presents an overall development protocol to evolving a flux dipping operation to production-level thermocompression assembly of large die with ultra-fine pitch (60 μm) copper pillar interconnections. After reviewing the state of the art for fluxing technology and detailing the specific technical issues, we present and defend the chosen flux application approach with its corresponding parameters of interest. Physical and chemical characterization results for selected flux material candidates are reported in conjunction with an analysis of how their properties correlate to the flux dip application parameters. As part of this fundamental understanding, we investigate and report on flux dip coating behaviour and how it compares to other industrial dip coating applications. Finally, the results of process assembly experiments in a production-type environment are reviewed and discussed with respect to the previous characterizations. These experiments span downstream assembly process compatibility (i.e. cleaning and underfill) as well as product reliability.
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Bai, Jiang Hao, Xiao Dong Xiong, Jun Feng Luo, Guo Jin Xu, and Yong Jun Li. "Progress of Microstructure and Texture of High Purity Tantalum Sputtering Target." Materials Science Forum 1035 (June 22, 2021): 704–11. http://dx.doi.org/10.4028/www.scientific.net/msf.1035.704.
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In recent years, the IC (integrated circuit) industry has developed rapidly and the chip process technology has developed in the direction of higher density. Because of its good chemical stability, tantalum is used as a sputtering coating material for the diffusion barrier in the copper interconnect process. The uniform microstructure of the tantalum target directly affects the sputtering performance. The fabrication of high-quality thin films requires the tantalum target to have fine and uniform crystal grains and random grain orientation distribution. However, due to the characteristics of tantalum, it is easy to form a microstructure with {100} (<100>//ND) orientation on the surface and {111} (<111>//ND) orientation on the core during cold working. During the fabrication of thin films, the sputtering rate varies with the thickness of the target, which affects the sputtering stability. To provide ideas for improving the uniformity of the microstructure of the tantalum target, this article reviews the preparation processes that affect the grain orientation and size of the high-purity tantalum target, including forging methods, rolling methods, recrystallization annealing, etc., analyze the law of texture evolution of tantalum and introduction the research status of cold working and recrystallization.
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Light, Edward D., Victor Lieu, and Stephen W. Smith. "New Fabrication Techniques for Ring-Array Transducers for Real-Time 3D Intravascular Ultrasound." Ultrasonic Imaging 31, no. 4 (October 2009): 247–56. http://dx.doi.org/10.1177/016173460903100403.
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We have previously described miniature 2D array transducers integrated into a Cook Medical, Inc. vena cava filter deployment device. While functional, the fabrication technique was very labor intensive and did not lend itself well to efficient fabrication of large numbers of devices. We developed two new fabrication methods that we believe can be used to efficiently manufacture these types of devices in greater than prototype numbers. One transducer consisted of 55 elements operating near 5 MHz. The interelement spacing is 0.20 mm. It was constructed on a flat piece of copper-clad polyimide and then wrapped around an 11 French catheter of a Cook Medical, Inc. inferior vena cava (IVC) filter deployment device. We used a braided wiring technology from Tyco Electronics Corp. to connect the elements to our real-time 3D ultrasound scanner. Typical measured transducer element bandwidth was 20% centered at 4.7 MHz and the 50 Ω round trip insertion loss was −82 dB. The mean of the nearest neighbor cross talk was −37.0 dB. The second method consisted of a 46-cm long single layer flex circuit from MicroConnex that terminates in an interconnect that plugs directly into our system cable. This transducer had 70 elements at 0.157 mm interelement spacing operating at 4.8 MHz. Typical measured transducer element bandwidth was 29% and the 50 Ω round trip insertion loss was −83 dB. The mean of the nearest neighbor cross talk was −33.0 dB.
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Doppelt, Pascal, and Thomas H. Baum. "Chemical Vapor Deposition of Copper for IC Metallization: Precursor Chemistry and Molecular Structure." MRS Bulletin 19, no. 8 (August 1994): 41–48. http://dx.doi.org/10.1557/s0883769400047722.
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In the microelectronics industry, integrated circuit (IC) device performance is continually increasing while the critical feature sizes are rapidly decreasing. Since this trend is expected to continue for future generations of ICs, areal density constraints often require that circuit designs utilize multilevel structures with vertical interconnects. It was recently demonstrated that the resistivity of the metal interconnects may limit device performance in multilevel thin-film structures. Although Al metallurgy (Al/2 wt.% Cu alloy) is extensively used for IC metallization today, lower resistivity metals, such as gold, copper, and silver may be necessary for designs requiring feature sizes of 0.25 μm or less. Chemical vapor deposition (CVD) is an attractive technique for the conformal filling of submicron vertical interconnects. For CVD to be generally applicable to IC fabrication, volatile precursors with adequate stability must be designed and optimized. Lastly, IC metallization typically requires that both uniformity and conformality be achieved simultaneously in a single process step.
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Berry, G. J., J. A. Cairns, and J. Thomson. "New material for the production of fine line interconnects in integrated circuit technology." Journal of Materials Science Letters 14, no. 12 (1995): 844–46. http://dx.doi.org/10.1007/bf00639302.
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Sakata, Shuichi, Akinori Umeno, Kenji Yoshida, and Kazuhiko Hirakawa. "Critical Voltage for Atom Migration in Ballistic Copper Nanojunctions and Its Implications to Interconnect Technology for Very Large Scale Integrated Circuits." Applied Physics Express 3, no. 11 (November 5, 2010): 115201. http://dx.doi.org/10.1143/apex.3.115201.
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Tehrani, Bijan K., Ryan A. Bahr, and Manos M. Tentzeris. "Inkjet and 3D Printing Technology for Fundamental Millimeter-Wave Wireless Packaging." Journal of Microelectronics and Electronic Packaging 15, no. 3 (July 1, 2018): 101–6. http://dx.doi.org/10.4071/imaps.660476.
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Abstract This article outlines the design, processing, and implementation of inkjet and 3D printing technologies for the development of fully printed, highly integrated millimeter-wave (mm-wave) wireless packages. The materials, tools, and processes of each technology are outlined and justified for their respective purposes. Inkjet-printed 3D interconnects directly interfacing a packaging substrate with an integrated circuit (IC) die are presented using printed dielectric ramps and coplanar waveguide transmission lines exhibiting low loss (.6–.8 dB/mm at 40 GHz). Stereolithography 3D printing is presented for the encapsulation of IC dice, enabling the application-specific integration of on-package structures, including dielectric lenses and frequency selective surface–based wireless filters. Finally, inkjet and 3D printing technology are combined to present sloped mm-wave interconnects through an encapsulant, or through mold vias, achieving a slope of up to 65° and low loss (.5–.6 dB/mm at 60 GHz). The combination of these additive techniques is highlighted for the development of scalable, application-specific wireless packages.
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Zhao, Wen-Sheng, Kai Fu, Da-Wei Wang, Meng Li, Gaofeng Wang, and Wen-Yan Yin. "Mini-Review: Modeling and Performance Analysis of Nanocarbon Interconnects." Applied Sciences 9, no. 11 (May 28, 2019): 2174. http://dx.doi.org/10.3390/app9112174.
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As the interconnect delay exceeds the gate delay, the integrated circuit (IC) technology has evolved from a transistor-centric era to an interconnect-centric era. Conventional metallic interconnects face several serious challenges in aspects of performance and reliability. To address these issues, nanocarbon materials, including carbon nanotube (CNT) and graphene, have been proposed as promising candidates for interconnect applications. Considering the rapid development of nanocarbon interconnects, this paper is dedicated to providing a mini-review on our previous work and on related research in this field.
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T, Sridhar, and Dr A. S. R Murty. "Low power driver receiver topology with delay optimization for on-chip bus interconnects." International Journal of Engineering & Technology 7, no. 3.29 (August 24, 2018): 180. http://dx.doi.org/10.14419/ijet.v7i3.29.18554.
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Demands on reducing the delay and power on integrated circuits is increasing with the development of more and more low power devices. The technology scaling and the device design manage static power dissipation. However, the dynamic power dissipation and the delays associated with the bus interconnects have to be addressed separately. A low swing driver-receiver circuit for driving and receiving the signals on the global bus interconnects is presented. Also the capacitively driven interconnects are used for the signal transmission and a series coupling capacitor is introduced at an optimized location along the bus. A substantial improvement of 55% in the delay performance is obtained with the driver-receiver and capacitively driven interconnect topology combine for the data transmission bus
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Spry, David J., Philip G. Neudeck, Liang-Yu Chen, Dorothy Lukco, Carl W. Chang, Glenn M. Beheim, Michael J. Krasowski, and Norman F. Prokop. "Processing and Characterization of Thousand-Hour 500 °C Durable 4H-SiC JFET Integrated Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (January 1, 2016): 000249–56. http://dx.doi.org/10.4071/2016-hitec-249.
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Abstract This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 °C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over ~ 1-μm scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 °C operational testing. These results advance the technology foundation for realizing long-term durable 500 °C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.
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Lennon, Alison, Jack Colwell, and Kenneth P. Rodbell. "Challenges facing copper-plated metallisation for silicon photovoltaics: Insights from integrated circuit technology development." Progress in Photovoltaics: Research and Applications 27, no. 1 (August 8, 2018): 67–97. http://dx.doi.org/10.1002/pip.3062.
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Lu, Tien-Lin, Yu-An Shen, John A. Wu, and Chih Chen. "Anisotropic Grain Growth in (111) Nanotwinned Cu Films by DC Electrodeposition." Materials 13, no. 1 (December 28, 2019): 134. http://dx.doi.org/10.3390/ma13010134.
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We have reported a method of fabricating (111)-orientated nanotwinned copper (nt-Cu) by direct current electroplating. X-ray analysis was performed for the samples annealed at 200 to 350 °C for an hour. X-ray diffraction indicates that the (200) signal intensity increases while (111) decreases. Abnormal grain growth normally results from transformation of surface energy or strain energy density. The average grain size increased from 3.8 µm for the as-deposited Cu films to 65–70 µm after the annealing at 250 °C for 1 h. For comparison, no significant grain growth behavior was observed by random Cu film after annealing for an hour. This research shows the potential for its broad electric application in interconnects and three-dimensional integrated circuit (3D IC) packaging.
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Li, Jian, Tom E. Seidel, and Jim W. Mayer. "Copper-Based Metallization in ULSI Structures: Part II: Is Cu Ahead of Its Time as an On-Chip Interconnect Material?" MRS Bulletin 19, no. 8 (August 1994): 15–21. http://dx.doi.org/10.1557/s0883769400047692.
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The demand for manufacturing integrated circuit (IC) devices such as dynamic random access memory (DRAM), static random access memory (SRAM), electrically erasable and programmable read only memory (EEPROM) and logic devices with high circuit speed, high packing density and low power dissipation requires the downward scaling of feature sizes in ultralarge-scale integration (ULSI) structures. When chip size becomes smaller, the propagation delay time in a device is reduced. However, the importance of on-chip interconnect RC (resistance capacitance) delay to chip performance, reliability, and processing cost is increasing dramatically. When interconnect feature size decreases and clock frequencies increase, RC time delays become the major limitation in achieving high circuit speeds. The miniaturization of interconnect feature size also severely penalizes the overall performance of the interconnect, such as increasing interconnect resistance and interconnect current densities, which lead to reliability concerns due to electromigration. Lower resistance metal and lower dielectric materials are being considered to replace current Al and SiO2 interconnect materials. Innovative efforts in circuit design, process development, and the implementation of new materials can provide solutions. This issue of the MRS Bulletin focuses on the industrial viewpoint of copper interconnects. (A previous issue of the MRS Bulletin, June 1993, addressed university research approaches to copper metallization.) Articles in this issue, from six major semiconductor companies—IBM, Motorola, AT&T Bell Laboratories, SEMATECH/National Semiconductor, NTT, and Fujitsu—provide a real-world viewpoint of the challenges faced when replacing aluminum with copper. The articles published in both issues also contain a comprehensive list of references (more than 300) to articles, patents, and device applications related to copper metallization for ULSI applications.
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Gao, Yan, Xiu Liu, Jin Jiang He, Hao Zeng, Xiao Dong Xiong, and Yue Wang. "Replacement of High-Purity Copper Target by High-Purity Copper Alloy Target in Very Large Scale Integrated Circuit." Materials Science Forum 848 (March 2016): 430–34. http://dx.doi.org/10.4028/www.scientific.net/msf.848.430.
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With the development of semiconductor technology, the size of complementary metal oxide semiconductor (CMOS) devices has been scaled down to nanoscale dimensions. The technology of copper interconnection is the mainstream technology, so the request of the copper target is more and more rigor. This article analyzes the impact factors on the copper alloy target capability, including oxidation and strength. The aim of this investigation is to set up a bridge between the vendors of copper targets and the foundries of integrated circuit (IC) chip, and the base for the next generation copper targets.
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Cherman, Vladimir O., Nga P. Pham, John Slabbekoorn, Alessandro Faes, Benno Margesin, and Harrie A. C. Tilmans. "Performance and Perspectives of Zero-Level MEMS Chip Packages with Vertical Interconnects." Journal of Microelectronics and Electronic Packaging 11, no. 3 (July 1, 2014): 87–93. http://dx.doi.org/10.4071/imaps.418.
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This paper presents the performance of a MEMS zero-level chip cap package implemented with through-the-cap vertical interconnects. The interconnect as well as the hermetic bond and sealing are established using flip-chip thermo-compression bonding by creating a copper-tin to gold metallic (solder) joint. The hermeticity of the packages is assessed via electrical measurements of encapsulated MEMS resonators and the RF performance of 3D interconnects is evaluated via microwave measurements of integrated coplanar waveguides. Design guidelines imposed by concurrent requirements of the flip-chip assembly process and the RF performance are discussed. The developed technology for the MEMS cap uses CMOS-compatible materials and the CMOS fabrication process.
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Lahbib, Insaf, Sidina Wane, Aziz Doukkali, Dominique Lesénéchal, Thanh Vinh Dinh, Laurent Leyssenne, Rosine Coq Germanicus, et al. "Reliability analysis of BiCMOS SiGe:C technology under aggressive conditions for emerging RF and mm-wave applications: proposal of reliability-aware circuit design methodology." International Journal of Microwave and Wireless Technologies 10, no. 5-6 (June 2018): 690–99. http://dx.doi.org/10.1017/s1759078718000624.
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AbstractIn this contribution, the impact of extreme environmental conditions in terms of energy-level radiation of protons on silicon–germanium (SiGe)-integrated circuits is experimentally studied. Canonical representative structures including linear (passive interconnects/antennas) and non-linear (low-noise amplifiers) are used as carriers for assessing the impact of aggressive stress conditions on their performances. Perspectives for holistic modeling and characterization approaches accounting for various interaction mechanisms (substrate resistivity variations, couplings/interferences, drift in DC and radio frequency (RF) characteristics) for active samples are down to allow for optimal solutions in pushing SiGe technologies toward applications with harsh and radiation-intense environments (e.g. space, nuclear, military). Specific design prototypes are built for assessing mission-critical profiles for emerging RF and mm-wave applications.
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Gnidzinska, K., G. De Mey, and A. Napieralski. "Heat dissipation and temperature distribution in long interconnect lines." Bulletin of the Polish Academy of Sciences: Technical Sciences 58, no. 1 (March 1, 2010): 119–24. http://dx.doi.org/10.2478/v10175-010-0012-8.
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Heat dissipation and temperature distribution in long interconnect linesThermal and time delay aspects of long interconnect lines have been investigated. To design a modern integrated circuit we need to focus on very long global interconnects in order to achieve the desired frequency and signal synchronization. The long interconnection lines introduce significant time delays and heat generation in the driver transistors. Introducing buffers helps to spread the heat production more homogenously along the line but consumes extra power and chip area. To ensure the functionality of the circuit, it is compulsory to give priority to the time delay aspect and then the optimized solution is found by making the power dissipation as homogenous as possible and consequently the temperature distribution T (relative to ambient) as low as possible. The technology used for simulations is 65 nm node. The occurring phenomena have been described in a quantitative and qualitative way.
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Ofek Almog, Rakefet, Hadar Ben-Yoav, Yelena Sverdlov, Tsvi Shmilovich, Slava Krylov, and Yosi Shacham-Diamand. "Integrated Polypyrrole Flexible Conductors for Biochips and MEMS Applications." Journal of Atomic, Molecular, and Optical Physics 2012 (August 9, 2012): 1–5. http://dx.doi.org/10.1155/2012/850482.
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Integrated polypyrrole, a conductive polymer, interconnects on polymeric substrates were microfabricated for flexible sensors and actuators applications. It allows manufacturing of moving polymeric microcomponents suitable, for example, for micro-optical-electromechanical (MOEMS) systems or implanted sensors. This generic technology allows producing “all polymer” components where the polymers serve as both the structural and the actuating materials. In this paper we present two possible novel architectures that integrate polypyrrole conductors with other structural polymers: (a) polypyrrole embedded into flexible polydimethylsiloxane (PDMS) matrix forming high aspect ratio electrodes and (b) polypyrrole deposited on planar structures. Self-aligned polypyrrole electropolymerization was developed and demonstrated for conducting polymer lines on either gold or copper seed layers. The electropolymerization process, using cyclic voltammetry from an electrolyte containing the monomer, is described, as well as the devices’ characteristics. Finally, we discuss the effect of integrating conducting polymers with metal seed layer, thus enhancing the device durability and reliability.
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Garner, C. Michael. "Lithography for enabling advances in integrated circuits and devices." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 370, no. 1973 (August 28, 2012): 4015–41. http://dx.doi.org/10.1098/rsta.2011.0052.
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Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.
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Nolden, Ramona, Kerstin Zöll, and Anne Schwarz-Pfeiffer. "Development of Flexible and Functional Sequins Using Subtractive Technology and 3D Printing for Embroidered Wearable Textile Applications." Materials 14, no. 10 (May 18, 2021): 2633. http://dx.doi.org/10.3390/ma14102633.
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Embroidery is often the preferred technology when rigid circuit boards need to be connected to sensors and electrodes by data transmission lines and integrated into textiles. Moreover, conventional circuit boards, like Lilypad Arduino, commonly lack softness and flexibility. One approach to overcome this drawback can be flexible sequins as a substrate carrier for circuit boards. In this paper, such an approach of the development of flexible and functional sequins and circuit boards for wearable textile applications using subtractive and additive technology is demonstrated. Applying these techniques, one-sided sequins and circuit boards are produced using wax printing and etching copper-clad foils, as well as using dual 3D printing of conventional isolating and electrically conductive materials. The resulting flexible and functional sequins are equipped with surface mounted devices, applied to textiles by an automated embroidery process and contacted with a conductive embroidery thread.
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Bhattacharya, Sandip, Debaprasad Das, and Hafizur Rahaman. "Analysis of Simultaneous Switching Noise and IR-Drop in Side-Contact Multilayer Graphene Nanoribbon Power Distribution Network." Journal of Circuits, Systems and Computers 27, no. 01 (August 23, 2017): 1850001. http://dx.doi.org/10.1142/s0218126618500019.
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The work in this paper presents the analyses of temperature-dependent simultaneous switching noise (SSN) and IR-Drop in multilayer graphene nanoribbon (MLGNR) power interconnects for 16[Formula: see text]nm ITRS technology node. A [Formula: see text] standard cell-based integrated circuit is designed to analyze the SSN and IR-Drop using the proposed temperature-dependent model of MLGNR and Cu interconnect for 10[Formula: see text][Formula: see text]m interconnect length at temperatures (233[Formula: see text]K, 300[Formula: see text]K and 378[Formula: see text]K). Our analysis shows that MLGNR exhibits ([Formula: see text]–[Formula: see text]) less SSN and ([Formula: see text]–[Formula: see text]) less IR-Drop as compared with traditional Cu-based power interconnects. Our analysis also shows that the average percentage of reduction in peak SSN is 52–32% (at 233[Formula: see text]K), 53–32% (at 300[Formula: see text]K) and 52–30% (at 378[Formula: see text]K) less in MLGNR compared with traditional Cu-based power interconnect and the average percentage of reduction in peak IR-Drop in MLGNR is 54–31% (at 233[Formula: see text]K), 57–29% (at 300[Formula: see text]K) and 57–26% (at 378[Formula: see text]K) less than that of Cu-based power interconnects.
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B, Srinath, P. Aruna priya, and Chirag Kasliwal. "Analysis of a Multiple Supply Voltage Floorplan Considering Voltage Drop and Electron Migration Risk." International Journal of Engineering & Technology 7, no. 2.24 (April 25, 2018): 496. http://dx.doi.org/10.14419/ijet.v7i2.24.12145.
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In Contemporary Integrated Circuits (IC), the Voltage drop in the power rails and Electron migration risk (EM) due to high current densities are the most important factors degrading the reliability of the chip. The effect of these factors leads to an imbalance in the flow of charge carriers and voids in interconnects. This paper resolves the above issues, through analyzing and predetermining it in a Multiple Supply Voltage (MSV) design during the floorplanning stage. Simulations were carried out in Cadence digital Encounter system with 180nm technology for the circuit net list of 8 point FFT (Fast Fourier Transform) and FIR filter. Results show that floorplanning scheme is powerful in reducing 100% of voltage drop and 50% of EM risk in the chip as compared to previous works.
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CHAN, PHILIP C. "DESIGN AUTOMATION FOR MULTICHIP MODULE — ISSUES AND STATUS." International Journal of High Speed Electronics and Systems 02, no. 04 (December 1991): 263–85. http://dx.doi.org/10.1142/s0129156491000132.
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In this paper we will review the current state of commercial electronic design automation (EDA) tools for the design of multichip modules. MCM can be classified in terms of its substrate technology. The choice of substrate technology has important implications for the selection of design automation tools. A PCB EDA system seems more appropriate for MCMs with stacked via substrate which closely resembles the through-hole printed circuit board (PCB). A chip layout system may be more appropriate for MCMs with low-cost thin-film silicon substrate which typically uses staircase vias. The cofired ceramic substrate MCM which evolved from the hybrid integrated circuit technology may use the specialized hybrid EDA software packages available for the designing of hybrid integrated circuits. Historically, printed circuit board and integrated circuit design automation software evolved separately. There exists a boundary between the printed circuit board and integrated circuit design automation tools in the physical design hierarchy. This boundary can be an important limitation for the repartitioning of the physical design hierarchy within the MCM. We shall discuss in detail the impact of MCM on various aspects of EDA. In the area of physical design, we must face the traditional placement and routing problem for any high speed design. Problems such as system clock skew and tight timing requirements must be considered. As one push clock frequency higher, one also must consider discontinuities due to vias and bends besides the classical transmission line effect due to long wires. Other traditional physical design problems such as ground and power plane generation, physical design verification and mask tooling must be revisited in the context of various MCM substrate technologies. The thermal aspects of MCM design are strongly influenced by the placement of chips on the MCM substrate. Thermal design is especially important for high density MCMs using the flip-chip mounting technology. Here, the heat must be dissipated through the back of the substrate via thermal pillars or bumps. We still need to deal with the traditional coupled transmission line problems. Due to the small cross section, high performance MCM substrate interconnects are resistive and the transmission lines they form are lossy. Noise is another main problem for MCM design. For high speed MCM with many CMOS buffers, the ground bouncing noise resulting from simultaneous switching of a large number of CMOS drivers must be controlled through proper substrate and package design. We will conclude the paper by comparing existing VLSI and PCB EDA tools for MCM design.
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Ghannam, Ayad, Alessandro Magnani, David Bourrier, and Thierry Parra. "Wafer Level 3D System Integration using a Novel 3D-RDL Technology." International Symposium on Microelectronics 2015, no. 1 (October 1, 2015): 000092–97. http://dx.doi.org/10.4071/isom-2015-tp36.
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A new wafer-level 3D system integration process that relies on a novel multi-level 3D redistribution layer technology (3D-RDL) to interconnect chips together as well as to the substrate was developed. The 3D-RDL technology is based on a single electroplating step that allows routing high density, auto-adaptive vertical copper interconnects (20 μm Line/Space “L/S”) at the edge of known-good dies as well as redistribution layer on top of the die and the substrate. Furthermore, this technology enables 3D interconnection of stacked dies using a single 3D-RDL layer. Additionally, high performance 3D inductive devices with small form factor can be integrated above-IC or above-substrate using the same 3D-RDL processing steps. These capabilities allow miniaturization and performance enhancement and make the technology ideal for various applications requiring functional heterogeneous system integration on a small footprint, such as systems for mobile and Internet-of-Things (IoT) applications, MEMS and Sensors.
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Habu, Tomoyuki, Shinichi Endo, and Shintaro Yabu. "Result of high accelerated stress test of organic substrates made by integrated dry process." International Symposium on Microelectronics 2018, no. 1 (October 1, 2018): 000153–60. http://dx.doi.org/10.4071/2380-4505-2018.1.000153.
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Abstract The uses of the semiconductor increase by the development of Internet of Things. Miniaturization of the semiconductor wiring to bring speedup, electric power saving advances, and various technologies are developed. The new technology that applied a semiconductor production technology is waited eagerly for the production of the printed circuit board and semiconductor packaging. We presented new dry process “Integrated dry process” using Photodesmear technology and sputter seed process in IMAPS2016 Pasadena. After the micro via formation with the laser, the smear is effective to remove a smear remaining behind in the via bottom by Photodesmear. Furthermore, we improved adhesion between copper metal and epoxy resin in a sputtering seed together. We made the large experimental tool that Photodesmear could process an actually size of the print circuit board by static irradiation. And we proved that handling of panel size was technically possible. The connection reliability of the contact via is evaluated after electric copper plating by quick via peel examination. A cross section of the vias was made and, the residual smear removal properties of wet desmear processing and the Photodesmear processing were compared with the residual smear and the thin oxidation layer by observation of the connection interface. The interfacial surface state after the desmear processing was analyzed in X-ray probe analyzer. We produced the test vehicle using Photodesmear technology and a sputtering seed technology. I compared it with the same pattern sample produced by a process conventionally. In this paper, we report the result of the high accelerated temperature and humidity stress test.
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Saris, Nur Najahatul Huda, Osamu Mikami, Azura Hamzah, Sumiaty Ambran, and Chiemi Fujikawa. "A V-Shape Optical Pin Interface for Board Level Optical Interconnect." Photonics Letters of Poland 10, no. 1 (March 31, 2018): 20. http://dx.doi.org/10.4302/plp.v10i1.786.
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This paper introduces a new interface of an optical pin for Printed Circuit Boards (PCBs), the V-shape cut type which is an innovation from the 90-degree cut type optical pin. The effectiveness is determined by optical characteristics through OptiCAD and by experiment. The simulation used a model of ray tracing analysis which is a one to two (split) connection function model. For the experiment, a Polymer Optical Fibre (POF) V-shape optical pin has been fabricated. It was found that the V-shaped optical pin has a multi-branched function and is applicable to optical interconnection. Full Text: PDF ReferencesMikami, O., et al. Optical pin interface for 90-deg optical path conversion coupling to Printed Wiring Board. in Region 10 Conference (TENCON), 2016 IEEE. 2016. IEEE. CrossRef DeCusatis, C., Data center architectures, in Optical Interconnects for Data Centers. 2017, Elsevier. p. 3-41. CrossRef Duranton, M., D. Dutoit, and S. Menezo, Key requirements for optical interconnects within data centers, in Optical Interconnects for Data Centers. 2017, Elsevier. p. 75-94. CrossRef ITOH, Y., et al., Optical Coupling Characteristics of Optical Pin with 45° Micro Mirror for Optical Surface Mount Technology. Journal of The Japan Institute of Electronics Packaging, 2001. 4(6): p. 497-503. CrossRef Uchida, T. and O. Mikami, Optical surface mount technology. IEICE Transactions on Electronics, 1997. 80(1): p. 81-87. CrossRef Papakonstantinou, I., et al., Low-cost, precision, self-alignment technique for coupling laser and photodiode arrays to polymer waveguide arrays on multilayer PCBs. IEEE Transactions on Advanced Packaging, 2008. 31(3): p. 502-511. CrossRef Nakama, K., et al., Optical connection device. 2006, Google Patents. DirectLink Ramaswami, R., K. Sivarajan, and G. Sasaki, Optical networks: a practical perspective. 2009: Morgan Kaufmann. DirectLink Tong, X.C., Advanced materials for integrated optical waveguides. 2014: Springer. CrossRef
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Hernandez, George A., Daniel Martinez, Stephen Patenaude, Charles Ellis, Michael Palmer, and Michael Hamilton. "Through Si Vias Using Liquid Metal Conductors for Re-workable 3D Electronics." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (January 1, 2013): 001343–57. http://dx.doi.org/10.4071/2013dpc-wp13.
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This paper describes the design and fabrication of liquid metal interconnects (vias) for 2.5D and 3D integration. The liquid metal is gallium indium eutectic with a melting temperature of approximately 15.7°C that is introduced into via openings of a silicon interposer. This liquid interconnect technology can be integrated with existing interposer technologies, such as capacitors and traditional (solid metal) through-silicon vias (TSVs). In addition, liquid metal interconnects can better accommodate thermal stresses and provide re-workability in case of chip failure. Our research efforts are focused on the integration of multi-chip modules using liquid metal interconnects. Our study encompasses Direct Current (D.C.) measurements and failure analysis using snake and comb structures at low temperature (10 degrees Kelvin) to slightly above room temperature (300 degrees Kelvin). The snake and comb structure allows us to measure electrical shorts and opens, as well as provide estimates of via yield and allows additional information for determination of possible failure mechanisms. In order to make electrical contact to the liquid metal interconnect interposer from both the top and bottom, test coupons have been fabricated with arrays of large numbers of vias. The interposer structure consists of a thin (200 um thick) silicon wafer with via holes filled with liquid metal. The test coupon consists of bottom and top silicon die with a thickness of 500 um. The bottom wafer incorporates a 2 um-thick daisy-chain metallization and 100 um copper tall vias, which are electrically isolated from each other and the underlying Si by patterned AL-X dielectric. The top wafer incorporates an array of 80 um tall, electroplated copper pillars and top daisy-chain metallization. Liquid metal containment mechanisms and structures have also been investigated. In our presentation we will describe the design, fabrication and characterization of this re-workable interposer with liquid metal interconnects. We will present D.C. resistance and X-ray imagery of the liquid metal filled via. In addition, we will provide failure analysis of via yield per chip.
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Sterken, T., M. Op de Beeck, F. Vermeiren, T. Torfs, L. Wang, S. Priyabadini, K. Dhaenens, D. Cuypers, and J. Vanfleteren. "High Yield Embedding of 30μm Thin Chips in a Flexible PCB using a Photopatternable Polyimide based Ultra-Thin Chip Package (UTCP)." International Symposium on Microelectronics 2012, no. 1 (January 1, 2012): 000940–45. http://dx.doi.org/10.4071/isom-2012-wp52.
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A thin chip package for off-the-shelf ICs is developed which enables the embedding of these chips into a flexible circuit board. The package consists of a copper fan-out on a polyimide substrate, in which the thinned IC (30μm) is embedded. These packages are subsequently integrated in a standard flexible circuit board (FCB). A microcontroller and a proprietary DSP processor are embedded using this technology. The yield of the Ultra-Thin Chip package (UTCP) was measured before embedding in the circuit board, and reaches up to 87% for the packaged microcontrollers (MSP430 family, known-good dies). The yield on the DSP processor was measured to be 62%. After embedding in the FCB, 95% of the functional UTCP-packaged dies are still functional.
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Pethuraja, Gopal G., Roger E. Welser, John W. Zeller, Yash R. Puri, Ashok K. Sood, Harry Efstathiadis, Pradeep Haldar, and Jennifer L. Harvey. "Advanced Flexible CIGS Solar Cells Enhanced by Broadband Nanostructured Antireflection Coatings." MRS Proceedings 1771 (2015): 145–50. http://dx.doi.org/10.1557/opl.2015.589.
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ABSTRACTFlexible copper indium gallium diselenide (CIGS) solar cells on lightweight substrates can deliver high specific powers. Flexible lightweight CIGS solar cells are also primary candidates for building-integrated panels. In all applications, CIGS cells can greatly benefit from the application of broadband and wide-angle AR coating technology. The AR coatings can significantly improve the transmittance of light over the entire CIGS absorption band spectrum. Increased short-circuit current has been observed after integrating AR coated films onto baseline solar panels. NREL’s System Advisor Model (SAM) has predicted up to 14% higher annual power output on AR integrated vertical or building-integrated panels. The combination of lightweight flexible substrates and advanced device designs employing nanostructured optical coatings together have the potential to achieve flexible CIGS modules with enhanced efficiencies and specific power.
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Wickham, Martin, Kate Clayton, Ana Robador, and Christine Thorogood. "Organic Hybrids for Circuit Assemblies – Initial environmental testing of a low cost alternative to ceramic substrate based assemblies." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2018, HiTEC (May 1, 2018): 000022–27. http://dx.doi.org/10.4071/2380-4491-2018-hiten-000022.
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Abstract There are an increasing number of electronics applications in aerospace, automotive, shale/gas and power management, which are required to operate at or above 200 °C. Organic matrix reinforced substrates such as polyimide, have maximum operating temperatures in the region of 175 °C. Reliable operation of electronics at temperatures higher than this requires a combination of performance improvements in components, interconnects and substrates. Ceramic based substrate options are based on alumina substrates with printed inks fired at ~ 600 °C and can be costly, heavy and prone to mechanical damage. Printed circuit board (PCB) options are restricted to lower working temperatures of the organic resins and degradation of their conductive copper tracks through oxidation. This paper highlights earlier work undertaken by the authors and partners to understand the deficiencies of copper-clad PCB technology and details work to develop a low cost alternative to ceramic substrate based assemblies. The authors have investigated replacing the alumina substrates with high temperature engineering thermoplastics such as PEEK. The high temperature fired inks conventionally used in hybrid circuit manufacture have been replaced with screen-printable silicone based ink systems curing at 250 °C. The specially developed electrically conductive and dielectric inks were utilised to produce a multilayer system demonstrator with high temperature compatible components attached using a high temperature conductive adhesive. Such an assembly system has the potential to benefit from reductions in substrate cost and assembly weight. Energy cost associated with manufacture are significantly reduced. In addition the organic substrate is easier to machine and form into complex shapes and offers the possibility of integrating thermal management solutions. Environmental testing has been undertaken to determine the suitability of the system to operate for extended periods at 250 °C and the results of the electrical and mechanical performance for continuous ageing of test assemblies at 250 °C will be given.
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Kumar Sharma, Devendra, Brajesh Kumar Kaushik, and R. K. Sharma. "Impact of driver size and interwire parasitics on crosstalk noise and delay." Journal of Engineering, Design and Technology 12, no. 4 (September 30, 2014): 475–90. http://dx.doi.org/10.1108/jedt-08-2012-0036.
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Purpose – The purpose of this research paper is to analyze the combined effects of driver size and coupling parasitics on crosstalk noise and delay for static and dynamically switching victim line. Furthermore, this paper shows the effect of inductance on delay and qualitatively optimizes its value to obtain minimum delay. Design/methodology/approach – The interwire parasitics are the primary sources of crosstalk or coupled noise that may lead to critical delays/logic malfunctions. This paper is based on simulating a pair of distributed resistance inductance capacitance (RLC) interconnects coupled capacitively and inductively for measurements of crosstalk noise/delay. The combined effects of driver sizing and interwire parasitics on peak overshoot noise/delay are observed through simulation program with integrated circuit emphasis (SPICE) simulations for different switching patterns. Furthermore, the analysis of inductive effect on propagation delay as a function of coupling capacitance is carried out and the optimization of delay is worked out qualitatively. The simulations are carried out at 0.13 μm, 1.5 V technology node. Findings – This paper observes the contradictory effects of coupling parasitics on wire propagation delay; however, the effect on peak noise is of a different kind. Further, this paper shows that the driver size exhibits opposite kind of behavior on propagation delay than peak over shoot noise. It is observed that the delay is affected in presence of inductance; thus, the optimization of delay is carried out. Originality/value – The effects of driver sizing and interwire parasitics are analyzed through simulations. The optimum value of coupling capacitance for delay is found qualitatively. These findings are important for designing very large scale integration (VLSI) interconnects.
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Cho, Sangbeom, Venky Sundaram, Rao Tummala, and Yogendra Joshi. "Multi-scale thermal modeling of glass interposer for mobile electronics application." International Journal of Numerical Methods for Heat & Fluid Flow 26, no. 3/4 (May 3, 2016): 1157–71. http://dx.doi.org/10.1108/hff-09-2015-0378.
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Purpose – The functionality of personal mobile electronics continues to increase, in turn driving the demand for higher logic-to-memory bandwidth. However, the number of inputs/outputs supported by the current packaging technology is limited by the smallest achievable electrical line spacing, and the associated noise performance. Also, a growing trend in mobile systems is for the memory chips to be stacked to address the growing demand for memory bandwidth, which in turn gives rise to heat removal challenges. The glass interposer substrate is a promising packaging technology to address these emerging demands, because of its many advantages over the traditional organic substrate technology. However, glass has a fundamental limitation, namely low thermal conductivity (∼1 W/m K). The purpose of this paper is to quantify the thermal performance of glass interposer-based electronic packages by solving a multi-scale heat transfer problem for an interposer structure. Also, this paper studies the possible improvement in thermal performance by integrating a fluidic heat spreader or vapor chamber within the interposer. Design/methodology/approach – This paper illustrates the multi-scale modeling approach applied for different components of the interposer, including Through Package Vias (TPVs) and copper traces. For geometrically intricate and repeating structures, such as interconnects and TPVs, the unit cell effective thermal conductivity approach was used. For non-repeating patterns, such as copper traces in redistribution layer, CAD drawing-based thermal resistance network analysis was used. At the end, the thermal performance of vapor chamber integrated within a glass interposer was estimated by using an enhanced effective thermal conductivity, calculated from the published thermal resistance data, in conjunction with the analytical expression for thermal resistance for a given geometry of the vapor chamber. Findings – The limitations arising from the low thermal conductivity of glass can be addressed by using copper structures and vapor chamber technology. Originality/value – A few reports can be found on thermal performance of glass interposers. However thermal characteristics of glass interposer with advanced cooling technology have not been reported.
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Ramm, Peter, Armin Klumpp, Alan Mathewson, Kafil M. Razeeb, and Reinhard Pufall. "The European 3D Heterogeneous Integration Platform (e-BRAINS) - a Particular Focus on Reliability and Low-Temperature Processes for 3D Integrated Sensor Systems." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, DPC (January 1, 2015): 001847–84. http://dx.doi.org/10.4071/2015dpc-tha11.
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The European 3D heterogeneous integration platform has been established by the consortium of the Integrated Project e-BRAINS [1], where technologies of the following relevant main categories of 3D integration are provided to enable future applications of smart sensor systems:3D System-on-Chip Integration - 3D-SOC: TSV technology for stacking of thinned devices or large IC blocks (global level),3D Wafer-Level-Packaging - 3D-WLP: embedding technology with through-polymer vias (TPV) for stacking of thinned ICs on wafer-level (no TSV), and3D System-in-Package - 3D-SIP: 3D stacking of packaged devices or substrates *definitions according to [2] Regarding TSV performance, the applications do not need ultra-high vertical interconnect densities as for 3D stacked Integrated Circuits – 3D-SIC*. Nevertheless, the lateral sizes of the TSVs are preferably minimized to allow for place and route for small “open” IC areas. Smaller TSVs are also preferred in order to reduce thermo-mechanical stress. e-BRAINS' focus is on how heterogeneous integration and sensor device technologies can be combined to bring new performance levels to targeted applications with high market potentials. The consortium, under coordination of Infineon and technical management by Fraunhofer EMFT, is composed of major European system manufacturers (Infineon, Siemens, SensoNor, 3D PLUS, Vermon and IQE), SMEs (DMCE, Magna Diagnostics, SORIN and eesy-ID), the large research institutions CEA Grenoble, Fraunhofer (EMFT Munich & IIS-EAS Dresden), imec, SINTEF, Tyndall and ITE Warsaw, and universities (EPFL Lausanne, TU Chemnitz and TU Graz). Target applications include automotive, ambient living and medical devices, with a specific focus on wireless sensor systems. Concerning the enabling 3D Heterogeneous Integration Platform, the e-BRAINS partners are working close together, where Infineon, Fraunhofer EMFT, imec and SINTEF are focusing mainly on 3D-SOC and 3D-WLP, and the French system manufacturer 3D PLUS and Tyndall on 3D-WLP and 3D-SIP technologies. The focus of this paper is on low-temperature bonding processes for highly reliable 3D integrated sensor systems. One of the key issues for heterogeneous systems production is the impact of 3D processes to the reliability of the product, i.e. the high built-in stresses caused by e.g. the CTE mismatch of complex layer structures (thin Si, ILDs, metals etc.) in combination with elevated bonding temperatures. As consequence, extensive project work was dedicated in the developments of reliable low-temperature bonding processes. Mainly intermetallic compound (IMC) bonding with Cu/Sn metal systems supported by ultrasonic agitation (Fraunhofer EMFT) was successfully introduced in 3D integration technology (see Fig. 2). A copper/tin solid-liquid interdiffusion (SLID) system was investigated using ultrasonic agitation to reduce the assembly temperature below the melting point of tin. Cleaning procedures are important shortly before joining the samples; dry cleaning has best results due to removal of thin oxide layers. Figure 2 shows a cross section of US supported Cu/Sn bonding at 150C. The intermetallic compounds Cu3Sn and Cu6Sn5 as well as pure tin easily can be identified. Due to low temperature assembly the most stable intermetallic compound (IMC) Cu3Sn has a minor share of the metal system. Most importantly there is no gap between top and bottom part of the joint despite the macroscopic assembly temperature is far away from the melting point of tin. But maybe the ultrasonic agitation brings enough energy to the interfaces, so locally melting can occur. In this way robust IMC bonding technology at 150C could be demonstrated with shear forces of 17 MPa and an alignment accuracy of 3 μm, well-suited for 3D integration. Figure 2: Low-temperature IMC bonding technology using ultrasonic agitation (Fraunhofer EMFT) Reliability for SLID contacts is certainly a very challenging objective especially looking for robust solutions in automotive applications. Thermally induced mechanical stress is the main reason for early fails during temperature cycling. Cross sectioned samples were investigated and methods like nanoindentation, Raman spectroscopy, fibDAC, and high local resolution x-ray scattering were applied to measure the intrinsic stresses. It can be shown that low temperature bonding is the right approach to avoid excessive stress cracking the interface or even fracturing the silicon. Also fatigue of metals can be reduced in a range that plastic deformation is no lifetime limiting factor.
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Levy, Andrew, Hans Manhaeve, and Ed McBain. "An Innovative 2.5D IC Interconnection Reliability System." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (January 1, 2013): 002056–89. http://dx.doi.org/10.4071/2013dpc-tha34.
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In this paper we present a new methodology that addresses the quality and reliability problems of applications that deploy “2.5D” packaging technology for integrated circuits (ICs). This technology employs through-silicon vias (TSVs), enabling greatly increased circuit density, performance, and functionality for a given volume. The 2.5D ICs require the use of an interposer to route signals between the chips and the package substrate. While this packaging solution has some distinct advantages over other packaging/mounting technologies, there are disadvantages as well. Qualifying and testing such connections is very difficult and expensive, and techniques for anticipating failure do not currently exist. Therefore, confidence in the reliability of 2.5D IC interconnects is lacking. Systems that use them may require a high level of preventive maintenance whenever possible, or such packaging may simply be avoided when such maintenance is not possible or practical. The paper outlines an approach that combines embedded digital and analog measurement instruments that are capable of detecting and identifying opens and shorts in 2.5D IC TSV stacks. The monitors reside on the silicon interposer. This system is the first to address the difficult issue of 2.5D IC package interconnect integrity after assembly is done and when the related devices are deployed in larger systems. The innovation will improve reliability of TSV-based packaging by detecting and identifying faulty connections at package test during the manufacturing process. It also provides prognostic monitoring so that interconnect-related operational faults can be detected before actual system failure occurs after the packaged component is deployed in the field.
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Chien, Chun-Hsien, Yu-Hua Chen, Yu-Chung Hsieh, Wei-Ti Lin, Chien-Chou Chen, Dyi-Chung Hu, Tzvy-Jang Tseng, and Ravi Shenoy. "Glass 3D Solenoid Inductors IPD Substrate Manufacturing Assembly and Characterization." International Symposium on Microelectronics 2016, no. 1 (October 1, 2016): 000013–17. http://dx.doi.org/10.4071/isom-2016-tp13.
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Abstract This paper aims to discuss the integration of 3D solenoid inductors fabricated by using a glass core substrate with through glass via (TGV) technology. Glass materials were chosen for the substrate core based on the natural properties of low insertion loss, adjustable CTE, low surface roughness and high insulation for RF application. The TGV formation and semi-additive conformal copper electroplating were the key processes of the glass core substrate manufacturing. The key benefits of these evaluations are a competitive cost structure for a 508mm × 508mm glass panel IC (integrated circuit) substrate HVM (high volume manufacture) line. The characterization results of TGV formation, the process flow of 3D solenoid inductor glass core substrate and real silicon device chips assembled on the top of glass core substrate were also investigated and discussed.