Relevant bibliographies by topics / Interconnects (Integrated circuit technology) Metal oxide semiconductors

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Conference papers

Academic literature on the topic 'Interconnects (Integrated circuit technology) Metal oxide semiconductors'

Author: Grafiati
Published: 4 June 2021
Last updated: 5 February 2022

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Journal articles on the topic "Interconnects (Integrated circuit technology) Metal oxide semiconductors"

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Garner, C. Michael. "Lithography for enabling advances in integrated circuits and devices." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 370, no. 1973 (August 28, 2012): 4015–41. http://dx.doi.org/10.1098/rsta.2011.0052.

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Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.
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Soref, Richard. "Applications of Silicon-Based Optoelectronics." MRS Bulletin 23, no. 4 (April 1998): 20–24. http://dx.doi.org/10.1557/s0883769400030220.

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Silicon-based optoelectronics is a diversified technology that has grown steadily but not exponentially over the past decade. Some applications—such as smart-pixel signal processing and chip-to-chip optical interconnects—have enjoyed impressive growth, whereas other applications have remained quiescent. A few important applications such as optical diagnosis of leaky metal-oxide-semiconductor-field-effect-transistor circuits, have appeared suddenly. Over the years, research and development has unveiled some unique and significant aspects of Si-based optoelectronics. The main limitation of this technology is the lack of practical silicon light sources—Si lasers and efficient Si light-emitting devices (LEDs)—though investigators are “getting close” to the LED.Silicon-based optoelectronics refers to the integration of photonic and electronic components on a Si chip or wafer. The photonics adds value to the electronics, and the electronics offers low-cost mass-production benefits. The electronics includes complementary-metal-oxide semiconductors (CMOS), very large-scale integration (VLSI), bipolar CMOS, SiGe/Si heterojunction bipolar transistors, and heterostructure field-effect transistors. In this discussion, we will use a loose definition of optoelectronics that includes photonic and optoelectronic integrated circuits (PICs and OEICs), Si optical benches, and micro-optoelectromechanical (MOEM) platforms. Optoelectronic chips and platforms are subsystems of computer systems, communication networks, etc. Silicon substrates feature a superior native oxide, in addition to excellent thermal, mechanical, and economic properties. Silicon wafers “shine” as substrates for PICs and OEICs.
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Khursheed, Afreen, and Kavita Khare. "Designing dual-chirality and multi-Vt repeaters for performance optimization of 32 nm interconnects." Circuit World 46, no. 2 (January 13, 2020): 71–83. http://dx.doi.org/10.1108/cw-06-2019-0060.

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Purpose This paper is an unprecedented effort to resolve the performance issue of very large scale integrated circuits (VLSI) interconnects encountered because of the scaling of device dimensions. Repeater interpolation technique is an effective approach for enhancing speed of interconnect network. Proposed buffers as repeater are modeled by using dual chirality multi-Vt technology to reduce delay besides mitigating average power consumption. Interconnects modeled with carbon nanotube (CNT) technology are compared with copper interconnect for various lengths. Buffer circuits are designed with both CNT and metal oxide semiconductor technology for comparison by using various combination of (CMOSFET repeater-Cu interconnect) and (CNTFET repeater-CNT interconnect). Compared to conventional buffer, ProposedBuffer1 saves dynamic power by 84.86%, leakage power by 88% and offers reduction in delay by 72%. ProposedBuffer2 brings about dynamic power saving of 99.94%, leakage power saving of 93%, but causes delay penalty. Simulation using Stanford SPICE model for CNT and silicon-field effective transistor berkeley short-channel IGFET Model4 (BSIM4) predictive technology model (PTM) for MOS is done in H simulation program with integrated circuit emphasis for 32 nm. Design/methodology/approach Usually, the dynamic power consumption dominates the total power, while the leakage power has a negligible effect. But with the scaling of device technology, leakage power has become one of the important factors of consideration in low power design techniques. Various strategies are explored to suppress the leakage power in standby mode. The adoption of a multi-threshold design strategy is an effective approach to improve the performance of buffer circuits without compromising on the delay and area overhead. Unlike MOS technology, to implement multi-Vt transistors in case of CNT technology is quite easy. It can be achieved by varying diameter of carbon nanotubes using chirality control. Findings An unprecedented approach is taken for optimizing the delay and power dissipation and hence drastically reducing energy consumption by keeping proper harmony between wire technology and repeater-buffer technology. This paper proposes two novel ultra-low power buffers (PB1 and PB2) as repeaters for high-speed interconnect applications in portable devices. PB1 buffer implemented with high-speed CML technique nested with multi-threshold (Vt) technology sleep transistor so as to improve the speed along with a reduction in standby power consumption. PB2 is judicially implemented by inserting separable sized, dual chirality P type carbon nanotube field effective transistors. The HSpice simulation results justify the correctness of schemes. Originality/value Result analysis points out that compared to conventional Cu interconnect, the CNT interconnects paired with Proposed CNTFET buffer designs are more energy efficient. PB1 saves dynamic power by 84.86%, reduces propagation delay by 72% and leakage power consumption by 88%. PB2 brings about dynamic power saving of 99.4%, leakage power saving of 93%, with improvement in speed by 52%. This is mainly because of the fact that CNT interconnect offers low resistance and CNTFET drivers have high mobility and ballistic mode of operation.
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Palma, Fabrizio. "New Insight on Terahertz Rectification in a Metal–Oxide–Semiconductor Field-Effect Transistor Structure." Electronics 9, no. 7 (July 3, 2020): 1089. http://dx.doi.org/10.3390/electronics9071089.

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The use of a metal–oxide–semiconductor field-effect transistor (MOS-FET) permits the rectification of electromagnetic radiation by employing integrated circuit technology. However, obtaining a high-efficiency rectification device requires the assessment of a physical model capable of providing a qualitative and quantitative explanation of the processes involved. For a long time, high-frequency detection based on MOS technology was explained using plasma wave detection theory. In this paper, we review the rectification mechanism in light of high-frequency numerical simulations, showing features never examined until now. The results achieved substantially change our understanding of terahertz (THz) rectification in semiconductors, and can be interpreted by the model based on the self-mixing process in the device substrate, providing a new and essential tool for designing this type of detector.
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Palma, Fabrizio. "Self-Mixing Model of Terahertz Rectification in a Metal Oxide Semiconductor Capacitance." Electronics 9, no. 3 (March 14, 2020): 479. http://dx.doi.org/10.3390/electronics9030479.

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Metal oxide semiconductor (MOS) capacitance within field effect transistors are of great interest in terahertz (THz) imaging, as they permit high-sensitivity, high-resolution detection of chemical species and images using integrated circuit technology. High-frequency detection based on MOS technology has long been justified using a mechanism described by the plasma wave detection theory. The present study introduces a new interpretation of this effect based on the self-mixing process that occurs in the field effect depletion region, rather than that within the channel of the transistor. The proposed model formulates the THz modulation mechanisms of the charge in the potential barrier below the oxide based on the hydrodynamic semiconductor equations solved for the small-signal approximation. This approach explains the occurrence of the self-mixing process, the detection capability of the structure and, in particular, its frequency dependence. The dependence of the rectified voltage on the bias gate voltage, substrate doping, and frequency is derived, offering a new explanation for several previous experimental results. Harmonic balance simulations are presented and compared with the model results, fully validating the model’s implementation. Thus, the proposed model substantially improves the current understanding of THz rectification in semiconductors and provides new tools for the design of detectors.
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Lopez-Diaz, Daniel, Ingmar Kallfass, Axel Tessmann, Rainer Weber, Hermann Massler, Arnulf Leuther, Michael Schlechtweg, and Oliver Ambacher. "High-performance 60 GHz MMICs for wireless digital communication in 100 nm mHEMT technology." International Journal of Microwave and Wireless Technologies 3, no. 2 (March 3, 2011): 107–13. http://dx.doi.org/10.1017/s1759078711000109.

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Wireless data communication is pushing towards 60 GHz and will most likely be served by SiGe and Complementary Metal Oxide Semiconductor (CMOS) technologies in the consumer market. Nevertheless, some applications are imposing superior performance requirements on the analog frontend, and employing III-V compound semiconductors can provide significant advantages with respect to transmitter power and noise figure. In this paper, we present essential building blocks and a novel single-chip low complexity transceiver Monolithic Microwave Integrated Circuit (MMIC) with integrated antenna switches for 60 GHz communication, fabricated in a 100 nm metamorphic high electron mobility transistor (mHEMT) technology. This technology features a measured noise figure of <2.5 dB in low-noise amplifiers at 60 GHz and the realized medium power amplifiers achieve more than 20 dBm saturated output power. Integrated antenna switches with an insertion loss of less than 1.5 dB enable the integration of the transmit and the receive stages on a single chip. A single-chip transceiver with external subharmonic Local Oscillator (LO) supply for its I/Q down- and up-converter achieves a linear conversion gain in both, the Transmit (Tx) and the Receive (Rx) paths, of more than 10 dB.
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Ren, Xiaojiao, Ming Zhang, Nicolas Llaser, and Yiqi Zhuang. "On-Chip Measurement of Quality Factor Implemented in 0.35μm CMOS." Journal of Circuits, Systems and Computers 25, no. 08 (May 17, 2016): 1650087. http://dx.doi.org/10.1142/s0218126616500870.

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Based on time-domain quality factor (Q-factor) measurement principle, we have proposed an architecture which has the potential to be integrated on-chip. Thanks to the proposed original reconfigurable structure, the main measurement error from the offset of the operational transconductance amplifier (OTA) used can be cancelled automatically during the measurement operation, leading to a high accuracy Q-factor measurement. The digital control circuit plays an important role in the automatic passage between the two configurations designed, i.e., peak detector and comparator. The main advantages of the proposed time-domain Q-factor measurement lay on the possibility of being integrated next to the Micro Electro Mechanical System (MEMS) resonator to be measured, the miniaturization of the whole measuring system as well as the enhancement of the measurement performance, and to guide the design of such architecture, a theoretical analysis linking the required accuracy and the given Q-factor to the circuit parameters have been given in this paper. The proposed circuit is designed and simulated in a 0.35[Formula: see text][Formula: see text]m Complementary Metal Oxide Semiconductors (CMOS) technology. The post-layout simulation results show that the operating frequency can reach up to 200[Formula: see text]kHz with an accuracy of 0.4%.
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Merschky, Michael, Fabian Michalik, Martin Thoms, Robin Taylor, Diego Reinoso-Cocina, Stephan Hotz, and Patrick Brooks. "Using a Metal Oxide Adhesion Layer and Wet Chemical Cu Metallization for Fine Line Pattern Formation on Glass." International Symposium on Microelectronics 2017, no. 1 (October 1, 2017): 000458–63. http://dx.doi.org/10.4071/isom-2017-wp51_084.

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Abstract With the trends towards miniaturization and heterogeneous integration, both IC and advanced substrate manufacturers are striving to meet the needs of next generation platforms, to increase the density of interconnects, and generate conductors featuring finer lines and spaces. Advanced manufacturing technologies such as Semi-Additive-Processing (SAP) and Advanced Modified-Semi-Additive-Processing (amSAP) were devised, realized and implemented in order to meet these requirements. Line and space (L/S) requirements of copper conductors will be below 5/5μm for advanced substrates, with 2/2μm L/S required for chip to chip connections in the near future. Herein we report about the performance of the new developed ferric sulfate based EcoFlash™ process for SAP and amSAP application with the focus on glass as the substrate and VitroCoat as thin metal oxide adhesion promotion layer. The adhesion promotion layer (about 5–10 nm thickness) is dip-coated by a modified sol-gel process followed by sintering which creates chemical bonds to the glass. The sol-gel dip coating process offers good coating uniformity on both Though-Glass-Via (TGV) and glass surfaces under optimized coating conditions. Uniform coating can be achieved up to aspect ratios of 10:1 by using a 300μm thick glass with 30μm diameter TGV. The thin adhesive layer enables electroless and electrolytic copper plating directly onto glass substrates. Excellent adhesion of electroless plated copper seed layer on glass can be achieved by using the adhesive layer and annealing technology. The thin adhesive layer is non-conductive and can be easily removed from the area between circuit traces together with the electroless copper seed layer by etching with a ferric sulfate based process. We have successfully integrated the adhesion layer and electroless and electrolytic copper plating technologies into semi-additive process and seed layer etching capable producing L/S below 10 μm.
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Sidhu, Ramneek, and Mayank Kumar Rai. "Edge scattering limited crosstalk analysis in adjacent multilayer graphene interconnects and its impact on gate oxide reliability." Circuit World ahead-of-print, ahead-of-print (July 15, 2021). http://dx.doi.org/10.1108/cw-09-2020-0233.

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Purpose This paper aims to present the edge scattering dominant circuit modeling. The effect of crosstalk on gate oxide reliability (GOR), along with the mitigation using shielding technique is further studied. Design/methodology/approach An equivalent distributed Resistance Inductance Capacitance circuit of capacitively coupled interconnects of multilayer graphene nanoribbon (MLGNR) has been considered for T Simulation Program with Integrated Circuit Emphasis (TSPICE) simulations under functional and dynamic switching conditions. Complementary metal oxide semiconductor driver transistors are modeled by high performance predictive technology model that drive the distributed segment with a capacitive load of 0.001 fF, VDD and clock frequency as 0.7 V and 0.2 GHz, respectively, at 14 nm technology node. Findings The results reveal that the crosstalk induced delay and noise area are dominated by the overall mean free path (MFP) (i.e. including the effect of edge roughness induced scattering), in contrary to, acoustic and optical scattering limited MFP with the temperature, width and length variations. Further, GOR, estimated in terms of average failure rate (AFR), shows that the shielding technique is an effective method to minimize the relative GOR failure rate by, 0.93e-7 and 0.7e-7, in comparison to the non-shielded case with variations in interconnect’s length and width, respectively. Originality/value Considering realistic circuit modeling for MLGNR interconnects by incorporating the edge roughness induced scattering mechanism, the outcomes exhibit more penalty in terms of crosstalk induced noise area and delay. The shielding technique is found to be an effective mitigating technique for minimizing AFR in coupled MLGNR interconnects.
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Catrysse, Peter B. "Monolithic Integration of Electronics and Sub-wavelength Metal Optics in Deep Submicron CMOS Technology." MRS Proceedings 869 (2005). http://dx.doi.org/10.1557/proc-869-d1.5.

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AbstractThe structures that can be implemented and the materials that are used in complementary metal-oxide semiconductor (CMOS) integrated circuit (IC) technology are optimized for electronic performance. However, they are also suitable for manipulating and detecting optical signals. In this paper, we show that while CMOS scaling trends are motivated by improved electronic performance, they are also creating new opportunities for controlling and detecting optical signals at the nanometer scale. For example, in 90-nm CMOS technology the minimum feature size of metal interconnects reaches below 100 nm. This enables the design of nano-slits and nano-apertures that allow control of optical signals at sub-wavelength dimensions. The ability to engineer materials at the nanoscale even holds the promise of creating meta-materials with optical properties, which are unlike those found in the world around us. As an early example of the monolithic integration of electronics and sub-wavelength metal optics, we focus on integrated color pixels (ICPs), a novel color architecture for CMOS image sensors. Following the trend of increased integration in the field of CMOS image sensors, we recently integrated color-filtering capabilities inside image sensor pixels. Specifically, we demonstrated wavelength selectivity of sub-wavelength patterned metal layers in a 180-nm CMOS technology. To fulfill the promise of monolithic photonic integration and to design useful nanophotonic components, such as those employed in ICPs, we argue that analytical models capturing the underlying physical mechanisms of light-matter interaction are of utmost importance.
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Dissertations / Theses on the topic "Interconnects (Integrated circuit technology) Metal oxide semiconductors"

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Mule, Anthony Victor. "Volume grating coupler-based optical interconnect technologies for polylithic gigascale integration." Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-06072004-131259/unrestricted/mule%5Fanthony%5Fv%5F200405%5Fphd.pdf.

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Mule, Anthony Victor. "Volume grating coupler-based optical interconnect technologies for polylithic gigascale integrat." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/9447.

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Rakheja, Shaloo. "Interconnects for post-CMOS devices: physical limits and device and circuit implications." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45866.

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The objective of this dissertation is to classify the opportunities, advantages, and limits of novel interconnects for post-CMOS logic that can augment or eventually replace the CMOS logic. Post-CMOS devices are envisaged on the idea of using state variables other than the electron charge to store and manipulate information. In the first component of the thesis, a comprehensive analysis of the performance and the energy dissipation of novel logic based on various state variables is conducted, and it is demonstrated that the interconnects will continue to be a major challenge even for post-CMOS logic. The second component of the thesis is focused on the analysis of the interconnection aspects of spin-based logic. This research goal is accomplished through the development of physically-based models of spin-transport parameters for various metallic, semiconducting, and graphene nanoribbon interconnects by incorporating the impact of size effects for narrow cross-sectional dimensions of all-spin logic devices. Due to the generic nature of the models, they can be used in the analysis of spin-based devices to study their functionality and performance more accurately. The compact nature of the models allows them to be easily embedded into the developing CAD tools for spintronic logic. These models then provide the foundation for (i) analyzing the spin injection and transport efficiency in an all-spin logic circuit with various interconnect materials, and (ii) estimating the repeater-insertion requirements in all-spin logic, and (iii) estimating the maximum circuit size for all-spin logic. The research is crucial in pinpointing the implications of the physical limits of novel interconnects at the material, device, circuit, and architecture levels.
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Deodhar, Vinita Vasant. "Throughput-Centric Wave-Pipelined Interconnect Circuits for Gigascale Integration." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7503.

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The central thesis of this research is that VLSI interconnect design strategies should shift from using global wires that can support only a single binary transition during the latency of the line to global wires that can sustain multiple bits traveling simultaneously along the length of the line. It is shown in this thesis that such throughput-centric multibit transmission can be achieved by wave-pipelining the interconnects using repeaters. A holistic analysis of wave-pipelined interconnect circuits, along with the full-custom optimization of these circuits, is performed in this research. With the help of models and methodologies developed in this thesis, the design rules for repeater insertion are crafted to simultaneously optimize performance, power, and area of VLSI global interconnect networks through a simultaneous application of voltage scaling and wire sizing. A qualitative analysis of latency, throughput, signal integrity, power dissipation, and area is performed that compares the results of design optimizations in this work to those of conventional global interconnect circuits. The objective of this thesis is to study the circuit- and system-level opportunities of voltage scaling, wire sizing, and repeater insertion in wave-pipelined global interconnect networks that are implemented in deep submicron technologies.
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Song, Indal. "Multi-Gbit/s CMOS Transimpedance Amplifier with Integrated Photodetector for Optical Interconnects." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4902.

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Trends toward increased integration and miniaturization of optical system components have created pressure to consolidate widely disparate analog and digital functions onto fewer and fewer chips with a goal of eventually built into a single mixed-signal chip. Yet, because of those performance requirements, the frontend circuit has traditionally used III-V compound semiconductor technologies, but the low-level of integration with other digital ICs limits the sustainability of such end products for short-distance applications. On the other hand, their CMOS counter parts, despite having such advantages as low power consumption, high yield that lowers the cost of fabrication, and a higher degree of integration, have not performed well enough to survive in such a noisy environment without sacrificing other important attributes. In this research, a high-speed CMOS preamplifier was designed and fabricated through TSMC 0.18/spl mu/m mixed-signal non-epi CMOS technology, and a 20/spl mu/m diameter InGaAs thin-film Inverted-MSM photodetector with a responsivity of 0.15A/W at a wavelength of 1550/spl mu/m was post-integrated onto the circuit. The circuit has a overall transimpedance gain of 60dB/spl Omega/, and bit-error-rate data and eye-diagram measurement results taken as high as 10Gbit/s are reported in this dissertation.
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Liang, Tao. "Atomic-scale calculations of interfacial structures and their properties in electronic materials." Connect to resource, 2005. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1127163029.

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Thesis (Ph. D.)--Ohio State University, 2005.
Title from first page of PDF file. Document formatted into pages; contains xvi, 136 p.; also includes graphics (some col.). Includes bibliographical references (p. 125-136). Available online via OhioLINK's ETD Center
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Saint-Laurent, Martin. "Modeling and Analysis of High-Frequency Microprocessor Clocking Networks." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7271.

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Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems. The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems.
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Zhang, Xibo. "RF integrated circuit design options : from technology to layout /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20ZHANG.

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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.
Includes bibliographical references (leaves 59-61). Also available in electronic version. Access restricted to campus users.
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La, Pietra Andrew R. "Establishing a bipolar fabrication service for analog circuit realization at the Rochester Institute of Technology /." Online version of thesis, 1991. http://hdl.handle.net/1850/11272.

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Vakili-Amini, Babak. "A Mixed-Signal Low-Noise Sigma-Delta Interface IC for Integrated Sub-Micro-Gravity Capacitive SOI Accelerometers." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10437.

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This dissertation presents the design and development of a mixed-signal low noise second-order integrated circuit (IC) for the open-loop and closed-loop operation of integrated capacitive micro- and nano-gravity accelerometers. The micromechanical accelerometers are fabricated in thick (less than 100 m) silicon-on-insulator (SOI) substrates. The IC provides the 1-bit digital output stream and has the versatility of interfacing sensors with different sensitivities while maintaining minimum power consumption (less than 5 mW) and maximum dynamic range (90 dB). A fully-differential sampled-data scheme is deployed with the ability of low-frequency noise reduction through the use of correlated double sampling (CDS) scheme. In this work, the measured resolution of the closed-loop CMOS-SOI accelerometer system, in the presence of high background accelerations, is in the micro-g (g: gravity) range. In this design, a second-order SC modulator is cascaded with the accelerometer and the front-end amplifier. The accelerometer operates in air and is designed for non-peaking response with a BW-3dB of 500 Hz. A 22 dB improvement in noise and hence dynamic range is achieved with a sampling clock of 40 kHz corresponding to a low oversampling ratio (OSR) of 40. The interface IC consumed a current of 1.5 mA from a supply of 3 V.
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Books on the topic "Interconnects (Integrated circuit technology) Metal oxide semiconductors"

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Shoji, Masakazu. CMOS digital circuit technology. New Jersey: Prentice-Hall International, 1988.

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CMOS digital circuit technology. Englewood Cliffs, N.J: Prentice Hall, 1987.

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R, Holberg Douglas, ed. CMOS analog circuit design. 3rd ed. New York: Oxford University Press, USA, 2011.

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P, Galipeau Denis, ed. Analog BiCMOS design: Practices and pitfalls. Boca Raton, Fla: CRC Press, 2000.

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International, Workshop on Stress-Induced Phenomena in Metallization (10th 2008 Austin Texas). Stress-induced phenomena in metallization: Tenth International Workshop on Stress-Induced Phenomena in Metallization, Austin, Texas, 5-7 November 2008. Melville, N.Y: American Institute of Physics, 2009.

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International, Workshop on Stress-Induced Phenomena in Metallization (9th 2007 Kyoto Japan). Stress-induced phenomena in metallization: Ninth International Workshop on Stress-Induced Phenomena in Metallization, Kyoto, Japan 4 - 6 April 2007. Melville, N.Y: American Institute of Physics, 2007.

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International Workshop on Stress-Induced Phenomena in Metallization (11th 2010 Bad Schandau, Germany). Stress-induced phenomena in metallization: Eleventh International Workshop on Stress-Induced Phenomena in Metallization, Bad Schandau, Germany, 12-14 April 2010. Edited by Zschech Ehrenfried, Ho P. S, and Ogawa Shinʼichi. Melville, N.Y: American Institute of Physics, 2010.

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International Workshop on Stress-Induced Phenomena in Metallization (10th 2008 Austin, Texas). Stress-induced phenomena in metallization: Tenth International Workshop on Stress-Induced Phenomena in Metallization, Austin, Texas, 5-7 November 2008. Edited by Ho P. S, Ogawa Shinichi Dr, and Zschech Ehrenfried. Melville, N.Y: American Institute of Physics, 2009.

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1945-, Brodersen Robert W., ed. Low-power CMOS wireless communications: A wideband CDMA system design. Boston: Kluwer Academic Publishers, 1998.

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Money, Harris David, and Weste Neil H. E, eds. CMOS VLSI design: A circuits and systems perspective. 3rd ed. Boston: Pearson/Addison-Wesley, 2005.

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Conference papers on the topic "Interconnects (Integrated circuit technology) Metal oxide semiconductors"

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Prejean, Seth J., and Joseph Shannon. "Backside Deprocessing of CMOS SOI Devices for Physical Defect and Failure Analysis." In ISTFA 2003. ASM International, 2003. http://dx.doi.org/10.31399/asm.cp.istfa2003p0099.

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Abstract This paper describes improvements in backside deprocessing of CMOS (Complimentary Metal Oxide Semiconductor) SOI (Silicon On Insulator) integrated circuits. The deprocessing techniques described here have been adapted from a previous research publication on backside deprocessing of bulk CMOS integrated circuits [1]. The focus of these improvements was to provide a repeatable and reliable methodology of deprocessing CMOS devices from the backside. We describe a repeatable and efficient technique to deprocess flip chip packaged devices and unpackaged die from the backside. While this technique has been demonstrated on SOI and bulk devices, this paper will focus on the latest SOI technology. The technique is useful for quick and easy access to the transistor level while preserving the metal interconnects for further analysis. It is also useful for deprocessing already thinned or polished die without removing them from the package. Removing a thin die from a package is very difficult and could potentially damage the device. This is especially beneficial when performing physical failure analysis of samples that have been back thinned for the purpose of fault isolation and defect localization techniques such as: LIVA (Laser Induced Voltage Alteration), TIVA (Thermally Induce Voltage Alteration), SDL [2] (Soft Defect Localization), and TRE (Time Resolved Emission) analysis. An important fundamental advantage of deprocessing SOI devices is that the BOX (Buried Oxide) layer acts as a chemical etch stop when etching the backside or bulk silicon. This leaves the transistor active silicon intact for analysis. Further delayering allows for the inspection of the active silicon, gate oxide, silicide, spacers, and poly. After deprocessing the transistor level, the metal layers are still intact and, in most cases, still electrically connected to the outside world. This can provide additional failure analysis opportunities.
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