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MOHAMED, MOHAMED ELSAID ELKHAYAT MOATAZBELLAH. "Interface Circuits for Sensors and Actuators." Doctoral thesis, Università degli studi di Pavia, 2018. http://hdl.handle.net/11571/1214860.
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The research activity described in this Thesis is the result of three different projects, all dealing with interface circuits for sensors and actuators.
1) Capacitive Humidity sensor with temperature controller and heater integrated in CMOS technology
The first project deals with the design of the integrated interface circuit for accurately controlling the temperature of a CMOS capacitive humidity sensor, with the final goal of allowing self-dignostics and self-calibration of the sensor. The humidity sensor used is equipped with an integrated resistor and a temperature sensor which allow changing and measuring the actual sensor temperature.
This activity concentrated initially on the characterization of the humidity sensor provided by Texas Instruments, with the goal of determining the features and the behavior of the device and identifying the specifications of the integrated interface circuit. A measurement setup based on LabView has been developed to allow controlling the temperature of the sensor with an accuracy of 0.005˚C and measuring both the relative humidity and the temperature.
Based on the sensor measurement results we developed a model of the humidity sensor with built-in heater and thermometer in the Cadence framework, to allow the simulation of the complete system. In this sensor model, all the dynamic effects of the heater and relative humidity variation have been considered, to guarantee proper design of the temperature controller integrated circuit. The temperature controller is designed in CMOS technology; it allows a precise adjustment of the temperature with an accuracy better than 0.1˚C. The circuit is based on an analog control loop with PWM modulator.
The circuit has been fabricated using a 0.35µm CMOS technology.
2) Scaltech28 (test structures in CMOS 28nm)
The second project deals with the design of test structures in CMOS 28nm technology, to evaluate it potential for the implementation of sensor interface circuits in future high-energy physics experiments. This work has been carried out in the frame of project, SCALTECH28, which continues the tradition of other similar studies carried out in previous technology generations for achieving optimal results in IC design for various detectors.
This investigation within the selected 28nm technology had to address basic analysis on the single MOS devices (n-MOS and p-MOS), on passive elements like resistors and capacitors, and finally on basic circuits and system building blocks, among the most critical in the sensor interface circuits for different physics experiments.
The main purpose of the work is to investigate the performance of the 28nm technology in terms of signal processing quality, power consumption, and radiation hardness with respect to previous technological generations. An additional target is to experimentally evaluate radiation damage effects on single devices and on full circuits to develop rad-models for simulations. A test chip including elementary device arrays and dedicated read-out circuits has been developed and fully characterized. In particular, a capacitance to frequency converter has been integrated to measure the matching between different capacitors of a programmable array.Experimental measurements showed that the worst-case measurement for the capacitor pair matching is around 0.98% error at 500fF. This value is compliant to the feasibility of A/D converters for sensor readout with resolution better than 10 bits. It is clear from the results that matching performance is comparable to previous technologies, making the 28nm technology eligible for analog signal processing in front-end circuits for physical experiments and related data converters. Samples have been sent to irradiation facility to be exposed to different radiation doses in order to be re-measured and compared in terms of matching and absolute capacitance values with respect to the measurements done before. Based on the results obtained on the basic devices in 28nm technology, we designed a 14-bit 1MS/s extended range incremental A/D converter composed by the cascade of two resettable second-order sigma-delta modulators. The system is designed for reading out detector arrays in particle physics experiments. The two stages, ideally targeting 9 and 6 bits, respectively, are both based on a cascade of integrators with feed-forward (CIFF) architecture to maximize linearity. If necessary, they can work in pipeline to minimize conversion time. When the conversion of each sample by the two stages is completed, a digital recombination filter produces the overall ADC output word with the required resolution (ENOB) of at least 13 bits and a throughput of 1MS/s at the very low over sampling ratio (OSR) of 16. Each stage, implemented with the switched capacitor technique, consists of two integrators followed by a multi-bit quantizer and a capacitive DAC for the feedback. At the start of each conversion cycle, both analog integrators and the digital filter memory elements are reset. The ADC has been sent for fabrication in 28nm technology. Driving circuit for the piezoelectric actuators in ultrasonic washing machines The third project deals with the design of the driving circuit for the piezoelectric actuators in ultrasonic washing machines. The object of this project concerns the study and design of a driving and control system for an ultrasonic cleaning machine, or more commonly called ultrasonic washing machine. These devices are used in several industrial applications. Ultrasonic washing machines consist of a tank filled with a detergent solvent, an electronic interface circuit and one or more piezoelectric transducers, which are mechanically connected to the tank and electrically to the driving circuit. The driving system is connected from the AC mains and consists of three cascaded stages: a rectifier followed by a boost converter, to regulate the power factor and produce an intermediate DC voltage; a buck converter, to adjust the amplitude of the supply voltage for the piezoelectric transducers; an inverter, to drive the actuators with a square wave at their resonance frequency between 30kHz and 40kHz. A flyback converter has also been designed for generating the auxiliary power supply voltage for all the integrated components in the system. A control system based on an Arduino microcontroller has been developed to adjust the frequency of the square wave to the resonance frequency of the transducer, control the output voltage of the buck converter and read data from a current sensor. The system is designed and implemented on a PCB board of 10cm×15cm. The system has been tested on machined with two different tank sizes.
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Peter, Kenneth W. "Integrated interface circuits for switched capacitor sensors." Thesis, University of Edinburgh, 1991. http://hdl.handle.net/1842/15637.
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This thesis reports an investigation into integrated interface circuits for switched capacitor sensors for application in industrial process control instrumentation networks. Three circuits are presented: an absolute capacitance to voltage converter; a capacitance ratio to frequency ratio converter; and a capacitance ratio to voltage ratio converter. Of the circuits, the first two are subject to most thorough investigation with the capacitance ratio to frequency ratio converter being of particular interest. This circuit is based upon a switched capacitor, frequency controlled, negative feedback loop which permits implementation with modest quality analogue components, such as are provided with a standardcell ASIC CMOS process. Initial investigations, accomplished with discrete component implementations of the interface circuits, reveal a significant departure in behaviour from that predicted by firstorder analysis. Switch induced chargefeedthrough is shown to be responsible for the deviation. In addition, parasitic induced jitter and frequency locking are identified as a second source of error. The three interface circuits are implemented as an integrated circuit using the European Silicon Structures (ES2) ASIC CMOS process, with a modification to permit the inclusion of fullcustom designed, chargefeedthrough compensated switches. This implementation exhibits greatly reduced chargefeedthrough, and circuit behaviour is in accordance with a modification to the firstorder analysis that includes the effects of chargefeedthrough. Importantly, no frequency locking and much reduced jitter is observed. Significantly, linear performance is obtained for the capacitance ratio to frequency ratio converter over a 20 to 1 capacitance range, with operation demonstrable down to 5pF sensor capacitance.
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Mason, J. S. B. "Analog Design within High Speed Serial Interface Circuits." Thesis, Oxford Brookes University, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.493433.
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The serial interface is a pervasive component within many electronic products and will be familiar to users of personal computers and modern electronic devices. Over the last twenty years, the serial interface or link has developed from a specialist electronic subsystem for computer and telecommunication systems to an essential building block for modern electronic products ranging from disk storage devices to home entertainment consoles. The high speed serial interface (HSS!) offers fast data transfer at relatively low cost and is now an semiconductor vendors supplying chips to original equipment manufacturers.
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Nerkar, Rajesh. "Self-Timed DRAM Data Interface." PDXScholar, 2013. https://pdxscholar.library.pdx.edu/open_access_etds/1443.
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A DRAM communicates with a processing unit via two interfaces: a data interface and a command interface. In today's DRAMs, also known as synchronous DRAMs (SDRAMs), both interfaces use a clock to communicate with the processing unit. The clock times the communication between the processing unit and the SDRAM on both the data interface and the command interface.
We propose a self-timed DRAM. The self-timed DRAM introduces more flexibility into the DRAM interface by eliminating the clock. The command interface and the data interface each communicate with the processing unit using a handshake protocol rather than a clock.
This thesis presents the data interface between the self-timed DRAM and the processing unit. The proposed data interface is self-timed. The self-timed data interface allows the DRAM to deliver data to or accept data from the processing unit as the processing unit demands rather than on a schedule set from the command interface.
The self-timed data interface is designed using GasP circuits and micropipeline circuits. The design is simulated in 180nm CMOs process technology using hspice. This thesis presents the effects of width mismatch on the self-timed data interface. The micropipeline is slightly faster than the GasP. Also, the thesis compares the self-timed DRAM data interface with synchronous DRAM for the data burst rate.
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Mohammed, A. A. "IGIMCD : An interactive graphical interface for microwave circuit design." Thesis, University of Kent, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.375622.
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Silay, Kanber Mithat. "High Performance Cmos Capacitive Interface Circuits For Mems Gyroscopes." Master's thesis, METU, 2006. http://etd.lib.metu.edu.tr/upload/2/12607518/index.pdf.
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This thesis reports the development and analysis of high performance CMOS readout electronics for increasing the performance of MEMS gyroscopes developed at Middle East Technical University (METU). These readout electronics are based on unity gain buffers implemented with source followers. High impedance node biasing problem present in capacitive interfaces is solved with the implementation of a transistor operating in the subthreshold region.
A generalized fully differential gyroscope model with force feedback electrodes has been developed in order to simulate the capacitive interfaces with the model of the gyroscope. This model is simplified for the single ended gyroscopes fabricated at METU, and simulations of resonance characteristics are done.
Three gyroscope interfaces are designed by considering the problems faced in previous interface architectures. The first design is implemented using a single ended source follower biased with a subthreshold transistor. From the simulations, it is observed that biasing impedances up to several gigaohms can be achieved. The second design is the fully differential version of the first design with the addition of a self biasing scheme. In another interface, the second design is modified with an instrumentation amplifier which is used for fully differential to single ended conversion. All of these interfaces are fabricated in a standard 0.6 µm CMOS process. Fabricated interfaces are characterized by measuring their ac responses, noise response and transient characteristics for a sinusoidal input. It is observed that, biasing impedances up to 60 gigaohms can be obtained with subthreshold transistors. Self biasing architecture eliminates the need for biasing the source of the subthreshold transistor to set the output dc point to 0 V. Single ended SOG gyroscopes are characterized with the single ended capacitive interfaces, and a 45 dB gain improvement is observed with the addition of capacitive interface to the drive mode. Minimum resolvable capacitance change and displacement that can be measured are found to be 58.31 zF and 38.87 Fermi, respectively. The scale factor of the gyroscope is found to be 1.97 mV/(°
/sec) with a nonlinearity of only 0.001% in ±
100 °
/sec measurement range. The bias instability and angle random walk of the gyroscope are determined using Allan variance method as 2.158 °
/&
#8730
hr and 124.7 °
/hr, respectively.
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Honghao, Tang. "A Study on Interface Circuits for Piezoelectric Energy Harvesting." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-144497.
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A piezoelectric energy harvesting (PEH) system can harvest electrical energy from ambient vibration energy. In a PEH system, the interface rectifier circuit is critical because it converts AC from the output of piezoelectric harvester to DC that can power the load. Hence, improving the efficiency of the interface circuit can directly increase the efficiency of the entire PEH system; consequently, more power can be harvested. Commonly used interface circuits in PEH systems, such as full-bridge and voltage- doubler rectifiers,lead to relatively simple circuit implementations but they show serious limitations in energy-harvesting efficiency. Several innovative solutions have been reported to improve the efficiency of the interface rectifiers, such as ‘switch-only’ and ‘bias-flip’ techniques [7]. Such solutions utilize additional switches or switched inductors to speed up and even quickly reverse (flip) the voltage on the rectifier input to the desired voltage-level and condition for energy transfer, ultimately improving the overall efficiency of the energy harvesting. However, such techniques rely on accurate timing and synchronization of the pulsed switches every time the current produced by the piezoelectric harvester changes polarity. This thesis studies and investigates the impact of the non-ideal switching effects on the energy efficiency of the switch-only and bias-flip interface rectifiers in a PEH system, by theoretical derivation and experimental simulation.
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MOISELLO, ELISABETTA. "Integrated Interface Circuits for MEMS Contact-less Temperature Sensors." Doctoral thesis, Università degli studi di Pavia, 2020. http://hdl.handle.net/11571/1370177.
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Thermal sensors, exploiting the relation between the thermal radiation emitted by an object and its temperature, as expressed by the Stefan-Boltzmann law, allow realizing contact-less temperature measurements, required in a wide range of applications, ranging from fever measurements to presence detection for security and climate control systems.
With the advent of smart homes and Internet of Things (IoT) and the wide spreading of mobile and wearable devices, the need for low-cost low-power thermal sensors has arisen, therefore moving the focus of the research away from standard bolometers and pyroelectric detectors and towards uncooled infrared (IR) sensors solutions that can be easily integrated. Bolometers and pyroelectric detectors, which are the main types of thermal sensors found nowadays on the market, in fact, do not comply with the low-cost and easy integration specifications.
Integration of thermal sensors is possible through Micro-Electro Mechanical Systems (MEMS) technology, which allows combining on the same substrate or chip both electrical and mechanical structures with dimensions in the micro-meter range, thus providing structures with high thermal isolation and low thermal mass. The micromachining processes that are required to thermally isolate the sensing element from the substrate are versatile and include anisotropic wet etching, dry and wet etching, electrochemical etch stop, or the use of silicon-on-insulator (SOI).
In this scenario, STMicroelectronics has fabricated two different novel thermal sensors, which fulfill the low-cost low-power specifications for smart homes, IoT and mobile and wearable devices, while also being compatible with CMOS processes and thus easily integrated: a polysilicon thermopile and a micromachined CMOS transistor, from now on referred to as TMOS.
During my Ph.D. activity I was involved in a cooperation between the STMicroelectronics Analog MEMS and Sensors R&D group and the University of Pavia, that led to the design of two readout circuits specifically tailored on the sensors characteristics, one for the thermopile sensor and one for the TMOS (developed by the Technion-Israel Institute of Technology), which were integrated in two test-chip prototypes and thoroughly characterized through measurements as stand-alone devices and as a system with the sensor they were designed for.Thermal sensors, exploiting the relation between the thermal radiation emitted by an object and its temperature, as expressed by the Stefan-Boltzmann law, allow realizing contact-less temperature measurements, required in a wide range of applications, ranging from fever measurements to presence detection for security and climate control systems. With the advent of smart homes and Internet of Things (IoT) and the wide spreading of mobile and wearable devices, the need for low-cost low-power thermal sensors has arisen, therefore moving the focus of the research away from standard bolometers and pyroelectric detectors and towards uncooled infrared (IR) sensors solutions that can be easily integrated. Bolometers and pyroelectric detectors, which are the main types of thermal sensors found nowadays on the market, in fact, do not comply with the low-cost and easy integration specifications. Integration of thermal sensors is possible through Micro-Electro Mechanical Systems (MEMS) technology, which allows combining on the same substrate or chip both electrical and mechanical structures with dimensions in the micro-meter range, thus providing structures with high thermal isolation and low thermal mass. The micromachining processes that are required to thermally isolate the sensing element from the substrate are versatile and include anisotropic wet etching, dry and wet etching, electrochemical etch stop, or the use of silicon-on-insulator (SOI). In this scenario, STMicroelectronics has fabricated two different novel thermal sensors, which fulfill the low-cost low-power specifications for smart homes, IoT and mobile and wearable devices, while also being compatible with CMOS processes and thus easily integrated: a polysilicon thermopile and a micromachined CMOS transistor, from now on referred to as TMOS. During my Ph.D. activity I was involved in a cooperation between the STMicroelectronics Analog MEMS and Sensors R&D group and the University of Pavia, that led to the design of two readout circuits specifically tailored on the sensors characteristics, one for the thermopile sensor and one for the TMOS (developed by the Technion-Israel Institute of Technology), which were integrated in two test-chip prototypes and thoroughly characterized through measurements as stand-alone devices and as a system with the sensor they were designed for.
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Johnson, James Robert. "Interface design for an audio based information retrieval system." Master's thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-05042010-020011/.
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Chan, Cheung. "Out of plane screening and dipolar interaction in heterostructures /." View abstract or full-text, 2009. http://library.ust.hk/cgi/db/thesis.pl?PHYS%202009%20CHAN.
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Zhang, Tan Tan. "Nano-watt class CMOS interface circuits for wireless sensor nodes." Thesis, University of Macau, 2018. http://umaclib3.umac.mo/record=b3952097.
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Chen, Wenjin. "Investigation of interface property between GaMnAs and organic material /." View abstract or full-text, 2009. http://library.ust.hk/cgi/db/thesis.pl?PHYS%202009%20CHENW.
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Wei, Jie. "Circuits de récupération d’énergie très basse puissance pour transducteurs à capacité variable." Thesis, Université Paris-Saclay (ComUE), 2017. http://www.theses.fr/2017SACLS220.
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La récupération d'énergie mécanique de vibration à l’aide de transducteurs à capacité variable mène à l’étude de systèmes non linéaires complexes, mais présente des perspectives applicatives très prometteuses. Notre travail a porté sur l’étude d’une nouvelle famille de circuits d'interface pour transducteurs capacitifs. Entre autres avantages, ces circuits sont réalisables avec des rendements élevés à très basse puissance, typiquement dès quelques dizaines de nano-watts de puissance moyenne, ce qui les distingue des solutions présentées dans de l’état de l’art. De plus, Les circuits étudiés dans cette thèse ne contiennent aucun composant magnétique, ce qui constitue un atout considérable en termes de miniaturisation et d’intégration et permet eu outre la compatibilité avec l’imagerie par résonance magnétique. Les différentes structures qui constituent la famille de circuits proposés permettent de répondre à différentes contraintes imposées par le transducteur capacitif, en particulier le rapport des capacités maximale et minimale Cmax/Cmin. A partir d’une tension de sortie donnée, la tension appliquée sur le transducteur capacitif peut être modifiée en utilisant différents circuits ou en utilisant un circuit unique dont la topologie est modifiée à l’aide d’un interrupteur électronique. Les modèles théoriques développés prennent en compte le couplage électromécanique du transducteur de manière à décrire le comportement global des systèmes étudiés. Les circuits étudiés ont été validés expérimentalement avec deux transducteurs capacitifs de structure différente. En pratique, le rendement de ces circuits est proche de 80% pour des puissances converties aussi basses que la centaine de nano wattsThe mechanic vibration energy harvesting using variable capacitance transducers leads to the study of complex nonlinear systems but has very promising application perspectives. Our work focused on the study of a new family of interface circuits for capacitive transducers. Among all the advantages, these circuits are achievable with high efficiencies at very low power, typically a few tens of nanowatts average power, which distinguishes them from the solutions presented in the state of the art. Moreover, the circuits studied in this thesis do not contain any magnetic components, which is a considerable asset in terms of miniaturization and integration and also allows compatibility with magnetic resonance imaging. The various structures which constitute the family of circuits proposed make it possible to satisfy various constraints imposed by the capacitive transducer, in particular, the ratio of the maximum and minimum capacities Cmax / Cmin. For a given output voltage, the voltage applied to the capacitive transducer can be varied by using different circuits or by using a single circuit whose topology is modified by the operation of an electronic switch. In order to describe the overall behavior of the studied systems, the electromechanical coupling of the transducer is taken into account in the developed theoretical models. The studied circuits have been validated experimentally with two capacitive transducers of different structure. In practice, the output of these circuits is close to 80% for converted powers as low as the hundred nanowatts
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So, Biu 1959. "THE METHODOLOGY AND IMPLEMENTATION OF RELAXATION METHOD TO INVESTIGATE ELECTRO-THERMAL INTERACTIONS IN SOLID-STATE INTEGRATED CIRCUITS." Thesis, The University of Arizona, 1987. http://hdl.handle.net/10150/276384.
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Beikahmadi, Mohammad. "Analysis and design of analog interface circuits for capacitive detector readout systems." Thesis, University of British Columbia, 2017. http://hdl.handle.net/2429/62490.
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The full abstract for this thesis is available in the body of the thesis, and will be available when the embargo expires.Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
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Mayberry, Curtis Lee. "Interface circuits for readout and control of a micro-hemispherical resonating gyroscope." Thesis, Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/53116.
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Gyroscopes are inertial sensors that measure the rate or angle of rotation. One of the most promising technologies for reaching a high-performance MEMS gyroscope has been development of the micro-hemispherical shell resonator. (μHSR) This thesis presents the electronic control and read-out interface that has been developed to turn the μHSR into a fully functional micro-hemispherical resonating gyroscope (μHRG) capable of measuring the rate of rotation. First, the μHSR was characterized, which both enabled the design of the interface and led to new insights into the linearity and feed-through characteristics of the μHSR. Then a detailed analysis of the rate mode interface including calculations and simulations was performed. This interface was then implemented on custom printed circuit boards for both the analog front-end and analog back-end, along with a custom on-board vacuum chamber and chassis to house the μHSR and interface electronics. Finally the performance of the rate mode gyroscope interface was characterized, showing a linear scale factor of 8.57 mv/deg/s, an angle random walk (ARW) of 34 deg/sqrt(hr) and a bias instability of 330 deg/hr.
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Pickles, Neil S. (Neil Stuart) Carleton University Dissertation Engineering Electrical. "Design, modeling, and optimization of ECL interface circuits for BiCMOS integrated systems." Ottawa, 1993.
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Zhou, Yangyang. "Characterization of organic semiconductor and ferromagnetic half-metallic oxide interface /." View abstract or full-text, 2009. http://library.ust.hk/cgi/db/thesis.pl?PHYS%202009%20ZHOU.
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Su, Jin Jyh. "Integrated low-power interfaces for impedimetric chemical sensors." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/54288.
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This thesis presents two interface circuits for impedimetric chemical sensors: one for passive chemical sensors and the other for ChemFETs. Both interfaces were fabricated in 0.35μm BiCMOS technology and provide the same output data rate of 1Hz.
The interface for passive impedimetric sensors is reconfigurable for performing either resistance or capacitance measurements and provides a fully digital output with less than 81.8μW power consumption at VDD = 2.5V. The interface features a 176dB resistance dynamic range (31.6Ω-200MΩ, <±0.8% nonlinearity, and >40dB SNR) realized with only two sub-ranges to minimize calibration efforts and a 102dB capacitance dynamic range (0.8-1000pF, <±0.2% nonlinearity, and >40dB SNR).
The ChemFET interface is a highly versatile system that can generate a wide range of bias voltages (VG up to 9.74V and VD up to 16.3V depending on the measurement modes) and perform either constant voltage or constant current mode measurement. At maximum rated output (VG = 9.74V, VD = 16.3V, and IDS = 15μA), the interface consumes only 2.02μW at VDD = 3.3V and provides analog readout noise levels of 0.0476μARMS at 10μA and 0.503mVRMS for IDS and VT, respectively.
Besides attempting versatile system architectures, detailed noise and efficiency analysis were performed for the passive sensor interface and the ChemFET interface, respectively. The noise analysis suggests that different types of noise (correlated or uncorrelated) dominate the noise performance in different measurement ranges and, thus, noise suppression techniques, such as chopper stabilization, correlated double sampling (CDS), and oversampling/averaging, are applied to adequate parts of the interface system. The efficiency analysis of the boost capacitor charger in the ChemFET interface concludes that applying a moderate pulsewidth (200-300ns) to drive the boost converter yields the best efficiencies for charging a capacitor.
Compared to interfaces described in the literature, the proposed interface for passive sensors achieves better versatility and wide dynamic range with less number of sub-ranges and power consumption. The proposed interface for ChemFETs achieves wider voltage supply range at very low power level.
In-house fabricated chemical sensors, including passive chemical sensors and ChemFETs, were interfaced with the developed circuits and gas-phase chemical measurements with the systems were demonstrated. The novel passive chemical sensor tested in this thesis employs a multi-functional design, which can be configured into either a chemoresistor or a chemocapacitor; the tested ChemFET employs a bottom-gate TFT structure to allow the semiconducting film to interact with the analytes.
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Zheng, Wei. "Low-power low-noise DC-coupled sensor amplifier IC." Pullman, Wash. : Washington State University, 2008. http://www.dissertations.wsu.edu/Thesis/Summer2008/w_zheng_070908.pdf.
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Thesis (M.S. in electrical engineering)--Washington State University, August 2008.Title from PDF title page (viewed on Mar. 11, 2009). "School of Electrical Engineering and Computer Science." Includes bibliographical references (p. 48-49).
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Dhar, Romit. "Growth and optimization of piezoelectric single crystal transducers for energy harvesting from acoustic sources." Pullman, Wash. : Washington State University, 2009. http://www.dissertations.wsu.edu/Dissertations/Spring2009/R_Dhar_031309.pdf.
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Laotaveerungrueng, Noppasit. "A High-Voltage, High-Current Multi-Channel Arbitrary Waveform Generator ASIC for Neural Interface and MEMS Applications." Case Western Reserve University School of Graduate Studies / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=case1291675462.
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Mao, Yu-lung. "Novel high-K gate dielectric engineering and thermal stability of critical interface /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
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Gabrys, Ann M. "Interface state characterization techniques for MOS capacitors incorporating ultra-thin dielectric films /." Diss., ON-CAMPUS Access For University of Minnesota, Twin Cities Click on "Connect to Digital Dissertations", 2001. http://www.lib.umn.edu/articles/proquest.phtml.
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Thesis (M.S.)--University of Minnesota, 2001."Accompanying CD-ROM contains Excel spreadsheets and Mathematica notebooks that contain data and templates" for further investigation.--P. 68. Includes bibliographical references (leaves 70-71). Also available on the World Wide Web as a PDF file.
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Levi, Meir H. "Intelligent reflexive interfaces and their applications." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=65931.
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Subramanian, Shankar. "CAD oriented database for integrated circuit layouts." Thesis, Virginia Polytechnic Institute and State University, 1986. http://hdl.handle.net/10919/94475.
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Modern integrated circuit layouts are so complex that databases often have to deal with a million or more geometric objects. For circuit and layout designers to be able to cope with such complex circuits, we (tool designers) must provide more and more support in such areas as design rule checking, circuit extraction, compaction, and routing. To support these tools the database must provide fast geometric operations for region queries, neighbor finding, and location of empty space. Furthermore, in order to build practical interactive systems the database must also permit fast incremental modifications. This thesis describes the design of a database that satisfies the above requirements. The database, based on a data structure called corner stitching, consists of all data structure definitions and operations, the rule based system, hierarchical structures, database I/O, and interface for the CAD tool designer. The implementation techniques for a layout editor are also described. The most important feature of the database is that the complexity of key operations for neighbor finding, region queries, and location of empty space depend on local factors and are independent of overall layout size. The above mentioned features should make it possible to design tools that operate incrementally.M.S.
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Inoue, Masumi, Takashi Nishitani, Akira Fujimaki, Takahiro Yamada, Koji Sawaki, Iwao Kawayama, and Masayoshi Tonouchi. "Study on the optical input interface for Nb single-flux-quantum logic circuits." American Institute of Physics, 2006. http://hdl.handle.net/2237/8767.
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Leicht, Joachim [Verfasser], and Yiannos [Akademischer Betreuer] Manoli. "CMOS circuits for electromagnetic vibration energy harvesters : : system modeling, interface design and implementation." Freiburg : Universität, 2019. http://d-nb.info/1193423090/34.
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Wilson, Denise M. "Analog VLSI architecture for chemical sensing microsystems." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/13322.
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Dalal, Milap. "Low noise, low power interface circuits and systems for high frequency resonant micro-gyroscopes." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/44861.
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Today's state-of-the-art rate vibratory gyroscopes use a large proof mass that vibrates at a low resonance frequency (3-30 kHz), a condition that creates a performance tradeoff in which the gyroscope can either offer large bandwidth or high resolution, but not both. This tradeoff led to the development of the capacitive bulk acoustic wave (BAW) silicon disk gyroscope, a new class of micromachined rate vibratory gyroscopes operating in the frequency range of 1-10MHz with high device bandwidth and shock/vibration tolerance. By scaling the frequency, BAW gyroscopes can provide low mechanical noise without sacrificing the high bandwidth performance needed for most commercial applications. The drive loop of the BAW gyroscope can also be exploited as a timing device that can be integrated in existing commercial systems to provide competitive clock performance to the state-of-the-art using less area and power.
This dissertation discusses the design and implementation of a CMOS ASIC architecture that interfaces with a high-Q, wide-bandwidth BAW gyroscope and the challenges associated with optimizing the noise performance to achieve navigation-grade levels of sensitivity as the frequency is scaled into the MHz regime. Mathematical models are derived to describe the operation of the sensor and are used to generate equivalent electrical circuit models of the gyroscope. A design strategy is then outlined for the ASIC to optimize the drive loop and sense channel for power and noise, and steps toward reducing this noise as the system is pushed to navigation-grade performance are presented that maintain optimum system power consumption.
After analyzing the BAW gyroscope and identifying a strategy for developing the drive and sense interface circuitry, a complete fully-differential ASIC is designed in 0.18μm CMOS to interface with a bulk acoustic wave (BAW) disk gyroscope. As an oscillator, the gyroscope provides an uncompensated clock signal at ~9.64 MHz with a temperature sensitivity of -27 ppm/°C and phase noise of -104 dBc at 1 kHz from carrier. When the complete ASIC is interfaced with the gyroscope, the sensor shows a measured rate sensitivity of 1.15 mV/o/s with an open-loop bandwidth of 280 Hz and a bias instability of 0.095 o/s, suitable for the rate-grade performance commonly required for commercial and consumer electronics applications. The system is recorded to have a total power of 1.6 mW and a total area of 0.64 mm2.
Following the design of the interface ASIC, this dissertation investigates in further detail the requirements for designing and optimizing charge pumps for capacitive MEMS devices. Basic charge pump design is outlined, followed by an overview of techniques that can be used to generate larger polarization voltages from the ASIC. Lastly, an alternate measurement technique for measuring the rotation rate of the gyroscope is discussed. This technique is based on the phase-shift modulation of the gyroscope output signal when the device is driven with two orthogonal signal inputs and can be easily modified to provide either linear scale factor measurement or a linear calibration curve that can be used to track and adjust the variation of the sensor scale factor over time.
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Xia, Hongxia Carleton University Dissertation Engineering Electronics. "Transistor placement algorithm for automatic layout synthesis of CMOS/BiCMOS logic and interface circuits." Ottawa, 1993.
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Krishnamurthy, Hari. "A low noise low power dc-coupled sensor amplifier with offset cancellation." Pullman, Wash. : Washington State University, 2009. http://www.dissertations.wsu.edu/Thesis/Fall2009/h_krishnamurthy_111909.pdf.
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Thesis (M.S. in electrical engineering)--Washington State University, December 2009.Title from PDF title page (viewed on Jan. 15, 2010). "School of Electrical Engineering and Computer Science." Includes bibliographical references (p. 52-53).
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Zhu, Xingguang Williams John R. "Alternative growth and interface passivation techniques for SiO2 on 4H-SiC." Auburn, Ala, 2008. http://hdl.handle.net/10415/1494.
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Finn, Steven Ernest. "Interface circuit designs for extreme environments using SiGe BiCMOS technology." Thesis, Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/22679.
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SiGe BiCMOS technology has many advantageous properties that, when leveraged, enable circuit design for extreme environments. This work will focus on designs targeted for space system avioinics platforms under the NASA ETDP program. The program specifications include operation under temperatures ranging from -180 C to +125 C and with radiation tolerance up to total ionizing dose of 100 krad with built-in single-event latch-up tolerance. To the author's knowledge, this work presents the first design and measurement of a wide temperature range enabled, radiation tolerant as built, RS-485 wireline transceiver in SiGe BiCMOS technology. This work also includes design and testing of a charge amplification channel front-end intended to act as the interface between a piezoelectric sensor and an ADC. An additional feature is the design and testing of a 50 Ohm output buffer utilized for testing of components in a lab setting.
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Nanard, Jocelyne. "La Manipulation directe en interface homme-machine." Montpellier 2, 1990. http://www.theses.fr/1990MON20305.
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Cette etude analyse le concept de manipulation directe en interface homme-machine et propose un cadre conceptuel et methologique pour la conception d'interfaces a manipulation directe. Ce cadre permet d'integrer les theories et techniques d'informatique, de psychologie cognitive et d'ergonomie dans le but de concevoir des interfaces adaptees aux utilisateurs. Le point de depart est un schema cognitif, inspire de la theorie de l'action de norman, qui definit fonctionnellement l'interface. Il conduit a la proposition d'un modele d'architecture. La fonction de conversion de formalismes de l'interface est rendue operationnelle grace a un mecanisme de specifications d'interfaces base sur la notion de vue interactive. Le cadre ainsi pose ser de base pour analyser le concept de manipulation directe. Ce concept est precise en introduisant les notions ded correspondance semantique, correspondance articulatoire, suggestivite articulatoire, facilite operatoire, reversibilite, reversibilite, explorabilite, et en explicitant leur role pour concevoir des interfaces adaptees aux utilisateurs. Des principes methodiques s'appuyant sur les differents modeles et notions degagees sont enonces et definissent un referentiel pour l'application des regles ergonomiques de detail. La realisation des systemes macweb et h-station montre l'interet du cadre conceptuel et methodologique propose pour concevoir et produire des interfaces a manipulation directe. Elle illustre sa mise en uvre grace au mecanisme de specification de vues interatives
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Norouz, Pour Shirazi Arashk. "Advanced interface systems for readout, control, and self-calibration of MEMS resonant gyroscopes." Diss., Georgia Institute of Technology, 2016. http://hdl.handle.net/1853/54936.
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MEMS gyroscopes have become an essential component in consumer, industrial and automotive applications, owing to their small form factor and low production cost. However, their poor stability, also known as drift, has hindered their penetration into high-end tactical and navigation applications, where highly stable bias and scale factor are required over long period of time to avoid significant positioning error. Improving the long-term stability of MEMS gyroscopes has created new challenges in both the physical sensor design and fabrication, as well as the system architecture used for interfacing with the physical sensor. The objective of this research is to develop interface circuits and systems for in-situ control and self-calibration of MEMS resonators and resonant gyroscopes to enhance the stability of bias and scale factor without the need for any mechanical rotary stage, or expensive bulky lab characterization equipment. The self-calibration techniques developed in this work provide 1-2 orders of magnitude
improvement in the drift of bias and scale factor of a resonant gyroscope over temperature and time.
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Poivey, Christian. "Methodes d'optimisation pour la cao de circuits integres : interface avec le simulateur electrique spice-pac : applications." Clermont-Ferrand 2, 1987. http://www.theses.fr/1987CLF2D203.
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La conception des circuits integres consiste a determiner des valeurs acceptables des parametres afin de satisfaire certains criteres de fonctionnement du circuit donne par sa topologie. Le probleme est reformule en un probleme non lineaire a plusieurs dimensions avec contraisntes. Les fonctions a minimiser et les contraintes dependent implicitement des parametres d'optimisation par les equations du circuit, ce qui exige une simulation complete pour obtenir l'evaluation de la fonction. Les methodes du gradient et hessienne ne conviennent pas. La methode du simplex de nelder et head adjointe a une methode de recherche globale des meilleurs points d'attraction a ete retenue. Toutefois, la dimension n doit rester inferieure a 10. On tente de resoudre le probleme d'un grand nombre de variables en le fractionnant: au lieu d'agir sur la totalite des variables, on effectue des minimisations successives sur des sous-ensembles. Des essais sur des fonctions tests comportant jusqu'a 100 variables sont satisfaisants. On obtient la proportionnalite du temps de calcul et du nombre des variables. Ces methodes ont ete interfacees avec le simulateur electrique spice-pac et appliquees a la caracterisation de modeles de transistors et a l'optimisation de circuits
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Rahim, Md Sayed Kaysar Jaeger Richard C. Suhling J. C. "Die stress characterization and interface delamination study in flip chip on laminate assemblies." Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Summer/doctoral/RAHIM_MD_37.pdf.
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Chen, Chung-ping. "Performance-driven interconnect optimization /." Digital version accessible at:, 1998. http://wwwlib.umi.com/cr/utexas/main.
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Kepenek, Reha. "Capacitive Cmos Readout Circuits For High Performance Mems Accelerometers." Master's thesis, METU, 2008. http://etd.lib.metu.edu.tr/upload/12609310/index.pdf.
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This thesis presents the development of high resolution, wide dynamic range sigma-delta type readout circuits for capacitive MEMS accelerometers. Designed readout circuit employs fully differential closed loop structure with digital output, achieving high oversampling ratio and high resolution. The simulations of the readout circuit together with the accelerometer sensor are performed using the models constructed in Cadence and Matlab Simulink environments. The simulations verified the stability and proper operation of the accelerometer system. The sigma-delta readout circuit is implemented using XFab 0.6 µm CMOS process. Readout circuit is combined with Silicon-On-Glass (SOG) and Dissolved Wafer Process (DWP) accelerometers. Both open loop and closed loop tests of the accelerometer system are performed. Open loop test results showed high sensitivity up to 8.1 V/g and low noise level of 4.8 µ
g/&
#61654
Hz. Closed loop circuit is implemented on a PCB together with the external filtering and decimation electronics, providing 16-bit digital output at 800 Hz sampling rate. High acceleration tests showed ±
18.5 g of linear acceleration range with high linearity, using DWP accelerometers. The noise tests in closed loop mode are performed using Allan variance technique, by acquiring the digital data. Allan variance tests provided 86 µ
g/&
#61654
Hz of noise level and 74 µ
g of bias drift. Temperature sensitivity tests of the readout circuit in closed loop mode is also performed, which resulted in 44 mg/º
C of temperature dependency. Two different types of new adaptive sigma-delta readout circuits are designed in order to improve the resolution of the systems by higher frequency operation. The two circuits both change the acceleration range of operation of the system, according to the level of acceleration. One of the adaptive circuits uses variation of feedback time, while the other circuit uses multi-bit feedback method. The simulation results showed micro-g level noise in closed loop mode without the addition of the mechanical noise of the sensor.
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Simlissi, Essossinam. "Modeling of delamination and interface strength in printed circuit boards." Electronic Thesis or Diss., Université de Lorraine, 2019. http://www.theses.fr/2019LORR0326.
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Dans cette thèse, la résistance des interfaces dans les circuits imprimés (PCB) est étudiée. Un PCB est un élément passif permettant d’interconnecter des composants électroniques soudés sur les couches externes. Un PCB est un assemblage multicouche, multi-matériaux fait de composites tissés et de feuillards de cuivre. Le cuivre joue un rôle majeur dans les circuits imprimés car il est le support de l’information électrique. Pendant son cycle de vie, le PCB subit un grand nombre de cycles thermiques pouvant entraîner la rupture des fûts de cuivre. Par ailleurs, l’utilisation de certaines combinaisons de matériaux peut entraîner du délaminage ce qui limite la durée de vie du PCB. La mesure de la résistance de l'interface entre la couche de cuivre et le substrat composite est alors très importante. Pour l’industrie du PCB, le test de pelage reste la méthode courante pour mesurer les propriétés de l’interface entre deux matériaux. Cette thèse comporte trois parties. Premièrement des tests de pelage sont réalisés pour différents angles de pelage et à température ambiante. Les échantillons étudiés et testés sont constitués d'un feuillard de cuivre assemblé à un substrat composite tissé. Lors de l’essai, la décohésion au niveau de l’interface est bien observée. Par ailleurs, la force de pelage et le rayon de courbure du film de cuivre sont mesurés en régime stationnaire. En parallèle, une analyse théorique du test de pelage est conduite pour des matériaux élasto-plastiques. Le chemin de déformation du film de cuivre lors du test de pelage est assimilé à un mode de flexion – flexion inverse. Nous proposons une analyse théorique de ce trajet de chargement pour un matériau élasto-plastique obéissant à une loi d’écrouissage de type Voce. Enfin, des simulations de pelage par éléments finis sont effectuées pour différents angles. Le comportement du cuivre identifié à l’aide d’un essai de traction est considéré comme élasto-plastique. Une loi d’écrouissage de type Voce est utilisée. Le substrat est supposé élastique orthotrope. L’interface est modélisée par des éléments cohésifs en utilisant une loi de type traction séparation bilinéaire. Les résultats des simulations (EF) sont comparés aux données expérimentales de la thèse. On observe un bon accord au niveau à la fois de la force de pelage mais aussi du rayon de courbure. Au final, ce travail de thèse permet de proposer un dialogue essai / simulations numériques pour définir précisément l’énergie de rupture de l’interfaceIn this thesis, the identification of the interface strength in Printed Circuit Boards (PCBs) is assessed. A PCB is a passive component, which allows to interconnect electronic components soldered on the outer layers in order to realize a complex electronic system. It is a multiple layer assembly made of woven composite and copper foil. Copper plays a major role in Printed Circuit Boards (PCBs) since it is the carrier of the electrical information. During its lifetime, the PCB undergoes a large number of thermal cycles, which can lead to the failure of copper path. In addition, it has been detected that the use of certain combinations of based materials leads to delamination, which limits the PCB service-life. The measurement of interface strength between copper layer and composite substrate is critical and the usual method for measuring the interface properties in PCB industry is the peel test. The PhD is divided in three main parts. In the first experimental part, peel tests at various peel angles are performed using specimens, which consist of a copper foil bonded on a woven composite substrate. Interface separation between the copper film and the composite substrate is observed. During the test, the peel force per unit width and the copper film radius at steady state are measured. Next, a theoretical analysis of the peel test for an elastic-plastic material is proposed. A precise definition of the work done by bending plasticity for a particular class of material response is established. Indeed, we have extended previous works of the literature by considering that the plastic hardening behavior of the film is modeled by a Voce type law. Finally, finite element (FE) simulations of peeling are conducted at various peel angles by considering that the copper material response is elastic-plastic. The isotropic hardening is identified based on uni-axial tensile tests. The woven composite is assumed to remain elastic with an orthotropic response. The interface is modeled by cohesive elements using a bilinear traction separation law. FE results are compared to experimental data. It is shown that the peel force and the film curvature are predicted accurately, for a large range of peel angles. 125 Therefore, from the dialog between finite element calculations and experiments, the interface fracture energy is obtained
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Rachamadugu, Arun. "Digital implementation of high speed pulse shaping filters and address based serial peripheral interface design." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26603.
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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Laskar, Joy; Committee Member: Anderson, David; Committee Member: Cressler, John. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Wienke, James Patrick. "The impact of interface states on sub-threshold leakage and power management in CMOS devices and circuits." College Park, Md.: University of Maryland, 2007. http://hdl.handle.net/1903/7235.
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Thesis (M.S.) -- University of Maryland, College Park, 2007.Thesis research directed by: Dept. of Electrical and Computer Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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DOMIENIKAN, CLAUDIO. "interface eletronica para aquisicao de 12 espectros de coincidencias gama-gama atrasadas." reponame:Repositório Institucional do IPEN, 2001. http://repositorio.ipen.br:8080/xmlui/handle/123456789/10889.
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Dissertacao (Mestrado)
IPEN/D
Instituto de Pesquisas Energeticas e Nucleares - IPEN/CNEN-SP
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Vakili-Amini, Babak. "A Mixed-Signal Low-Noise Sigma-Delta Interface IC for Integrated Sub-Micro-Gravity Capacitive SOI Accelerometers." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10437.
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This dissertation presents the design and development of a mixed-signal low noise second-order integrated circuit (IC) for the open-loop and closed-loop operation of integrated capacitive micro- and nano-gravity accelerometers. The micromechanical accelerometers are fabricated in thick (less than 100 m) silicon-on-insulator (SOI) substrates. The IC provides the 1-bit digital output stream and has the versatility of interfacing sensors with different sensitivities while maintaining minimum power consumption (less than 5 mW) and maximum dynamic range (90 dB). A fully-differential sampled-data scheme is deployed with the ability of low-frequency noise reduction through the use of correlated double sampling (CDS) scheme. In this work, the measured resolution of the closed-loop CMOS-SOI accelerometer system, in the presence of high background accelerations, is in the micro-g (g: gravity) range. In this design, a second-order SC modulator is cascaded with the accelerometer and the front-end amplifier. The accelerometer operates in air and is designed for non-peaking response with a BW-3dB of 500 Hz. A 22 dB improvement in noise and hence dynamic range is achieved with a sampling clock of 40 kHz corresponding to a low oversampling ratio (OSR) of 40. The interface IC consumed a current of 1.5 mA from a supply of 3 V.
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Mustapha, Lateef Abimbola, and Lateef Abimbola Mustapha. "Thermo-Mechanical Characterization and Interfacial Thermal Resistance Studies of Chemically Modified Carbon Nanotube Thermal Interface Material - Experimental and Mechanistic Approaches." Diss., The University of Arizona, 2017. http://hdl.handle.net/10150/625379.
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Effective application of thermal interface materials (TIM) sandwiched between silicon and a heat spreader in a microelectronic package for improved heat dissipation is studied through thermal and mechanical characterization of high thermally conductive carbon nanotubes (CNTs) integrated into eutectic gallium indium liquid metal (LM) wetting matrix. Thermal conductivity data from Infrared microscopy tool reveals the dependence of experimental factors such as matrix types, TIM contacting interfaces, orientation of CNTs and wetting of CNTs in the matrix on the thermal behavior of TIM composite.
Observed generalized trend on LM-CNT TIM shows progressive decrease in effective thermal conductivity with increasing CNT volume fractions. Further thermal characterizations LM-CNT TIM however show over 2x increase in effective thermal conductivity over conventional polymer TIMs (i.e. TIM from silicone oil matrix) but fails to meet 10x improvement expected.
Poor wetting of CNT with LM matrix is hypothesized to hinder thermal improvement of LM-CNT TIM composite. Thus, wetting enhancement technique through electro-wetting and liquid crystal (LC) based matrix proposed to enhance CNT-CNT contact in LM-CNT TIM results in thermal conductivity improvement of 40 to 50% with introduction of voltage gradient of 2 to 24 volts on LM-CNT TIM sample with 0.1 to 1 percent CNT volume fractions over non voltage LM-CNT TIM test samples.
Key findings through this study show that voltage tests on LC- CNT TIM can cause increased CNT-CNT networks resulting in 5x increase in thermal conductivity over non voltage LC-CNT TIM and over 2x improvement over silicone-CNT TIMs. Validation of LM wetting of CNT hypothesis further shows that wetting and interface adhesion mechanisms are not the only factors required to improve thermal performance of LM-CNT TIM. Anisotropic characteristic of thermal conductivity of randomly dispersed CNTs is a major factor causing lower thermal performance of LM-CNTs TIM composite. Other factors resulting in LM-CNT TIM decreasing thermal conductivity with increasing CNT loading are (i) Lack of CNT-CNT network due to large difference in surface tension and mass density between CNTs and LM in TIM composite (ii) Structural stability of MWCNT and small MFP of phonons in ~5um MWCNTs compared to the system resulted in phonon scattering with reduced heat flow (iii) CNT percolation threshold limit not reached owing to thermal shielding due to CNT tube interfacial thermal resistance.
While mixture analytical models employed are able to predict thermal behaviors consistent with CNT-CNT network and CNT- polymer matrix contact phenomenon, these models are not equipped to predict thermo-chemical attributes of CNTs in LM-CNT TIM. Extent of LM-CNT wetting and LM-solid surface interfacial contact impacts on interfacial thermal resistance are investigated through LM contact angle, XPS/AES and SEM-EDX analyses on Au/Ni and Ni coated copper surfaces. Contact angle measurements in the range of 120o at both 55oC and 125oC show non wetting of LM on CNT, Au and Ni surfaces. Interface reactive wetting elemental composition of 21 days aged LM on Au/Ni and Ni surfaces reveals Ga dissolution in Au and Ni diffusion of ~0.32um in Au which are not present for similar analysis of 1 day LM on Au/Ni surface. Formation of Au-Ni-Ga IMC and IMC-oxide iono-covalency occurrence at the interface causes reduction in surface tension and reduction in interfacial contact resistance.
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Poivey, Christian. "Méthodes d'optimisation globale pour la C.A.O. de circuits intégrés interface avec le simulateur SPICE-PAC, applications, caractérisation de modèles de composants actifs, optimisation des performances de circuits non linéaires /." Grenoble 2 : ANRT, 1987. http://catalogue.bnf.fr/ark:/12148/cb376089463.
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Yu, Xinyu. "High-temperature Bulk CMOS Integrated Circuits for Data Acquisition." Case Western Reserve University School of Graduate Studies / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=case1144420886.
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Smith, O'neil Lohanica. "Design and use of surface modifiers as tools for understanding and controlling interfaces in organic electronics." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51838.
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This thesis focuses on the use of surface modifiers as tools for probing and/or controlling interfaces. Surface modification of transparent conducting oxides (TCOs) with organic and organometallic modifiers can be used as a tool for mediating interfacial energetics as well as probing the kinetics of charge-transfer at the metal oxide/organic interface. The synthetic tunability of these modifiers allows us to design molecules based on various parameters, which include the nature of the binding, spacer, and terminal groups. Based on this framework, several modifiers were synthesized and used to investigate surface energy tuning as well as charge injection kinetics as a function of molecular structure. More specifically, we use XPS/UPS to examine the evolution of the chemical structure and frontier orbital levels of the TCO/organic interface as a function of the chosen surface modifier. In addition, we investigate the impact that various molecular binding groups have on mediating the kinetics of charge-transfer.
In the last section of this body of work we examine the development of dielectric nanocomposite films for capacitor applications. More specifically, we examine the use of phosphonic acid modifiers to functionalize barium titanate nanoparticles in order to provide miscibility with a suitable polymer host. The effect of various modifiers on the dielectric properties not nanocomposite thin films was examined.
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Yamamoto, Silas Demmy. "Integração de sistema transceptor de 60 GHz para aplicações sem fio de interface multimídia de alta definição." [s.n.], 2011. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259229.
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Orientador: Jacobus Willibrordus SwartDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação
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Resumo: O trabalho intitulado Integração de Sistema Transceptor de 60 GHz para Aplicações Sem Fio de Interface Multimídia de Alta Definição (Wireless HDMI) foi realizado na empresa STMicroelectronics (França), no departamento de P&D de Tecnologia / CAD Central e Soluções, como requisito para a obtenção do título de mestre. O objetivo deste trabalho foi de pesquisar e propor uma integração de sistema do tipo Sistema no Empacotamento (SiP ou System in Package) a nível industrial, com o desenvolvimento de um Módulo de Múltiplos Chips (MCM ou Multi-Chip Module) de camadas cerâmicas com tecnologia Cerâmica Cossinterizada sob Alta Temperatura (HTCC), integrando componentes de diferentes tecnologias - um circuito integrado CMOS 65 nm, um circuito integrado monolítico de micro-ondas (MMIC) de Arseneto de Gálio (GaAs) comercial e antenas IPD (Dispositivo de Integração Passiva) de vidro. Além disso foram desenvolvidas técnicas de projeto de integração na tecnologia HTCC, atendendo-se às regras para fabricação e montagem industrial. Utilizaram-se no projeto ferramentas software de projeto de simulação elétrica e eletromagnética, resultando no módulo com área de 13 x 8 mm2 e 1,12 mm de espessura incluindo os componentes. Nas linhas de transmissão do sinal a 60 GHz e de banda base foram medidas perdas de inserção de 1,0 dB/mm e 0,6 dB respectivamente. A antena integrada no módulo apresentou um ganho mínimo de 6 dBi (de 53,5 a 59,5 GHz), com perda de retorno maior que 10 dB (de 51 a 63 GHz) e um pequeno deslocamento em relação à banda especificada. Os resultados de medição de algumas amostras demonstraram que a tecnologia HTCC, para integração do sistema, é viável tanto em termos de desempenho, quanto nos aspectos industrial e comercial, mesmo antes da análise da montagem e desempenho do MMIC HPA e do sistema
Abstract: This Master's degree work, entitled System-in-Package (SiP) Integration of 60 GHz Transceiver for Wireless High Definition Multimedia Interface Application, was executed at STMicroelectronics Company (France), Minatec site in the department of Research and Technological Development/Central CAD and Solutions Department, under the guidance of PhD. Andreia Cathelin. The objective was to research and propose a SiP integration for industrial production. The Multi-Chip Module with ceramic materials (MCM-C) of High Temperature Cofired Ceramic technology (HTCC) was developed. Components and devices of different technologies - an RF 65 nm CMOS Integrated Circuit (IC), a commercial Gallium Arsenide (GaAs) monolithic microwave IC (MMIC), and IPD (Integrated Passive Device) antennas with glass substrate - were integrated into the same module. Further design techniques were developed complying with techniques for industrial assembly and the design rules of Kyocera, the company which provides HTCC technology and module manufacturing. The complete system integration was designed with electronic design automation (EDA) software tools with electrical and electromagnetic simulation resulting in a 13 x 8 mm2 area and 1.12 mm thickness module including its components. The 60 GHz and the base band transmission lines presented an insertion loss of 1.0 dB/mm and 0.6 dB respectively. The IPD antenna integrated in the module presented a 6 dBi minimum gain (53.5 to 59.5 GHz band) with return loss above 10 dB (51 to 63 GHz band) and a small shift of the frequency band. The measurement results of some assembled samples showed that HTCC technology is viable in terms of performance and industrial production for the 60 GHz application, even before the analysis of MMIC HPA and the system evaluation
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica