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1
Radamson, Henry H., Huilong Zhu, Zhenhua Wu, Xiaobin He, Hongxiao Lin, Jinbiao Liu, Jinjuan Xiang, et al. "State of the Art and Future Perspectives in Advanced CMOS Technology." Nanomaterials 10, no. 8 (August 7, 2020): 1555. http://dx.doi.org/10.3390/nano10081555.
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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.
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ZEITZOFF, PETER M., JAMES A. HUTCHBY, and HOWARD R. HUFF. "MOSFET AND FRONT-END PROCESS INTEGRATION: SCALING TRENDS, CHALLENGES, AND POTENTIAL SOLUTIONS THROUGH THE END OF THE ROADMAP." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 267–93. http://dx.doi.org/10.1142/s0129156402001241.
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The development of advanced MOSFETs for future IC technology generations is discussed from the perspective of the 2001 International Technology Roadmap for Semiconductors (ITRS). Starting from overall chip circuit requirements, MOSFET and front-end process integration technology requirements and scaling trends are discussed, as well as some of the key challenges and potential solutions. These include the use of high-k gate dielectrics, metal-gate electrodes, and perhaps the use of non-classical devices such as double-gate MOSFETs in the later stages of the ITRS.
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Radamson, Henry H., Xiaobin He, Qingzhu Zhang, Jinbiao Liu, Hushan Cui, Jinjuan Xiang, Zhenzhen Kong, et al. "Miniaturization of CMOS." Micromachines 10, no. 5 (April 30, 2019): 293. http://dx.doi.org/10.3390/mi10050293.
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When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.
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F. Roslan, Ameer, F. Salehuddin, A. S. M.Zain, K. E. Kaharudin, H. Hazura, A. R. Hanim, S. K. Idris, B. Z. Zarina, and Afifah Maheran A.H. "3D Double Gate FinFET Construction of 30 nm Technology Node Impact Towards Short Channel Effect." Indonesian Journal of Electrical Engineering and Computer Science 12, no. 3 (December 1, 2018): 1358. http://dx.doi.org/10.11591/ijeecs.v12.i3.pp1358-1365.
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<p>This paper presents an investigation on properties of Double Gate FinFET (DGFinFET) and impact of physical properties of FinFET towards short channel effects (SCEs) for 30 nm device, where depletion-layer widths of the source-drain corresponds to the channel length aside from constant fin height (HFIN) and the fin thickness (TFIN). Virtual fabrication process of 3-dimensional (3D) design is applied throughout the study and its electrical characterization is employed and substantial is shown towards the FinFET design whereby in terms of the ratio of drive current against the leakage current (ION/IOFF ratio) at 563138.35 compared to prediction made by the International Technology Roadmap Semiconductor (ITRS) 2013. Conclusively, the incremental in ratio has fulfilled the desired in incremental on the drive current as well as reductions of the leakage current. Threshold voltage (VTH) meanwhile has also achieved the nominal requirement predicted by the International Technology Roadmap Semiconductor (ITRS) 2013 for which is at 0.676±12.7% V. The ION , IOFF and VTH obtained from the device has proved to meet the minimum requirement by ITRS 2013 for low performance Multi-Gate technology.</p>
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Kraus, W., and D. Schmitt-Landsiedel. "Influence of gate tunneling currents on switched capacitor integrators." Advances in Radio Science 7 (May 19, 2009): 225–29. http://dx.doi.org/10.5194/ars-7-225-2009.
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Abstract. In order to achieve a higher level of integration in modern VLSI systems, not only the lateral geometrical dimensions have to be scaled. Lowering the supply voltage also requires scaling down the oxide thickness of the transistors. While the oxide thickness is scaled down proportionally with the supply voltage, the gate tunneling currents grow exponentially, which results in special issues concerning deviations in charge based analog and mixed signal circuitry. The influence of gate tunneling currents on this kind of circuits will be demonstrated at a fully differential switched capacitor integrator. The used process data is derived from the International Technology Roadmap for Semiconductors (ITRS Roadmap, 2006). The Parameter sets for the simulations are based on the Predictive Technology Model of the Arizona State University Modelling Group for the 65 nm Technology node (Predictive Technology Model, 2008).
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Xu, K., S. Pichler, Kurt Wostyn, G. Cado, C. Springer, Glenn W. Gale, Michael Dalmer, et al. "Removal of Nano-Particles by Aerosol Spray: Effect of Droplet Size and Velocity on Cleaning Performance." Solid State Phenomena 145-146 (January 2009): 31–34. http://dx.doi.org/10.4028/www.scientific.net/ssp.145-146.31.
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As the dimensions of the structures of integrated circuits shrink, the influence of particles on device yield becomes increasingly important. According to the cleaning requirements of the International Technology Roadmap for Semiconductors (ITRS) in 2007, particles of 32 nm and larger are believed to be detrimental to devices and thus have to be removed. To remove nano-particles with minimal substrate loss and no damage requires very dilute chemistries and sufficiently gentle physical forces in a cleaning process. In this work the performance of an aerosol spray based cleaning technique is evaluated with regard to the removal efficiency of nano-particles as well as substrate loss and structural damage.
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Heyns, M., and W. Tsai. "Ultimate Scaling of CMOS Logic Devices with Ge and III–V Materials." MRS Bulletin 34, no. 7 (July 2009): 485–92. http://dx.doi.org/10.1557/mrs2009.136.
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AbstractOver the years, many new materials have been introduced in advanced complementary metal oxide semiconductor (CMOS) processes in order to continue the trend of reducing the gate length and increasing the performance of CMOS devices. This is clearly evidenced in the International Technology Roadmap for Semiconductors (ITRS), which indicates the requirements and technological challenges in the microelectronics industry in various technology nodes. Every new technology node, characterized by the minimal device dimensions that are used, has required innovations in new materials and transistor design. The introduction of deposited high-κ gate dielectrics and metal gates as replacements for the thermally grown SiO2 and poly-Si electrode was a major challenge that has been met in the transition toward the 32 nm technology node since it replaced the heart of the metal oxide semiconductor structure. For the next generation of technology nodes, even bigger hurdles will need to be overcome, since new device structures and high-mobility channel materials such as Ge and III–V compounds might be needed, according to the ITRS roadmap, to meet the power and performance specifications of the 16 nm CMOS node and beyond. The basic properties of these high-mobility channel materials and their impact on the device performance have to be fully understood to allow process integration and full-scale manufacturing. In addition to thermal stability, compatibility with other materials, electronic transport properties, and especially the passivation of electronically active defects at the interface with a high-κ dielectric, are enormous challenges. Many encouraging results have been obtained, but the stringent demands in terms of electrical performance and oxide thickness scaling needed for highly scaled CMOS devices are not yet fully met. Other areas where breakthroughs will be needed are the formation of low-resistivity contacts, especially on III–V materials, and III–V materials suited for pMOS channels. An overview of the major successes and remaining critical issues in the materials research on high-mobility channel materials for advanced CMOS devices is given in this issue of MRS Bulletin.
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Wilson, Peter R., Braham Ferreira, Jing Zhang, and Christina DiMarino. "IEEE ITRW: International Technology Roadmap for Wide-Bandgap Power Semiconductors: An Overview." IEEE Power Electronics Magazine 5, no. 2 (June 2018): 22–25. http://dx.doi.org/10.1109/mpel.2018.2821938.
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Kang, Yuhao, Walter Den, Hsunling Bai, and Fu-Hsiang Ko. "Surface Deposition of Diethyl Phthalate on SiO2 and Si3N4 Wafers in Simulated Cleanroom Environment." Journal of the IEST 48, no. 1 (September 1, 2005): 21–32. http://dx.doi.org/10.17764/jiet.48.1.f2l1547q134n506t.
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The surface deposition kinetics of airborne diethyl phthalate (DEP), a representative compound for high-boiling-point organic contaminants in cleanroom environments, were investigated in this study. Between the two types of wafer surfaces evaluated, wafer surfaces with oxide (SiO2) and wafer surfaces with nitride (Si3N4), DEP exhibited a stronger propensity to absorb on the SiO2 wafers, presumably due to the greater dipole moment between DEP and SiO2 surfaces. Under well-controlled exposure conditions, the rate parameters of a theoretical surface kinetic model were determined by employing a heuristic algorithm for numerical optimization to match the experimental profile. Subsequently, a series of time-dependent surface DEP concentrations were simulated and validated with the experimental data under various ambient concentrations. Estimation of the allowable wafer exposure durations and the maximum ambient concentrations were exemplified based on the guideline recommended by the International Technology Roadmap for Semiconductors (ITRS).1
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Leela Rani, V., and M. Madhavi Latha. "Particle Swarm Optimization Algorithm for Leakage Power Reduction in VLSI Circuits." International Journal of Electronics and Telecommunications 62, no. 2 (June 1, 2016): 179–86. http://dx.doi.org/10.1515/eletel-2016-0025.
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Abstract Leakage power is the dominant source of power dissipation in nanometer technology. As per the International Technology Roadmap for Semiconductors (ITRS) static power dominates dynamic power with the advancement in technology. One of the well-known techniques used for leakage reduction is Input Vector Control (IVC). Due to stacking effect in IVC, it gives less leakage for the Minimum Leakage Vector (MLV) applied at inputs of test circuit. This paper introduces Particle Swarm Optimization (PSO) algorithm to the field of VLSI to find minimum leakage vector. Another optimization algorithm called Genetic algorithm (GA) is also implemented to search MLV and compared with PSO in terms of number of iterations. The proposed approach is validated by simulating few test circuits. Both GA and PSO algorithms are implemented in Verilog HDL and the simulations are carried out using Xilinx 9.2i. From the simulation results it is found that PSO based approach is best in finding MLV compared to Genetic based implementation as PSO technique uses less runtime compared to GA. To the best of the author’s knowledge PSO algorithm is used in IVC technique to optimize power for the first time and it is quite successful in searching MLV.
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Lee, Sang Ho, Min Su Cho, Jun Hyeok Jung, Won Douk Jang, Hye Jin Mun, Jaewon Jang, Jin-Hyuk Bae, and In Man Kang. "Design of a Capacitorless Dynamic Random Access Memory Based on Ultra-Thin Polycrystalline Silicon Junctionless Field-Effect Transistor with Dual-Gate." Journal of Nanoscience and Nanotechnology 21, no. 8 (August 1, 2021): 4223–29. http://dx.doi.org/10.1166/jnn.2021.19386.
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In this paper, a 1T-DRAM based on the junctionless field-effect transistor (JLFET) with an ultrathin polycrystalline silicon layer was designed and investigated by using technology computer-aided design simulation (TCAD). The application of a negative voltage at the control gate results in the generation of holes in the storage region by the band-to-band tunneling (BTBT) effect. Memory characteristics such as sensing margin and retention time are affected by the doping concentration of the storage region, bias condition of the program, and length of the intrinsic region. In addition, the gate acts as a switch that controls the transfer characteristics while the control gate plays a role in retaining holes in the hold state. The device was optimized, considering various parameters such as the doping concentration of the storage region (Nstorage), intrinsic region length (Lint), and operation bias conditions to obtain a high sensing margin of 49.7 μA/μm and a long retention time of 2 s even at a high temperature of 358 K. The obtained retention time is almost 30 times longer than that predicted for modern DRAM cells by the International technology roadmap for semiconductors (ITRS).
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Afifah Maheran, Abdul Hamid, P. Susthitha Menon, I. Ahmad, and S. Shaari. "Application of Taguchi Method in Designing a 22nm High-k/Metal Gate NMOS Transistor." Advanced Materials Research 925 (April 2014): 514–18. http://dx.doi.org/10.4028/www.scientific.net/amr.925.514.
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This paper reports on the application of Taguchi method in modelling a 22nm gate length high-k/metal gate NMOS transistor. The Nominal-the-Best Signal-to-noise Ratio (SNR) using Taguchis optimization technique was utilized to optimize the process parameters in determining the best threshold voltage (Vth) value where it was used as the evaluation variable. The high permittivity material (high-k) / metal gate device consists of titanium dioxide (TiO2) and tungsten silicide (WSix) respectively. The simulation work was executed using a TCAD simulator, which consist of ATHENA and ATLAS as a process and device simulator respectively. In this research, the Halo implantation tilting angle was identified as the most influencial factor in affecting the Vthwith a percentage of 87%, followed by the oxide growth anneal temperature (8%), the metal gate anneal temperature (4%) and lastly the Halo implantation dose (1%). As a conclusion, the Halo tilting angle is the dominant factor in optimizing the process parameter. Meanwhile the Halo implantation dose can be considered as an adjustment factor in order to achieve the target Vthvalue of 0.289 V which is in line with projections made by the International Technology Roadmap for Semiconductors (ITRS).
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El Hariti, Zineb, Abdelhakim Alali, Mohamed Sadik, and Kaoutar Aamali. "Cosimulation of Power and Temperature Models at the SystemC/TLM for a Soft-Core Processor." Advances in Materials Science and Engineering 2020 (February 11, 2020): 1–7. http://dx.doi.org/10.1155/2020/2567915.
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Nowadays, modern embedded applications are becoming more and more complex and resource demanding. Fortunately, Systems on Chip (SoC) are one of the keys used to follow their requirements that stand in need of high performance while maintaining a low-power profile. On one hand, today, due to the limited power budget imposed by the batteries, power is the limiting factor of the logic CMOS. On the other hand, the downscaling of the technology node for 65 nm and beyond, based on the International Technology Roadmap for Semiconductors (ITRS) as a reference, has not only resulted in huge energy consumption but also increased the temperature chip. To address this challenge, designing at the system level is the suitable measure to tackle with the complexity of the Systems on Chip, aiming at having better adjustment between timing and accuracy for power and temperature estimations. We present in this paper, at the first stage, two models describing the static and dynamic power at the physical level. These models are implemented on an open virtual platform Model Power-Consumption and Temperature in SystemC/TLM (LIBTLMPWT) based on a representative SoC architecture. At the second stage, we focus on power, especially the thermal behaviour of the chip while running three benchmarks set on the game of life application for two different technology nodes.
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Atan, Norani, Burhanuddin Yeop Majlis, Ibrahin Ahmad, and K. H. Chong. "Analysis the Effect of Control Factors Optimization on the Threshold Voltage of 18 nm PMOS Using L27 Taguchi Method." Indonesian Journal of Electrical Engineering and Computer Science 10, no. 3 (June 1, 2018): 934. http://dx.doi.org/10.11591/ijeecs.v10.i3.pp934-942.
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This research paper is about the investigation of Halo Implantation, Halo Implantation Energy, Halo Tilt, Compensation Implantation and Source/Drain Implantation. They are types of control factors that used in achievement of the threshold voltage value. To support the successfully of the threshold voltage (VTH) producing, Taguchi method by using L27 orthogonal array was used to optimize the control factors variation. This analysis has involved with 2 main factors which are break down into five control factors and two noise factors. The five control factors were varied with three levels of each and the two noise factors were varied with two levels of each in 27 experiments. In Taguchi method, the statistics data of 18 nm PMOS transistor are from the signal noise ratio (SNR) with nominal-the best (NTB) and the analysis of variance (ANOVA) are executed to minimize the variance of threshold voltage. This experiment implanted by using Virtual Wafer Fabrication SILVACO software which is to design and fabricate the transistor device. Experimental results revealed that the optimization method is achieved to perform the threshold voltage value with least variance and the percent, which is only 2.16%. The threshold voltage value from the experiment shows -0.308517 volts while the target value that is -0.302 volts from value of International Technology Roadmap of semiconductor, ITRS 2012. The threshold voltage value for 18 nm PMOS transistor is well within the range of -0.302 ± 12.7% volts that is recommendation by the International Roadmap for Semiconductor prediction 2012.
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Salehuddin, Fauziyah, Anis Suhaila Mohd Zain, Niza Mohd Idris, Ahmad Kamal Mat Yamin, Afifah Maheran Abdul Hamid, Ibrahim Ahmad, and P. Susthitha Menon. "Analysis of Threshold Voltage Variance in 45nm N-Channel Device Using L27 Orthogonal Array Method." Advanced Materials Research 903 (February 2014): 297–302. http://dx.doi.org/10.4028/www.scientific.net/amr.903.297.
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In this research, orthogonal array of L27 in Taguchi Method was used to optimize the process parameters (control factors) variation in 45nm n-channel device with considering the interaction effect. The signal-to-noise (S/N) ratio and analysis of variance (ANOVA) are employed to study the performance characteristics of the device. There are only five process parameters (control factors) were varied for 3 levels to performed 27 experiments. Whereas, the two noise factors were varied for 2 levels to get four readings of Vth for every row of experiment. In this study, nominal-the-best characteristic was used in an effort to minimize the variance of Vth. The results show that the Vth values have least variance and percent different from the target value (0.287V) for this device is 1.42% (0.293V). This value is closer with International Technology Roadmap for Semiconductor (ITRS) prediction.
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Shailendra, Singh Rohitkumar, and V. N. Ramakrishnan. "Study of Reconfigurable Properties of DG-CNTFET with Different Oxide Material in Nanoscale Regime." Advanced Science Letters 24, no. 8 (August 1, 2018): 5964–69. http://dx.doi.org/10.1166/asl.2018.12228.
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As the scaling of Si MOSFET is approaching its limits, new alternative devices are coming up to overcome these limitations. CNTFET becomes one of the most promising candidates for Si MOS technology and its stunning performance opens a door of new possibilities in the field of nano-electronics. Towards or beyond the end of international technology roadmap for semiconductor (ITRS) 2009, when MOS scaling will likely become ineffective and/or prohibitively costly, some version(s) of emerging devices will be needed if the industry has to continue to enjoy rapid improvements in performance, lower power dissipation, cost per function, and higher functional density. In this paper, we have studied the effect of different oxide material and its thickness on the reconfigurable properties of DG-CNTFET up to 5 nm length scale. We used Non Equilibrium Green’s Function Method (NEGF) and mode space method to simulate our device to study the effect of different oxide material at smaller length scale. For dielectric constant (K) = 11 and 16 the drain current starts saturating with gate voltage = 0.25 V. Whereas dielectric constant (K) = 25, the drain current starts saturating with gate voltage = 0.20 V. Hence our simulation study shows that high dielectric constant material is better for CNTFET based device at few nanometer scale.
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F. Roslan, Ameer, F. Salehuddin, A. S. M. Zain, K. E. Kaharudin, and I. Ahmad. "Enhanced performance of 19 single gate MOSFET with high permittivity dielectric material." Indonesian Journal of Electrical Engineering and Computer Science 18, no. 2 (May 1, 2020): 724. http://dx.doi.org/10.11591/ijeecs.v18.i2.pp724-730.
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<p><span>In this research, the performance of the 19 nm single gate MOSFET is enhanced through the implementation of the high permittivity dielectric material. The MOSFET scaling trends necessities in device dimensions can be satisfied through the implementation of the high-K dielectric materials in place of the SiO2. Therefore, the 19 nm n-channel MOSFET device with different High-K dielectric materials are implemented and its performance improvement has also been analysed. Virtual fabrication is exercised through ATHENA module from Silvaco TCAD tool. Meanwhile, the device characteristic was utilized by using an ATLAS module. The aforementioned materials have also been simulated and compared with the conventional gate oxide SiO2 for the same structure. At the end, the results have proved that Titanium oxide (TiO2) device is the best dielectric material with a combination of metal gate Tungsten Silicides (WSix). The drive current (ION) of this device (WSix/TiO2) is 587.6 µA/um at 0.534 V of threshold voltage (VTH) as opposed to the targeted 0.530 V predicted, as well as a relatively low IOFF that is obtained at 1.92 pA/µm. This ION value meets the minimum requirement predicted by International Technology Roadmap for Semiconductor (ITRS) 2013 prediction for low performance <br /> (LP) technology. </span></p>
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Hazra, Arnab, and Sukumar Basu. "Graphene Nanoribbon as Potential On-Chip Interconnect Material—A Review." C 4, no. 3 (August 30, 2018): 49. http://dx.doi.org/10.3390/c4030049.
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In recent years, on-chip interconnects have been considered as one of the most challenging areas in ultra-large scale integration. In ultra-small feature size, the interconnect delay becomes more pronounced than the gate delay. The continuous scaling of interconnects introduces significant parasitic effects. The resistivity of interconnects increases because of the grain boundary scattering and side wall scattering of electrons. An increased Joule heating and the low current carrying capability of interconnects in a nano-scale dimension make it unreliable for future technology. The devices resistivity and reliability have become more and more serious problems for choosing the best interconnect materials, like Cu, W, and others. Because of its remarkable electrical and its other properties, graphene becomes a reliable candidate for next-generation interconnects. Graphene is the lowest resistivity material with a high current density, large mean free path, and high electron mobility. For practical implementation, narrow width graphene sheet or graphene nanoribbon (GNR) is the most suitable interconnect material. However, the geometric structure changes the electrical property of GNR to a small extent compared to the ideal behavior of graphene film. In the current article, the structural and electrical properties of single and multilayer GNRs are discussed in detail. Also, the fabrication techniques are discussed so as to pattern the graphene nanoribbons for interconnect application and measurement. A circuit modeling of the resistive-inductive-capacitive distributed network for multilayer GNR interconnects is incorporated in the article, and the corresponding simulated results are compared with the measured data. The performance of GNR interconnects is discussed from the view of the resistivity, resistive-capacitive delay, energy delay product, crosstalk effect, stability analysis, and so on. The performance of GNR interconnects is well compared with the conventional interconnects, like Cu, and other futuristic potential materials, like carbon nanotube and doped GNRs, for different technology nodes of the International Technology Roadmap for Semiconductors (ITRS).
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Roslan, Ameer F., F. Salehuddin, A. S. M. Zain, K. E. Kaharudin, and I. Ahmad. "Optimization of 16 nm DG-FinFET using L25 orthogonal array of taguchi statistical method." Indonesian Journal of Electrical Engineering and Computer Science 18, no. 3 (June 1, 2020): 1207. http://dx.doi.org/10.11591/ijeecs.v18.i3.pp1207-1214.
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<span>The impact of the optimization using Taguchi statistical method towards the electrical properties of a 16 nm double-gate FinFET (DG-FinFET) is investigated and analyzed. The inclusion of drive current (I<sub>ON</sub>), leakage current (I<sub>OFF</sub>), and threshold voltage (V<sub>TH</sub>) as part of electrical properties presented in this paper will be determined by the amendment of six process parameters that comprises the polysilicon doping dose, polysilicon doping tilt, Source/Drain doping dose, Source/Drain doping tilt, V<sub>TH</sub> doping dose, V<sub>TH</sub> doping tilt, alongside the consideration of noise factor in gate oxidation temperature and polysilicon oxidation temperature. Silvaco TCAD software is utilized in this experiment with the employment of both ATHENA and ATLAS module to perform the respective device simulation and the electrical characterization of the device. The output responses obtained from the design is then succeeded by the implementation of Taguchi statistical method to facilitate the process parameter optimization as well as its design. The effectiveness of the process parameter is opted through the factor effect percentage on Signal-to-noise ratio with considerations towards I<sub>ON</sub> and I<sub>OFF</sub>. The most dominant factor procured is the polysilicon doping tilt. The I<sub>ON</sub> and I<sub>OFF</sub> obtained after the optimization are 1726.88 μA/μm and 503.41 pA/μm for which has met the predictions of International Technology Roadmap for Semiconductors (ITRS) 2013. </span>
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F. Roslan, Ameer, F. Salehuddin, A. S. M. Zain, K. E. Kaharudin, I. Ahmad, H. Hazura, A. R. Hanim, and S. K. Idris. "Comparative high-k material gate spacer impact in DG-FinFET parameter variations between two structures." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 2 (May 1, 2019): 573. http://dx.doi.org/10.11591/ijeecs.v14.i2.pp573-580.
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<span lang="EN-GB">This paper investigates the impact of the high-K material gate spacer on short channel effects (SCEs) for the 16 nm double-gate FinFET (DG-FinFET), where depletion-layer widths of the source-drain corresponds to the channel length. Virtual fabrication process along with design modification throughout the study and its electrical characterization is implemented and significant improvement is shown towards the altered structure design whereby in terms of the ratio of drive current against the leakage current (I<sub>ON</sub>/I<sub>OFF</sub> ratio), all three materials tested being S<sub>3</sub>N<sub>4</sub>, HfO<sub>2</sub> and TiO<sub>2</sub> increases from the respective 60.90, 80.70 and 84.77 to 84.77, 91.54 and 92.69. That being said, the incremental in ratio has satisfied the incremental on the drive current as well as decreases the leakage current. Threshold voltage (V<sub>TH</sub>) for all dielectric materials have also satisfy the minimum requirement predicted by the International Technology Roadmap Semiconductor (ITRS) 2013 for which is at 0.461±12.7% V. Based on the results obtained, the high-K materials have shown a significant improvement, specifically after the modifications towards the Source/Drain. Compared to the initial design made, TiO<sub>2</sub> has improved by 12.94% after the alteration made in terms of the overall I<sub>ON</sub> and I<sub>OFF</sub> performances through the I<sub>ON</sub>/I<sub>OFF</sub> ratio value obtained, as well as meeting the required value for V<sub>TH </sub>obtained at 0.464V. The I<sub>ON</sub> from high-K materials has proved to meet the minimum requirement by ITRS 2013 for low performance Multi-Gate technology.</span>
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M. Arden, Wolfgang. "The International Technology Roadmap for Semiconductors—Perspectives and challenges for the next 15 years." Current Opinion in Solid State and Materials Science 6, no. 5 (October 2002): 371–77. http://dx.doi.org/10.1016/s1359-0286(02)00116-x.
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Verd, Jaume, and Jaume Segura. "Editorial for the Special Issue on Development of CMOS-MEMS/NEMS Devices." Micromachines 10, no. 4 (April 24, 2019): 273. http://dx.doi.org/10.3390/mi10040273.
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Micro and nanoelectromechanical system (M/NEMS) devices constitute key technological building blocks to enable increased additional functionalities within integrated circuits (ICs) in the More-Than-Moore era, as described in the International Technology Roadmap for Semiconductors [...]
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Guo, Ying, Feng Pan, Gaoyang Zhao, Yajie Ren, Binbin Yao, Hong Li, and Jing Lu. "Sub-5 nm monolayer germanium selenide (GeSe) MOSFETs: towards a high performance and stable device." Nanoscale 12, no. 28 (2020): 15443–52. http://dx.doi.org/10.1039/d0nr02170a.
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ML GeSe field-effect transistors have an excellent device performance, even at the 1 nm gate-length. The on-state current of the devices can fulfill the requirements of the International Technology Roadmap for Semiconductors (2013 version).
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Garner, C. Michael. "Lithography for enabling advances in integrated circuits and devices." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 370, no. 1973 (August 28, 2012): 4015–41. http://dx.doi.org/10.1098/rsta.2011.0052.
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Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.
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Dapor, Maurizio, Mark A. E. Jepson, Beverley J. Inkson, and Cornelia Rodenburg. "The Effect of Oxide Overlayers on Secondary Electron Dopant Mapping." Microscopy and Microanalysis 15, no. 3 (May 22, 2009): 237–43. http://dx.doi.org/10.1017/s1431927609090400.
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AbstractThe International Technology Roadmap for Semiconductors ranks dopant profiling as one of the most difficult challenges for analysis of semiconductors. Dopant mapping in the scanning electron microscope (SEM) has the potential to provide a solution. This technique has not yet found widespread application, however, mainly due to the lack of a comprehensive theoretical model, uncertain quantification, and its inability to differentiate doping levels in n-type silicon. Although a Monte Carlo model was recently published that closely matched experimental data obtained in p-doped silicon to data obtained from the theoretical model, a large discrepancy between experimental data obtained for n-type silicon was found. Here we present a Monte Carlo model that provides close matches between experimental and calculated data in both n- and p-type silicon, paving the way for a widespread application of SEM dopant contrast.
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Cao, Qing, Jerry Tersoff, Damon B. Farmer, Yu Zhu, and Shu-Jen Han. "Carbon nanotube transistors scaled to a 40-nanometer footprint." Science 356, no. 6345 (June 29, 2017): 1369–72. http://dx.doi.org/10.1126/science.aan2476.
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The International Technology Roadmap for Semiconductors challenges the device research community to reduce the transistor footprint containing all components to 40 nanometers within the next decade. We report on a p-channel transistor scaled to such an extremely small dimension. Built on one semiconducting carbon nanotube, it occupies less than half the space of leading silicon technologies, while delivering a significantly higher pitch-normalized current density—above 0.9 milliampere per micrometer at a low supply voltage of 0.5 volts with a subthreshold swing of 85 millivolts per decade. Furthermore, we show transistors with the same small footprint built on actual high-density arrays of such nanotubes that deliver higher current than that of the best-competing silicon devices under the same overdrive, without any normalization. We achieve this using low-resistance end-bonded contacts, a high-purity semiconducting carbon nanotube source, and self-assembly to pack nanotubes into full surface-coverage aligned arrays.
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Dichtel, William R., James R. Heath, and J. Fraser Stoddart. "Designing bistable [2]rotaxanes for molecular electronic devices." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 365, no. 1855 (April 12, 2007): 1607–25. http://dx.doi.org/10.1098/rsta.2007.2034.
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The development of molecular electronic components has been accelerated by the promise of increased circuit densities and reduced power consumption. Bistable rotaxanes have been assembled into nanowire crossbar devices, where they may be switched between low- and high-conductivity states, forming the basis for a molecular memory. These memory devices have been scaled to densities of 10 11 bits cm −2 , the 2020 node for memory of the International Technology Roadmap for Semiconductors. Investigations of the kinetics and thermodynamics associated with the electromechanical switching processes of several bistable [2]rotaxane derivatives in solution, self-assembled monolayers on gold, polymer electrolyte gels and in molecular switch tunnel junction devices are consistent with a single, universal switching mechanism whose speed is dependent largely on the environment, as well as on the structure of the switching molecule. X-ray reflectometry studies of the bistable rotaxanes assembled into Langmuir monolayers also lend support to an oxidatively driven mechanical switching process. Structural information obtained from Fourier transform reflection absorption infrared spectroscopy of rotaxane monolayers taken before and after evaporation of a Ti top electrode confirmed that the functionality responsible for switching is not affected by the metal deposition process. All the considerable experimental data, taken together with detailed computational work, support the hypothesis that the tunnelling current hysteresis, which forms the basis of memory operation, is a direct result of the electromechanical switching of the bistable rotaxanes.
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Kacker, Karan, Thomas Sokol, Wansuk Yun, Madhavan Swaminathan, and Suresh K. Sitaraman. "A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance." Journal of Electronic Packaging 129, no. 4 (April 9, 2007): 460–68. http://dx.doi.org/10.1115/1.2804096.
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Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.
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Neisser, Mark. "Patterning roadmap: 2017 prospects." Advanced Optical Technologies 6, no. 3-4 (January 1, 2017). http://dx.doi.org/10.1515/aot-2017-0039.
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AbstractRoad mapping of semiconductor chips has been underway for over 20 years, first with the International Technology Roadmap for Semiconductors (ITRS) roadmap and now with the International Roadmap for Devices and Systems (IRDS) roadmap. The original roadmap was mostly driven bottom up and was developed to ensure that the large numbers of semiconductor producers and suppliers had good information to base their research and development on. The current roadmap is generated more top-down, where the customers of semiconductor chips anticipate what will be needed in the future and the roadmap projects what will be needed to fulfill that demand. The More Moore section of the roadmap projects that advanced logic will drive higher-resolution patterning, rather than memory chips. Potential solutions for patterning future logic nodes can be derived as extensions of ‘next-generation’ patterning technologies currently under development. Advanced patterning has made great progress, and two ‘next-generation’ patterning technologies, EUV and nanoimprint lithography, have potential to be in production as early as 2018. The potential adoption of two different next-generation patterning technologies suggests that patterning technology is becoming more specialized. This is good for the industry in that it lowers overall costs, but may lead to slower progress in extending any one patterning technology in the future.
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Gossmann, H. J., C. S. Rafferty, and P. Keys. "Junctions for Deep Sub-100 NM MOS: How Far will Ion Implantation Take Us?" MRS Proceedings 610 (2000). http://dx.doi.org/10.1557/proc-610-b1.2.
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AbstractWe analyze the requirements that the International Technology Roadmap for Semiconductors (ITRS) implicitly imposes on the two-dimensional source/drain (SD) dopant profile and translate the results into implant parameters (energy, dose, peak concentration). We do this by determining the voltage drop that the SD current develops across the three main (exclusive of the channel) resistive components in the current path: the spreading resistance in the extension region; the metal-semiconductor contact; and the resistance in the link-up region where the SDregion meets the channel. The largest resistance occurs in the link-up region, followed by the resistance of the contact; the extension contribution is the smallest. The extension resistance requirement can be satisfied by ion-implantation for all generations of the ITRS. The link-up region requires very abrupt lateral profiles, not demonstrated so far by ion-implantation. It is found that such resistance cannot be reduced without impacting the intrinsic device behavior. The contact eventually necessitates dopant concentrations in excess of solid solubility and for NMOS in excess of the fundamental limit of dopant activation.
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A. H., Afifah Maheran,, Menon, P. S., I. Ahmad, and S. Shaari. "Optimisation of Process Parameters for Lower Leakage Current in 22 nm n-type MOSFET Device using Taguchi Method." Jurnal Teknologi 68, no. 4 (May 15, 2014). http://dx.doi.org/10.11113/jt.v68.2994.
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In this article, Taguchi orthogonal array method was used to optimize the process parameters during the design of a 22 nm n-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in order to decrease the leakage current (ILEAK) of the device. Titanium dioxide (TiO2) was used as the dielectric layer to replace the traditional silicon dioxide SiO2 and tungsten silicide (WSix) was used as a metal gate to replace polysilicon. The device’s fabrication and electrical characterization were executed using ATHENA and ATLAS modules from Silvaco International. Taguchi’s Power of Three Series L9 orthogonal array was used to optimize the device process parameters and to finally predict the best process parameter combination to obtain the minimum leakage current (ILEAK) using Smaller-the-Better (STB) signal-to-noise ratio (SNR). The optimization resulted in the attainment of the lowest ILEAK mean value of 0.25759 nA/µm which is in accordance to the predicted value given in the International Technology Roadmap for Semiconductors (ITRS) 2011.
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Torres, Florent, Eric Kerhervé, Andreia Cathelin, and Magali De Matos. "A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications." International Journal of Microwave and Wireless Technologies, August 25, 2020, 1–18. http://dx.doi.org/10.1017/s1759078720001087.
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Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.
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Ota, Masahiro, Manabu Tsujimura, Hiroaki Inoue, Hirokazu Ezawa, and Masahiro Miyata. "Silver Damascene Process with Cap Layer." MRS Proceedings 732 (2002). http://dx.doi.org/10.1557/proc-732-i3.1.
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AbstractDevelopment of semiconductors has proceeded according to broad frameworks such as the International Technology Roadmap for Semiconductors (ITRS). A key development in semiconductor technology involves the adoption of several new materials, such as Cu, low-k and high-k materials, and noble metals in capacitors, transistors, and/or interconnects. These developments will likely lead to wider application of the planarization process to new processes and new materials, and call for even stricter planarization performance requirements. One example involves planarizing Ag interconnects with an optimal cap layer configuration for reducing RC delays. The Cu interconnect process is currently used to reduce wire resistivity. One material that has been proposed as a successor to Cu is Ag. Many low-k materials have been developed with the goal of reducing dielectric constant (k). However, damascene design and matters such as cap layer configuration are also important considerations in reducing the effective dielectric constant (k eff). Our report herein begins by proposing Ni-B deposited by electroless plating as a candidate cap material, due to the following characteristics: (1) it offers good selectivity for Ag interconnects; (2) it provides good barrier effects through thermal processes; and (3) it provides good controllability of deposition rates. Next, we report that Ag damascene with Ni-B cap layer can be realized through electroplating and polishing of Ag interconnects. Although Ag polishing technologies are currently not fully developed, we suggest that they may nevertheless be successfully applied to polish Ag.
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Takamura, Yayoi, Sameer Jain, Peter B. Griffin, and James D. Plummer. "A Study of the Deactivation of High Concentration, Laser Annealed Dopant Profiles in Silicon." MRS Proceedings 669 (2001). http://dx.doi.org/10.1557/proc-669-j7.3.
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ABSTRACTAs semiconductor device dimensions continue to decrease, the main challenge in the area of junction formation involves decreasing the junction depth while simultaneously increasing the active dopant concentration. Laser annealing is being investigated as an alternative to rapid thermal annealing (RTA) to repair the damage from ion implantation and to activate the dopants. With this technique, uniform, box-shaped profiles are obtained, with dopant concentrations that can exceed equilibrium solubility limits. Unfortunately, these super-saturated dopant concentrations exist in a metastable state and deactivate upon further thermal processing. In this work, a comprehensive study of the deactivation kinetics of common dopants (P, B, and Sb) was performed across a range of annealing conditions. For comparison, As deactivation data from the work of Rousseau et al.1 is also presented. Each dopant exhibits different deactivation behavior, however, As and P can be classified as unstable species while B and Sb are stable against deactivation until higher temperatures of 700-800°C. In addition, a means of maintaining these metastably doped layers is being investigated with the goal of meeting the International Technology Roadmap for Semiconductors (ITRS) requirements for ultrashallow junctions.
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Jin, Yawei, Lei Ma, Chang Zeng, Krishnanshu Dandu, and Doug William Barlage. "Structure and Process Parameter Optimization for Sub-10nm Gate Length Fully Depleted N-Type SOI MOSFETs by TCAD Modeling and Simulation." MRS Proceedings 913 (2006). http://dx.doi.org/10.1557/proc-0913-d01-10.
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AbstractAccording to most recent 2004 International Technology Roadmap for Semiconductor (2004 ITRS), the high performance (HP) MOSFET physical gate length will be scaled to 9nm (22nm technology node) in 2016. We investigate the manufacturability of this sub-10nm gate length fully depleted SOI MOSFET by TCAD simulation. The commercial device simulator ISE TCAD is used. While it is impractical for experiments currently, this study can be used to project performance goals for aggressively scaled devices. In this paper, we will optimize different structure and process parameters at this gate length, such as body thickness, oxide thickness, spacer width, source/drain doping concentration, source/drain doping abruptness, channel doping concentration etc. The sensitivity of device electrical parameters, such as Ion, Ioff, DIBL, Sub-threshold Swing, threshold voltage, trans-conductance etc, to physical variations will be considered. The main objective of this study is to identify the key design issues for sub-10nm gate length Silicon based fully depleted MOSFET at the end of the ITRS. The paper will present the final optimized device structure and optimized performance will be reported.
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Polspoel, Wouter, Wilfried Vandervorst, Lidia Aguilera, Marc Porti, Montserrat Nafria, and Xavier Aymerich. "Improved Characterization of high-k Degradation with Vacuum C-AFM." MRS Proceedings 1074 (2008). http://dx.doi.org/10.1557/proc-1074-i11-02.
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ABSTRACTLocal phenomena like trap assisted tunneling and oxide breakdown (BD) in new high-k gate oxides in advanced MOS devices hinder the acquisition of device requirements stated in the International Technology Roadmap for Semiconductors (ITRS). Conductive Atomic Force Microscopy (C-AFM) visualizes these local phenomena by measuring the local tunneling through the dielectric. In the first part of this work we show that the physical composition of surface protrusions, that are produced at sites electrically stressed with C-AFM and that distort the electrical measurements, is oxidized Si. In the second part, we illustrate that C-AFM measurements become more reliable in high vacuum (1e−5torr) as surface (oxidized Si protrusions) and tip damage is reduced. Finally, we illustrate good agreement between conventional macroscopic electrical measurements and nanometer-scale C-AFM measurements on normal and gate – removed high-k capacitors, respectively. Moreover, to illustrate the strength of the local tunneling technique, we show the possibility of locating BD spots on a high-k capacitor.
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Borland, John O. "Low Temperature Shallow Junction Formation For 70nm Technology Node And Beyond." MRS Proceedings 717 (2002). http://dx.doi.org/10.1557/proc-717-c1.1.
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AbstractLow temperature shallow junction formation is an attractive activation technique for 70nm technology node and beyond as it can easily be integrated into device structures that are formed using disposable spacer (reverse source drain extension formation) or low power CMOS devices using high-k/metal gate stack structures. Therefore, this paper will first review the shallow junction requirements as stated in the 2001 ITRS (international technology roadmap for semiconductors) and it's interpretation to ion implantation shallow junction formation for various dopant activation and annealing techniques. First high temperature (>1000°C) RTA spike, flash or sub-melt laser annealing techniques with oxide or oxynitride/polysilicon electrode gate stack structures will be discussed and its limitations to >8E19/cm3 boron electrically active dopant level due to boron solid solubility limit in silicon satisfying only the 100nm technology node requirement (2003). Next, higher temperature laser melt annealing (1200°C to 1400°C) will be discussed and it's applicability beyond 70nm node technology (2006) to 25nm node (2016) where boron solid solubility limit is up to 5E20/cm3. However, if high-k (HfO) dielectric/metal electrode gate stack structures are to be used starting at sub-100nm node in 2005 for low power CMOS then low temperature (>700°C) annealing must be used for shallow junction formation to prevent recrystallization and dielectric constant degradation. Using low temperature SPE (solid phase epitaxial regrowth) annealing techniques in the 550°C to 750°C for short anneal times of >5mins., shallow & abrupt junctions 8.0nm deep, >2.0nm/decade with up to 2.5E20/cm3 boron electrical active dopant level can be achieved satisfying the 25nm technology node (2016) requirements.
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Tian, Wenchao, Chuqiao Wang, Zhanghan Zhao, and Hao Cui. "Structures and Materials of System in Package: A Review." Recent Patents on Mechanical Engineering 13 (July 28, 2020). http://dx.doi.org/10.2174/2212797613999200728190605.
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Background: As a new type of advanced packaging and system integration technology, System-in-Package (SiP) can realize the miniaturization and multi-functionalization of electronic products and is listed as an important direction of development by International Technology Roadmap for Semiconductors (ITRS). <P> Objective: This paper mainly introduces and discusses recent academic research and patents on package structure and packaging materials. Additionally, the trending of development is described. <P> Methods: Firstly, we analyze and summarize the challenges and existing problems in SiP. Then the corresponding solutions are introduced with respect to packaging structure and packaging materials. Finally, the research status of SIP and some patents in these aspects is reviewed. <P> Results: In order to increase the density of internal components, SiP products need to use a stacked structure. The cause of different performance in SiP products are: 1) the stress concentration and bonding quality problems caused by the chip stack structure; 2) the warpage and package thickness problems caused by the package stack; 3) Thermal conductivity of materials and thermal mismatch between materials; 4) Dielectric properties and thermomechanical reliability of materials. The following solutions are summarized: 1) Structural optimization of chip stacking and packaging stacking; 2) Application of new packaging technology; 3) Optimization of packaging materials; 4) Improvement of packaging material processing technology. <P> Conclusion: With the study of packaging structure and packaging materials, SiP can meet the requirements of the semiconductor industry and have great future prospects
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Khan, Aurangzeb, A. Q. S. Shah, and Jihua Gou. "Modeling and Simulation of n-Type Carbon Nanotube Field Effect Transistors Using Ca as Contact Electrodes." MRS Proceedings 1018 (2007). http://dx.doi.org/10.1557/proc-1018-ee10-17.
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AbstractIn this research work, a model has been proposed in view of the recent experimental demonstration using Calcium (Ca) as a contact metal to realize the n-type carbon nanotube field effect transistors (CNTFET). In order to fully optimize this proposed device model, effects of different parameters like the work function, oxide thickness, the oxide capacitance and the source velocity limits were studied. Among all the parameters, the work function of the contact metal plays an important role for controlling the flow of carriers through the carbon nanotube channel and to reduce the threshold voltage. A semi-classical simulation of the proposed n-type CNTFET has been performed. Results show an excellent subthreshold swing value of 62.91 mV/decade, close to the International Technology Roadmap for Semiconductor (ITRS) specifications.
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Venturini, J., M. Hernandez, D. Zahorski, G. Kerrien, T. Sarnet, D. Debarre, J. Boulmer, et al. "Experiment and Modelisation Results on Laser Thermal Processing for Ultra-Shallow Junction Formation: Influence of Laser Pulse Duration." MRS Proceedings 765 (2003). http://dx.doi.org/10.1557/proc-765-d7.3.
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AbstractAccording to the International Technology Roadmap for Semiconductors (ITRS), the doping technology requirements for the MOSFET source and drain regions of the future CMOS generations lead to a major challenge. A critical point of this evolution is the formation of ultra-shallow junctions(USJ) for which present technologies, based on ion implantation and rapid thermal annealing, will hardly meet the ITRS specifications. Laser Thermal Processing (LTP) has been shown to be a potential candidate to solve this fundamental problem. In the present paper, LTP experiments have been performed with two XeCl excimer lasers (λ= 308 nm) with different pulse characteristics. The first laser (Lambda Physik, Compex 102) delivers 200 mJ laser pulses with a duration of ∼25 ns. The second laser is an industrial tool (SOPRA, VEL 15) that delivers 16 J laser pulses with a duration of ∼200 ns and allows to anneal a few cm die in a single laser shot. Here we examine the influence of the pulse duration on LTP of B+ (with and without Ge+ pre-amorphization) and BF2 implanted silicon samples on the basis of real-time optical monitoring of the laser induced melting/recrystallisation process, four-point probe resistivity measurements, secondary ion mass spectrometry (SIMS) depth profiles. Experimental results are compared to finite element modelisation (FIDAP Fluent Software) that takes into account both laser pulses. The activated dopant dose, junction depth and sheet resistance, as a function of the laser fluence and shot number for both lasers, confirm the efficiency of laser processing to realize ultra-shallow and highly doped junctions as required by the future CMOS generations. Influence of the pulse duration on the USJ formation process is also discussed.
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Gutt, J., G. A. Brown, Yoshi Senzaki, and Seung Park. "An Advanced High-k Transistor Utilizing Metal-Organic Precursors in an ALD Deposition of Hafnium Oxide and Hafnium Silicate with Ozone as Oxidizer." MRS Proceedings 811 (2004). http://dx.doi.org/10.1557/proc-811-d2.4.
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AbstractThe International Technology Roadmap for Semiconductors (ITRS) has projected that continued scaling of planar CMOS technology to the 65nm node and beyond will require development of high-k films for transistor gate dielectric applications to allow further scaling of overall device sizes according to Moore's Law [1]. Researchers have recently been studying hafnium-based high-k dielectrics as an alternative to SiO2 [2]. The method of deposition of these films has been found to impact the applicability of the films for both low standby power and high performance applications [3]. Atomic Layer Deposition (ALD) has been among the more widely studied deposition techniques for these films, but previous work has emphasized ALD utilizing inorganic precursors [4]. In this paper, we shall describe a process in which hafnium oxide and hafnium silicate films were deposited from alternating pulses of volatile metal-organic Hf/Si liquid precursors and ozone on 200mm diameter Si substrates using a single wafer ALD system. Electrical characterization of the films is presented, including equivalent oxide thickness (EOT), gate leakage, and electron mobility data, showing an achievement of EOT's ranging from 1.19 to 1.69 nm with high field mobilities from 74% to more than 90% of that of SiO2 (2.1 nm film), and Jg in the range of 80mA to 3 A/cm2.
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"SOME QUICK NOTES ABOUT SEMICONDUCTOR CHIPS FABRICATION: MOOR’S LAWS, INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS (ITRS) AND MAJOR CHALLENGES IN THE STATE-OF-THE ART INTEGRATED CIRCUIT (IC) FABRICATION." IZVESTIYA VYSSHIKH UCHEBNYKH ZAVEDENIY KHIMIYA KHIMICHESKAYA TEKHNOLOGIYA 59, no. 11 (November 21, 2016). http://dx.doi.org/10.6060/tcct.20165911.5503.
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Sun, Lianchao, and Jean-Claude Fouere. "Precise Characterization of Silicon on Insulator (SOI) and Strained Silicon on Si1−xGex on Insulator (SSOI) Stacks with Spectroscopic Ellipsometry." MRS Proceedings 786 (2003). http://dx.doi.org/10.1557/proc-786-e6.9.
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ABSTRACTFurther improvements in CMOS circuit performance such as switching speed and power reduction will rely on the use of silicon on insulator (SOI) substrates with decreased functional layer thicknesses. According to the International Technology Roadmap for Semiconductors (ITRS), the silicon and buried SiO2 (BOX) layer thicknesses for a fully depleted device should be in the ranges of 10–16nm and 24 – 40nm by 2005, respectively. A key issue for fully-depleted CMOS transistors is control of such ultra-thin layer thicknesses and their uniformity along with other parameters such as surface and interface roughness. This poses a challenge to metrology, especially to conventional reflectometry technique because the layer thicknesses must be determined with angstrom precision for both silicon cap and SiO2 box layer.Spectroscopic ellipsometry (SE) is an optical and non destructive technique for determining thin film thickness and material optical properties. Because ellipsometry measures the change in the polarization state for both the amplitude ratio of the p to s polarizations, and in the phase retardation, it provides a precise way to characterize such ultra thin SOI stacks. Comprehensive characterization results for a number of thin and ultra thin SOI stacks with different thickness ranges will be presented together with measurement repeatability results relevant to the film thickness process tolerances. In addition, characterization results for advanced device applications such as strained silicon-on- Si1−xGex-on-insulator (SSOI) will also be shown, demonstrating the use and capability of spectroscopic ellipsometry for precise determination of layer thickness, material composition, interfacial layers, etc. Principles and advantages of the technique will also be discussed in the presentation.
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Arshak, Khalil, Stephen F. Gilmartin, Damien Collins, Olga Korostynska, Arousian Arshak, and Miroslav Mihov. "Ion Beam Lithography And Resist Processing for Nanofabrication." MRS Proceedings 983 (2006). http://dx.doi.org/10.1557/proc-983-0983-ll01-02.
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AbstractThe International Technology Roadmap for Semiconductors (ITRS) identifies the shrinking of lithography critical dimensions (CDs) as one of biggest challenges facing the semiconductor industry as it progresses to smaller geometry nodes. Nanolithography, the patterning of masking CDs below 100nm, enables both nanoscale wafer processing and the exploration of novel nanotechnology applications and devices.Focused Ion Beam (FIB) lithography has significant advantages over alternative nanolithography techniques, particularly when comparing resist sensitivity, topography effects, proximity effects and backscattering. FIB lithography uses the implantation of ions, such as Ga+, in its masking process. Ions implanted into resist in this manner typically have shallow penetration depths (<100nm for Ga+), and this would typically require the use of very thin resist layers during processing. This is often incompatible with subsequent fabrication steps such as plasma etching, where thicker resist layers are usually required to facilitate etch selectivity. Top surface imaging (TSI) is a solution to this problem.When compared with conventional microelectronic lithography, nanolithography techniques such as EUV, electron beam and nanoimprint lithography require expensive process equipment and the use of non-standard process materials.The 2-step negative resist image by dry etching (2-step NERIME) process is a FIB TSI scheme developed for DNQ/novolak based resists, and involves FIB exposure of resist with Ga+, followed by O2 plasma dry development using reactive ion etching. The 2-step NERIME process uses equipment sets and materials commonly found in microelectronic device fabrication (FIB tool, O2 plasma etcher, DNQ/novolak resists), and provides a low-cost and convenient nanolithography option for proof-of-concept nanoscale processing.To be of practical use, a nanolithography scheme must be capable of patterning nanoscale resist features over substrate topography while retaining resist profile control. The nanolithography scheme must also integrate with subsequent plasma etch processing steps that etch various material films such as metals, Si, SiO2, SiN. The 2-step NERIME FIB TSI process has been used to successfully pattern nanoscale (40nm-90nm) resist features on planar and topography substrates. We have also demonstrated sub-100nm etched features on topography substrates using the 2-step NERIME process, reporting 80nm Polycide and TiN etched features, and 90nm Ti etched features, that exhibit excellent profiles and minimal line edge roughness (LER).It is expected that the 2-step NERIME FIB TSI process will be further extended to etch sub-40nm features over topography substrates. The nanoscale etched features will be used to explore proof-of-concept geometry shrink & novel structures, with many possible applications, including NEMs and nanosensors research and development.
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Kozicki, Michael N. "Memory Devices Based on Solid Electrolytes." MRS Proceedings 997 (2007). http://dx.doi.org/10.1557/proc-0997-i05-01.
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AbstractCurrent mainstream memory technologies are unlikely to completely fulfill the solid state data storage requirements that will be imposed beyond the 32 nm node of the International Technology Roadmap for Semiconductors. One potential replacement technology is resistance change memory based on solid electrolytes and a number of significant research and development efforts are already underway. The lowering of the resistance is attained by the reduction of ions in a relatively high resistivity electrolyte to form a conducting bridge between the electrodes. The resistance is returned to the high value via the application of a reverse bias that results in the breaking of the conducting pathway. Germanium chalcogenides and Ag-Ge-S ternaries in particular possess good thermal processing characteristics while maintaining the necessary high ion mobility for rapid switching. Thermally diffused copper in deposited SiO2 also is of interest, as thermal stability in excess of 600°C and commonly used constituents makes this material system compatible with the widest range of back-end-of-line processes. This paper details some of the developments in the understanding of the materials used in solid electrolyte resistance change devices and presents a short review of the electrical characteristics of devices based on Ag-Ge-S and Cu-Si-O electrolytes.
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Smith, Ryan Scott, C. J. Uchibori, P. S. Ho, and T. Nakamura. "Critical and Sub-critical Debonding in Nano-clustering Porous Low-k Films." MRS Proceedings 914 (2006). http://dx.doi.org/10.1557/proc-0914-f02-10.
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AbstractVery few porous low-k dielectric materials meet the basic requirements for integration into the back end of the line (BEOL) metallization. According to the International Technology Roadmap for Semiconductors, 2005, candidates for the 45 nm node need a k<2.2 and a minimum adhesion strength of 5 J/m2. Recently, a low-k dielectric material was developed, called nano-clustered silica (NCS). It is a spin-on glass with k<2.3. NCS is constitutively porous, with a micro- and mesopore size of ~2.8 nm. The first reported adhesion strength of this material was 10+ J/m2. We investigated the nature of the adhesive strength of NCS by critical and sub-critical fracture and Fourier Transform IR Spectroscopy (FTIR). The four-point bend technique and a mixed-mode double cantilever beam technique were employed. The sub-critical crack growth studies were performed in humid environments and ambient temperatures. Different post-treatments were used on NCS to achieve different molecular structure, as measured with FTIR. A correlation between molecular structure and critical adhesion energy was found. Atomistic parameters were calculated from the sub-critical crack growth data. A dependency of fracture behavior on post-treatment and, therefore, structure was observed.