Relevant bibliographies by topics / Intrinsic voltage gain

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Intrinsic voltage gain'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Intrinsic voltage gain"

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Buhler, Rudolf T., Renato Giacomini, and João Antonio Martino. "Influence of Fin Shape and Temperature on Conventional and Strained MuGFETs’ Analog Parameters." Journal of Integrated Circuits and Systems 6, no. 2 (2011): 94–101. http://dx.doi.org/10.29292/jics.v6i2.344.

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This work evaluates two important technological variations of Triple-Gate FETs: the use of strained silicon and the occurrence of non-rectangular body cross-section. The anaysis is focused on the electrical parameters for analog applications, and covers a temperature range from 150 K to 400 K. The comparison of the intrinsic voltage gain between the different trapezoidal fin shapes showed that the fin shape can have a major role in some analog parameters than the use of the strained silicon technology, helping to improve those parameters under certain circumstances. The highest intrinsic volta
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Zhang, Nuo, Yi Rao, Nuo Xu, Ayden Maralani, and Albert P. Pisano. "Characterization of 4H-SiC Bipolar Junction Transistor at High Temperatures." Materials Science Forum 778-780 (February 2014): 1013–16. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.1013.

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In this work, a 4H-Silicon Carbide (SiC) Bipolar Junction Transistor (BJT) capable of operating at high temperatures up to 673 K is demonstrated. Comprehensive characterization including current gain, early voltage, and intrinsic voltage gain was performed. At elevated temperatures, although the current gain of the device is reduced, the intrinsic voltage gain increases to 5900 at 673 K, suggesting 4H-SiC BJT has the potential to be used as a voltage amplifier at extremely high temperatures.
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Rodrigues, Michele, Milene Galeti, Nadine Collaert, Eddy Simoen, Cor Claeys, and João Antonio Martino. "SOI n- and pMuGFET devices with different TiN metal gate thickness and crystallographic orientation of the sidewalls." Journal of Integrated Circuits and Systems 7, no. 2 (2012): 107–12. http://dx.doi.org/10.29292/jics.v7i2.362.

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This work presents an analysis of SOI p- and nMuGFET devices with different TiN metal gate electrode thickness for rotated and standard structures.Thinner TiN metal gate allows achieving a higher intrinsic voltage gain in spite of the reduced variation observed of the gm/IDS characteristics. This effect can be attributed to the increased Early voltage values observed for thinner TiN metal gate. Even with the larger mobility of the rotated nMuGFET devices when compared with the standard ones, the larger output conductance degradation resulted in an almost similar intrinsic voltage gain. P-chann
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Patel, Ameera X., Naomi Murphy, and Denis Burdakov. "Tuning Low-Voltage-Activated A-Current for Silent Gain Modulation." Neural Computation 24, no. 12 (2012): 3181–90. http://dx.doi.org/10.1162/neco_a_00373.

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Modulation of stimulus-response gain and stability of spontaneous (unstimulated) firing are both important for neural computation. However, biologically plausible mechanisms that allow these distinct functional capabilities to coexist in the same neuron are poorly defined. Low-threshold, inactivating (A-type) K+ currents (IA) are found in many biological neurons and are historically known for enabling low-frequency firing. By performing simulations using a conductance-based model neuron, here we show that biologically plausible shifts in IA conductance and inactivation kinetics produce dissoci
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Perina, Welder Fernandes, Vanessa Cristina Pereira Silva, Joao Antonio Martino, Paula Ghedini Der Agopian, Eddy Simoen, and Anabela Veloso. "Intrinsic Voltage Gain of Stacked GAA Nanosheet MOSFETs Operating at High Temperatures." ECS Meeting Abstracts MA2020-01, no. 24 (2020): 1395. http://dx.doi.org/10.1149/ma2020-01241395mtgabs.

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Perina, Welder Fernandes, Vanessa Cristina Pereira Silva, Joao Antonio Martino, Paula Ghedini Der Agopian, Eddy Simoen, and Anabela Veloso. "Intrinsic Voltage Gain of Stacked GAA Nanosheet MOSFETs Operating at High Temperatures." ECS Transactions 97, no. 5 (2020): 65–69. http://dx.doi.org/10.1149/09705.0065ecst.

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Assalti, Rafael, Denis Flandre, and Michelly De Souza. "Influence of Geometrical Parameters on the DC Analog Behavior of the Asymmetric Self-Cascode FD SOI nMOSFETs." Journal of Integrated Circuits and Systems 13, no. 2 (2018): 1–7. http://dx.doi.org/10.29292/jics.v13i2.15.

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This paper assesses the DC analog performance of a composite transistor named Asymmetric Self-Cascode structure, which is formed by two Fully Depleted SOI nMOSFETs connected in series with shortened gates. The influence of geometrical parameters, such as different channel widths and lengths on the transistors at source and drain sides is evaluated through three-dimensional numerical simulations, which have been firstly adjusted to the experimental measurements. The transconductance, output conductance, Early voltage and intrinsic voltage gain have been used as figure of merit to explore the ad
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NIRANJAN, VANDANA, ASHWANI KUMAR, and SHAIL BALA JAIN. "COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS." Journal of Circuits, Systems and Computers 23, no. 08 (2014): 1450108. http://dx.doi.org/10.1142/s0218126614501084.

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In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal a
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Pandey, Himadri, Jorge-Daniel Aguirre-Morales, Satender Kataria, et al. "Enhanced Intrinsic Voltage Gain in Artificially Stacked Bilayer CVD Graphene Field Effect Transistors." Annalen der Physik 529, no. 11 (2017): 1700106. http://dx.doi.org/10.1002/andp.201700106.

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Rodrigues, Michele, Milene Galeti, Joao A. Martino, et al. "Larger Intrinsic Voltage Gain Achieved with UTBOX SOI Devices and Thin Silicon Film." ECS Transactions 44, no. 1 (2019): 25–31. http://dx.doi.org/10.1149/1.3694292.

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Dissertations / Theses on the topic "Intrinsic voltage gain"

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Andrade, Maria Glória Caño de. "Estudo de transistores de porta tripla de corpo." Universidade de São Paulo, 2012. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-10062013-150025/.

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O objetivo principal deste trabalho é o estudo de transistores MuGFETs de porta tripla de Corpo de canal tipo-n com e sem a aplicação da configuração DTMOS. Este estudo será realizado através de simulações numéricas tridimensionais e por caracterizações elétricas. A corrente de dreno, a transcondutância, a resistência, a tensão de limiar, a inclinação de sublimiar e a Redução da Barreira Induzida pelo Dreno (DIBL) serão analisadas em modo DTMOS e em configuração de polarização convencional. Importantes figuras de mérito para o desempenho analógico como transcondutância-sobre-corrente de dreno,
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Books on the topic "Intrinsic voltage gain"

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Wright, A. G. The Photomultiplier Handbook. Oxford University Press, 2017. http://dx.doi.org/10.1093/oso/9780199565092.001.0001.

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This handbook is aimed at helping users of PMTs who are faced with the challenge of designing sensitive light detectors for scientific and industrial purposes. The raison d’être for photomultipliers (PMTs) stems from four intrinsic attributes: large detection area, high, and noiseless gain, and wide bandwidth. Detection involves a conversion process from photons to photoelectrons at the photocathode. Photoelectrons are subsequently collected and increased in number by the action of an incorporated electron multiplier. Photon detection, charge multiplication, and many PMT applications are stati
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Book chapters on the topic "Intrinsic voltage gain"

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Jespers, Paul G. A. "Sizing the Intrinsic Gain Stage." In The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits. Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-47101-3_1.

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Jespers, Paul G. A. "The Real Intrinsic Gain Stage." In The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits. Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-47101-3_6.

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Conference papers on the topic "Intrinsic voltage gain"

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Perina, Welder F., Joao A. Martino, and Paula G. D. Agopian. "Intrinsic Voltage Gain and Unit-Gain Frequency of Omega-Gate Nanowire SOI MOSFETs." In 2019 34th Symposium on Microelectronics Technology and Devices (SBMicro). IEEE, 2019. http://dx.doi.org/10.1109/sbmicro.2019.8919278.

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Martino, M. D. V., F. S. Neves, P. G. D. Agopian, et al. "Early voltage and intrinsic voltage gain in vertical nanowire-TFETs as a function of temperature." In 2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS). IEEE, 2014. http://dx.doi.org/10.1109/iccdcs.2014.7016154.

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Agopian, P. G. D., J. A. Martino, R. Rooyackers, et al. "Intrinsic voltage gain of Line-TFETs and comparison with other TFET and MOSFET architectures." In 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS). IEEE, 2016. http://dx.doi.org/10.1109/ulis.2016.7440040.

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Bordallo, C., J. Martino, P. Agopian, et al. "Impact of InxGa1−x composition and source Zn diffusion temperature on intrinsic voltage gain in InGaAs TFETs." In 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). IEEE, 2016. http://dx.doi.org/10.1109/s3s.2016.7804393.

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