Dissertations / Theses on the topic 'Inverter Fed Induction Motor Drives'

A distributed power system (DPS) is made up of several subsystems. For example, a two-stage distributed power system is made of a source subsystem consisting of line conditioners and a load subsystem consisting of loads. Motor drives used as a load subsystem form an important type of load in distributed power system applications. The input impedance of the load subsystem is an important factor in designing and analyzing the performance and stability of a distributed power system. In this thesis, a typical three-phase inverter-fed ac motor drive is modeled, analyzed and the input impedance characteristics are studied for the first time. Motor drives are found to have unique input impedance characteristics due to their electromechanical nature. The influence of these characteristics on the distributed power system are analyzed. The unique interaction problems that these characteristics lead to are studied. It is shown that a distributed power system designed without taking into account the unique input impedance characteristics of motors might suffer from performance degradation or might even become unstable. Design guidelines to avoid this situation in a distributed power system that uses motor drives as a load subsystem are developed and presented.
Master of Science

Induction motors are usually fed by voltage source inverters. In some cases, it is necessary to increase the speed of the motor beyond the rated speed. This could be done by increasing the supply voltage (which is not always possible) or by field weakening. Field weakening algorithms are desirable since the current and the voltage of the motor cannot exceed the rated values. However, the range of the controlled speed is limited because of the limitation of the input voltage of the inverter. In this project, considering the limitation of current and voltage, the fundamentals of the field weakening in induction motor are reviewed. Th motor performance is evaluated under a variable range of the input DC voltage. A three-phase boost converter is used to regulate the input DC voltage of the inverter. In fact, when the requested voltage of the control algorithm is greater than the producible voltage of the inverter, the input DC voltage of the inverter is increased by the boost converter. The performance of this drive is evaluated in terms of current, torque and speed of induction motor. Besides, the efficiency of the drive is discussed.

The use of variable frequency drives in centrifugal pump applications has raised the question of how to select a drive. Clogging obstacles in waste water applications create unknown transient loads for the pump system. A sudden load increase occurrence can clog the pump if the drive cannot supply enough current to reach the motor’s torque demand. In order to select a suitable drive, an empirical approach has been implemented, investigating three different drives. Results have shown that selecting a drive with the highest possible overload capabilities, even if for a short time is most suitable. Operation in vector speed control gives the most reliable operation if an automatic parameter tuning is performed by the drive.
Användningen av frekvensomriktare i centrifugalpumpar har väckt fr ågan om hur en omriktare skall väljas. Igensättande objekt i avloppsvatten kan ge upphov till transienta laster i pumpsystemen. En oförutsedd lastökning kan sätta igen pumpen om frekvensomriktaren inte kan förse motorn tillräckligt med ström för att möta momentbehovet. För att välja en lämplig omriktare har ett empiriskt tillvägag ångssätt valts i en undersökning av tre olika omriktare. Resultat har visat att det är lämpligast att välja en omriktare med högst överbelastningskapacitet, även om under en kort tid. Vektor hastighetskontroll är metoden som ger stabil körning om omriktaren f ått automatiskt ställa in motorparametrarna.

In high power induction motor drives, the switching frequency of the inverter is quite low due to the high losses in the power devices. Real-time PWM strategies, which result in reduced harmonic distortion under low switching frequencies and have maximum possible DC bus utilisation, are developed for such drives in the present work. The space vector approach is taken up for the generation of synchronised PWM waveforms with 3-Phase Symmetry, Half Wave Symmetry and Quarter Wave Symmetry, required for high-power drives. Rules for synchronisation and the waveform symmetries are brought out. These rules are applied to the conventional and modified forms of space vector modulation, leading to the synchronised conventional space vector strategy and the Basic Bus Clamping Strategy-I, respectively. Further, four new synchronised, bus-clamping PWM strategies, namely Asymmetric Zero-Changing Strategy, Boundary Sampling Strategy-I, Basic Bus Clamping Strategy-II and Boundary Sampling Strategy-II, are proposed. These strategies exploit the flexibilities offered by the space vector approach like double-switching of a phase within a subcycle, clamping of two phases within a subcycle etc. It is shown that the PWM waveforms generated by these strategies cannot be generated by comparing suitable 3-phase modulating waves with a triangular carrier wave. A modified two-zone approach to overmodulation is proposed. This is applied to the six synchronised PWM strategies, dealt with in the present work, to extend the operation of these strategies upto the six-step mode. Linearity is ensured between the magnitude of the reference and the fundamental voltage generated in the whole range of modulation upto the six-step mode. This is verified experimentally. A suitable combination of these strategies leads to a significant reduction in the harmonic distortion of the drive at medium and high speed ranges over the conventional space vector strategy. This reduction in harmonic distortion is demonstrated, theoretically as well as experimentally, on a constant V/F drive of base frequency 50Hz for three values of maximum switching frequency of the inverter, namely 450Hz, 350Hz and 250Hz. Based on the notion of stator flux ripple, analytical closed-form expressions are derived for the harmonic distortion due to the different PWM strategies. The values of harmonic distortion, computed based on these analytical expressions, compare well with those calculated based on Fourier analysis and those measured experimentally.

In high power induction motor drives, the switching frequency of the inverter is quite low due to the high losses in the power devices. Real-time PWM strategies, which result in reduced harmonic distortion under low switching frequencies and have maximum possible DC bus utilisation, are developed for such drives in the present work. The space vector approach is taken up for the generation of synchronised PWM waveforms with 3-Phase Symmetry, Half Wave Symmetry and Quarter Wave Symmetry, required for high-power drives. Rules for synchronisation and the waveform symmetries are brought out. These rules are applied to the conventional and modified forms of space vector modulation, leading to the synchronised conventional space vector strategy and the Basic Bus Clamping Strategy-I, respectively. Further, four new synchronised, bus-clamping PWM strategies, namely Asymmetric Zero-Changing Strategy, Boundary Sampling Strategy-I, Basic Bus Clamping Strategy-II and Boundary Sampling Strategy-II, are proposed. These strategies exploit the flexibilities offered by the space vector approach like double-switching of a phase within a subcycle, clamping of two phases within a subcycle etc. It is shown that the PWM waveforms generated by these strategies cannot be generated by comparing suitable 3-phase modulating waves with a triangular carrier wave. A modified two-zone approach to overmodulation is proposed. This is applied to the six synchronised PWM strategies, dealt with in the present work, to extend the operation of these strategies upto the six-step mode. Linearity is ensured between the magnitude of the reference and the fundamental voltage generated in the whole range of modulation upto the six-step mode. This is verified experimentally. A suitable combination of these strategies leads to a significant reduction in the harmonic distortion of the drive at medium and high speed ranges over the conventional space vector strategy. This reduction in harmonic distortion is demonstrated, theoretically as well as experimentally, on a constant V/F drive of base frequency 50Hz for three values of maximum switching frequency of the inverter, namely 450Hz, 350Hz and 250Hz. Based on the notion of stator flux ripple, analytical closed-form expressions are derived for the harmonic distortion due to the different PWM strategies. The values of harmonic distortion, computed based on these analytical expressions, compare well with those calculated based on Fourier analysis and those measured experimentally.

This thesis is focused on a novel agricultural technique for orchard cultivations that allows to perform automatic and fossil fuel free cultivation operations. More specifically, the aim of this thesis work is to study and implement the electric traction system and control the vehicle that performs the automatic operations. Starting from the analysis of each single component of the traction system, the control of the mobile platform will be then performed. After a first control of the mobile platform in no load conditions, the implementation of the dynamic model will be performed in the Simulink environment. Different simulations representing typical operational missions will be performed to have a real idea concerning the behaviour of the traction system and the energy consumption of this solution. Finally, the obtained results will be analysed for the future implementation of the mobile platform on the field.

Due to the ruggedness, reliability and low maintenance required, small inverter-fed induction motors (1.5 kW to 25 kW) have earned a reputation and are utilized more and more frequently in industry for variable speed applications. The applied voltage and current waveforms are generally quite non-sinusoidal and polluted with higher time harmonic components. The higher time harmonics affect the electrical and mechanical performance significantly, and adverse effects are investigated. Literature on the effect of higher time harmonics is reviewed. Recommendations referring to various aspects under non-sinusoidal excitation are made when installing inverter-fed induction motors. Different inverter supplies (6-Pulse Square Wave voltage source inverter (VSI), PWM VSI and sinusoidal excitation) are used with a small 3-Phase, 3-kW squirrel cage induction motor, configured under synchronous characteristic Vᵣ/50 and subsynchronous characteristic Vᵣ/87. The respective voltage and current frequency spectrums of the excitation source are analyzed and the harmonic content determined. Performance executed under identical operating respectively and results are compared with pure sinusoidal (fundamental) excitation. tests are conditions respect to To determine the electrical performance the efficiency, power factor, temperature rise of the stator and induced shaft voltages were analyzed. The mechanical performance under inverter operation was analyzed by measuring the torque, torque pulsations, critical speeds and resonance frequencies of frame vibrations and torque oscillations as well as vibrations in x-, y-, and z-direction of the inverter-fed induction machine. Consequences of time harmonics on the induction motor and system are discussed. Conclusions on the effect of time harmonics and performance of different inverter types compared to sinusoidal excitation are drawn and are theoretically summarized and justified. Summary in English and German. Bibliography: pages 148-154.

Induction machine drives with various configurations are getting a lot of attention in several industrial applications. Due to this increasing demand in industrial applications, the significance of developing effective control approaches for obtaining a high dynamic performance from the induction machine drives became essential. Up to the present time, the control of induction machine drives using power converters has been based on the principle of mean value, using pulse width modulation with linear controllers in a cascaded structure. Recent research works have demonstrated that it is possible to use Predictive Control to control induction machine drives with the use of power converters, without using modulators and linear controllers. This new approach will have a strong impact on control in power electronics in coming decades. The advantages of Predictive Control are noticed through the ability to consider a multi-objective case within the model, easy inclusion of non-linearities within the model, simple treatment of system constraints, easy of digital implementation, and flexibility of including modifications and extension of control horizons according to the required applications. Upon this, the research presented in this thesis concerns with developing different control topologies for various configurations of induction machine drives based on finite control set model predictive control (FCS-MPC) principle, which actuates directly the switch states of the voltage source inverter (VSI). In addition, for enhancing the robustness of the induction machine drives, different sensorless approaches are utilized and tested for validations. The first topology of induction machine drives that has been studied is the induction motor (IM) drive. An effective model predictive direct torque control (MP DTC) approach is used to control the torque and stator flux of the motor through the utilization of an effective cost function, through which the understanding and comparing implementation variants and studying convergence and stability issues can be easily investigated. The speed sample effect on the control variants and overall performance of the proposed MP DTC is analyzed, which enables the understanding of the real base principle of DTC, as well as why and when it works well. Two different sensorless procedures for estimating the speed and rotor position are used by the proposed MP DTC approach; the first utilizes a model reference adaptive system (MRAS) observer, while the other exploits the prediction step during the implementation of proposed MP DTC to get the speed information through performing a linear extrapolation of the speed values starting from the last two estimated samples. Extensive simulation and experimental tests have been carried out to validate the effectiveness of both sensorless approaches in achieving precise tracking of speed commands for a wide range of variations. For enhancing the robustness of proposed MP DTC, the stator flux as a control variable is replaced with controlling the flow of the reactive power through the induction motor drive. As the reactive power is a measured quantity compared with the estimated value of stator flux, thus, the sensitivity of the control against parameters variation is limited, and this confirmed through the obtained results from both simulation and experimental tests. In addition, an effective alternative approach to the MP DTC is presented, which based on controlling the instantaneous values of the active and reactive powers of the IM drive based on model predictive principle, instead of controlling the torque and flux as in MP DTC. This technique has the advantage that all controlled variables are became measured quantities (active and reactive powers), thus the estimation problems that commonly present in classic DTC schemes are effectively limited. For the last two control approaches (MP DTC reactive power control, and MP IPCactive and reactive power control), the sensorless that utilizes the predictive feature is also adopted. Obtained results via simulation and experiments confirm the feasibility of the two alternatives control procedures in obtaining a robust dynamic response of IM drive. To limit the accompanied ripple contents in the controlled values of electromagnetic torque and stator flux of induction motor, an effective ripple reduction technique has been presented. The technique is based on the derivation of the optimal value for the weighting factor (w_f) used in the cost function. A detailed mathematical derivation of the optimal value of w_f is introduced based on the analysis of torque and flux ripples behaviors. The proposed ripple reduction technique has been validated via simulation utilizing Matlab/Simulink software, and experimentally tested using a fast control prototyping dSpace 1104 board. In addition, the prediction step based sensorless approach is adopted during implementation. The performance of the IM drive using the proposed approach is compared with the results obtained from MP DTC approach that uses an arbitrary value of w_f. The comparison confirms the validity of the proposed ripple reduction procedure in reducing the ripple contents in the controlled variables while preserving the permissible computation burdens during the implementation. The FCS-MPC principle is also utilized to control the current of induction motor as an alternative to classic field oriented control (FOC), the proposed model predictive current control (MPCC) approach belongs to the class of the hysteresis predictive control (for limiting the switching frequency) as the MPCC is triggered by the exceeding of the error of a given threshold. In addition, a sensorless drive is achieved by including an effective Luenberger observer (LO) for precise estimation of rotor flux vector together with stator current, speed and load torque. The stator currents are estimated to eliminate the accompanied noise in their values when they are directly measured, thus the currents noise during prediction is limited. An effective pole placement procedure for the selection of observer gains has been adopted. The procedure is based on shifting the poles of the observer to the left of the motor poles in the complex (s-plane) with low imaginary part, so that the stability of the observer is enhanced for wide speed range. The feasibility of the sensorless MPCC for IM drive is confirmed through the obtained simulation and experimental results. The second topology of induction machine drives that has been studied is the doubly fed induction motor (DFIM) drive. An effective model predictive direct torque control (MP DTC) algorithm is developed for controlling the torque and rotor flux of DFIM drive. In addition, an effective sensorless approach is presented, which estimates the speed and rotor position in an explicit way without the need for involving the flux in the estimation process, thus the effect of parameters variation on the overall performance of the sensorless observer is effectively limited, this has been approved through the obtained results that are performed for a wide speed range from sub-synchronous to super-synchronous speed operation. During the operation, the stator resistance and magnetizing inductance values are changed from their original values to study the variation effect on the observer performance. Matlab/Simulink software and a prototyping dSpace 1104 control board are used to validate the effectiveness of proposed sensorless MP DTC approach through simulation and experiments, respectively. The results proof the robustness of the proposed sensorless approach and its ability to achieve precise estimation of the speed and rotor position. The third topology of induction machine drives that has been studied is the doubly fed induction generator (DFIG). A detailed analytical derivation for the proposed model predictive direct power control (MP DPC) approach for DFIG is presented, which as a sequence considered as a transposed control approach from the MP DTC used before for doubly fed induction motor (DFIM). A sensorless approach based on model reference adaptive system (MRAS) observer is adopted for estimating the speed and rotor position. Both simulation using Matlab/Simulink software and experimental test using a prototyping dSpace 1104 control board have tested the dynamic performance of the drive. Obtained results affirm the feasibility of the proposed MP DPC approach in achieving a decoupled control of active and reactive powers for DFIG. In summary, it can be said that the proposed model predictive control approaches have proved their ability in achieving high dynamic performance for different topologies of induction machine drives. In addition, the proposed sensorless techniques have confirmed their effectiveness for a wide range of speed variations. All of this are approved and validated through extensive simulation and experimental tests.
Gli azionamenti con machine ad induzione (macchine asincrone nelle loro varie configurazioni), stanno riacquistando molta attenzione in diverse applicazioni industriali. A causa di questo crescente interesse applicativo, è diventato di essenziale importanza lo sviluppo di efficaci tecniche di controllo per ottenere dagli azionamenti in questione elevate prestazioni dinamiche. Fino ad oggi, il controllo degli azionamenti con macchina a induzione alimentati da convertitori di potenza è basato sul “principio del valore medio” delle grandezze in commutazione, utilizzando la modulazione di larghezza di impulsi con controllori lineari in una struttura a cascata. Recenti ricerche hanno dimostrato che è possibile utilizzare il Controllo Predittivo per controllare gli azionamenti con macchina a induzione, con l'utilizzo di convertitori di potenza senza utilizzare modulatori e controllori lineari. Questo nuovo approccio avrà un forte impatto sul controllo dell'elettronica di potenza nei prossimi decenni. I vantaggi del Controllo Predittivo derivano dalla possibilità di perseguire problemi multi-obiettivo, di includere facile le non linearità all'interno del modello, di trattare in modo semplice i vincoli di sistema, nonché dalla facilità di implementazione digitale e dalla flessibilità di includere modifiche ed estensioni al controllo secondo le applicazioni richieste. Inlinea con tutto ciò, la ricerca presentata in questa tesi riguarda lo sviluppo di diverse topologie di controllo per varie configurazioni di azionamenti con macchine a induzione, basate sul principio di Controllo Predittivo a modello con insieme finito degli stati di controllo (Finite Control Set Model Predictive Control - FCS-MPC), che definisce direttamente l’assetto dell'inverter di tensione (VSI). Inoltre, per aumentare la robustezza degli azionamenti, vengono proposti e sperimentati diversi approcci senza sensori elettromeccanici (sensorless). La prima topologia studiata di azionamenti con macchina a induzione (IM) è l'azionamento con motore a gabbia. Il controllo diretto di coppia (DTC) è aggiornato in termini di controllo predittivo a modello (MP DTC) e usato per controllare la coppia e il flusso statorico attraverso l'utilizzo di una efficace funzione di costo attraverso la quale è anche possibile facilmente comprendere e confrontare le varianti di implementazione e studiare i problemi di convergenza e di stabilità. Viene analizzato l'effetto della velocità sulle diverse versioni di controllo e sulle prestazioni complessive del MP DTC proposto; ciò consente di comprendere appieno il principio del DTC, nonché perché e quando esso funzioni bene. Vengono utilizzate due diverse procedure di stima della posizione e della velocità del rotore nel MP DTC proposto; il primo utilizza uno stimatore adattivo con modello di riferimento (MRAS), mentre l'altro sfrutta la stessa fase di predizione del MP DTC proposto per ottenere le informazioni sulla velocità effettuando infine un'estrapolazione lineare dei valori di velocità a partire dagli ultimi due campioni stimati. Sono state eseguite numerose prove in simulazione e sperimentali per convalidare l'efficacia di entrambi gli approcci sensorless nell’ottenere un preciso inseguimento del comando di velocità per una vasta gamma di situazioni. Per migliorare la robustezza del MP DTC proposto rispetto alle variazioni parametriche, il controllo del flusso dello statore viene sostituito con quello della potenza reattiva assorbita dal motore ad induzione; di conseguenza la sensibilità del controllo alle variazioni dei parametri è limitata e ciò è confermato attraverso i risultati ottenuti sia dalla simulazione che dalle prove sperimentali. Inoltre, viene presentato un ulteriore efficace approccio alternativo per il MP DTC, basato sul principio del controllo predittivo a modello dei valori istantanei delle potenze attive e reattive dell'azionamento, invece di controllare la coppia e il flusso come nell’usuale MP DTC. Questa variante ha il vantaggio che tutte le variabili controllate sono divenute quantità misurate (potenze attive e reattive) e quindi i problemi di stima comunemente presenti nei classici schemi DTC sono efficacemente limitati. Per gli ultimi due approcci di controllo (controllo di coppia e di potenza reattiva e controllo di potenza attiva e reattiva) viene anche adottato la stima della velocità rotorica che sfrutta la funzione predittiva del controllo. I risultati ottenuti attraverso la simulazione e la sperimentazione confermano la fattibilità delle due procedure alternative di controllo per ottenere una risposta dinamica robusta dell’azionamento con IM. Per limitare il ripple che accompagna gli andamenti controllati della coppia e del flusso statorico del motore, è stata presentata una tecnica efficace di riduzione della sua ampiezza. La tecnica è basata sull’impiego di un valore ottimale per il fattore di ponderazione w_f utilizzato nella funzione di costo per sommare i due contributi che la definiscono. Viene introdotta una derivazione matematica dettagliata del valore ottimale di w_f attraverso l'analisi dei comportamenti dell’ondulazione di coppia e del flusso. La tecnica di riduzione del ripple proposta è stata verificata tramite la simulazione usando il software Matlab/Simulink e sperimentalmente utilizzando la scheda di rapida prototipazione del controllo dSpace 1104. Ancora, l'implementazione adotta l'approccio sensorless basato sulla fase di predizione. Le prestazioni dell’azionamento con IM utilizzando quest’ultimo approccio proposto sono confrontate con i risultati ottenuti con l'approccio MP DTC che utilizza invece un valore arbitrario di w_f. Il confronto conferma la validità della procedura di riduzione del ripple nelle variabili controllate mantenendo nel contempo gli oneri di calcolo entro i limiti consentiti per l'implementazione. Il principio FCS-MPC è anche utilizzato per controllare la corrente del motore di induzione come alternativa al controllo classico ad orientamento di campo (Field Oriented Control -FOC). L'approccio proposto di controllo di corrente di tipo predittivo (Model Predictive Current Control - MPCC) appartiene alla classe del controllo predittivo ad isteresi (per limitare il frequenza di commutazione) in quanto il MPCC viene attivato dal raggiungimento dell’errore di corrente di una determinata soglia. In questo caso, la caratteristica sensorless dell’azionamento è ottenuta includendo un efficace osservatore Luenberger (LO) per una precisa stima del vettore del flusso del rotore insieme alla coppia di carico e alla velocità. È stata adottata una efficace procedura di allocazione dei poli per la selezione dei guadagni dell'osservatore; la procedura si basa sul posizionamento dei poli dell'osservatore a sinistra di quelli del motore nel complesso (piano di s) con una ridotta parte immaginaria, in modo che la stabilità dell'osservatore sia migliorata in un'ampia gamma di velocità. La fattibilità dell'azionamento sensorless con MPCC è ancora confermata attraverso la simulazione e i risultati sperimentali. La seconda topologia degli azionamenti con macchina a induzione che è stata studiata è l'azionamento con motore ad anelli con rotore alimentato da invertitore e statore da rete (Doubly Fed Induction Motor DFIM). È stato sviluppato un efficace algoritmo predittivo a modello (MP DTC) per il controllo dinamico della coppia e del flusso di rotore dell'azionamento DFIM. Inoltre, viene presentato un approccio efficace di soluzione sensorless che valuta la velocità e la posizione del rotore in modo esplicito senza la necessità di coinvolgere la stima del flusso nel processo di predizione; di conseguenza l'effetto delle variazioni dei parametri sulle prestazioni complessive dell'osservatore di posizione e velocità è sensibilmente limitato. Questo è stato provato attraverso i risultati ottenuti con test eseguiti in un'ampia gamma di velocità, dal sub-sincronismo a velocità super-sincrona. Durante l'operazione, la resistenza dello statore e i valori di induttanza di magnetizzazione sono stati modificati rispetto ai valori reali per studiare l'effetto di variazioni parametriche sulle prestazioni dell'osservatore. Anche in questo caso, il software Matlab/Simulink e una scheda di controllo dSpace 1104 sono stati utilizzati per convalidare l'efficacia dell'approccio sensorless del MP DTC per l’azionamento. I risultati dimostrano la robustezza del controllo sensorless proposto e la sua capacità di ottenere una precisa stima della posizione e della velocità del rotore. La terza topologia di azionamenti con macchina a induzione che è stata studiata è quella del generatore ad induzione con rotore avvolto (DFIG) e invertitore sul rotore. Viene presentata una derivazione analitica dettagliata del controllo predittivo diretto di potenza (MP DPC) per DFIG, che trasferisce ed estende l’approccio di controllo del MP DTC citato prima per il motore a induzione a doppia alimentazione (DFIM). Una soluzione sensorless ancora basata sull'osservatore adattivo a modello di riferimento (MRAS) è adottato per stimare la velocità e la posizione del rotore. Sia le simulazioni usando il software Matlab/Simulink che i test sperimentali utilizzando la scheda dSpace 1104 hanno mostrato le elevate prestazioni dinamiche dell'azionamento. I risultati ottenuti confermano la fattibilità del metodo MP DPC proposto per ottenere un controllo disaccoppiato di potenze attive e reattive per DFIG. In sintesi, si può dire che l'utilizzo proposto del controllo predittivo a modello ha dimostrato la sua capacità di ottenere elevate prestazioni dinamiche per le diverse topologie degli azionamenti con macchina ad induzione considerati. Inoltre, le tecniche sensorless proposte hanno confermato la loro efficacia per una vasta gamma di velocità. Tutto questo è stato verificato e validato attraverso una vasta attività analisi simulativa e di sperimentazione in laboratorio.

AC motors are largely used in a wide range of modern systems, from household appliances to automated industry applications such as: ventilations systems, fans, pumps, conveyors and machine tool drives. Inverters are widely used in industrial and commercial applications due to the growing need for speed control in ASD systems. Fast switching transients and the common mode voltage, in interaction with parasitic capacitive couplings, may cause many unwanted problems in the ASD applications. These include shaft voltage and leakage currents. One of the inherent characteristics of Pulse Width Modulation (PWM) techniques is the generation of the common mode voltage, which is defined as the voltage between the electrical neutral of the inverter output and the ground. Shaft voltage can cause bearing currents when it exceeds the amount of breakdown voltage level of the thin lubricant film between the inner and outer rings of the bearing. This phenomenon is the main reason for early bearing failures. A rapid development in power switches technology has lead to a drastic decrement of switching rise and fall times. Because there is considerable capacitance between the stator windings and the frame, there can be a significant capacitive current (ground current escaping to earth through stray capacitors inside a motor) if the common mode voltage has high frequency components. This current leads to noises and Electromagnetic Interferences (EMI) issues in motor drive systems. These problems have been dealt with using a variety of methods which have been reported in the literature. However, cost and maintenance issues have prevented these methods from being widely accepted. Extra cost or rating of the inverter switches is usually the price to pay for such approaches. Thus, the determination of cost-effective techniques for shaft and common mode voltage reduction in ASD systems, with the focus on the first step of the design process, is the targeted scope of this thesis. An introduction to this research – including a description of the research problem, the literature review and an account of the research progress linking the research papers – is presented in Chapter 1. Electrical power generation from renewable energy sources, such as wind energy systems, has become a crucial issue because of environmental problems and a predicted future shortage of traditional energy sources. Thus, Chapter 2 focuses on the shaft voltage analysis of stator-fed induction generators (IG) and Doubly Fed Induction Generators DFIGs in wind turbine applications. This shaft voltage analysis includes: topologies, high frequency modelling, calculation and mitigation techniques. A back-to-back AC-DC-AC converter is investigated in terms of shaft voltage generation in a DFIG. Different topologies of LC filter placement are analysed in an effort to eliminate the shaft voltage. Different capacitive couplings exist in the motor/generator structure and any change in design parameters affects the capacitive couplings. Thus, an appropriate design for AC motors should lead to the smallest possible shaft voltage. Calculation of the shaft voltage based on different capacitive couplings, and an investigation of the effects of different design parameters are discussed in Chapter 3. This is achieved through 2-D and 3-D finite element simulation and experimental analysis. End-winding parameters of the motor are also effective factors in the calculation of the shaft voltage and have not been taken into account in previous reported studies. Calculation of the end-winding capacitances is rather complex because of the diversity of end winding shapes and the complexity of their geometry. A comprehensive analysis of these capacitances has been carried out with 3-D finite element simulations and experimental studies to determine their effective design parameters. These are documented in Chapter 4. Results of this analysis show that, by choosing appropriate design parameters, it is possible to decrease the shaft voltage and resultant bearing current in the primary stage of generator/motor design without using any additional active and passive filter-based techniques. The common mode voltage is defined by a switching pattern and, by using the appropriate pattern; the common mode voltage level can be controlled. Therefore, any PWM pattern which eliminates or minimizes the common mode voltage will be an effective shaft voltage reduction technique. Thus, common mode voltage reduction of a three-phase AC motor supplied with a single-phase diode rectifier is the focus of Chapter 5. The proposed strategy is mainly based on proper utilization of the zero vectors. Multilevel inverters are also used in ASD systems which have more voltage levels and switching states, and can provide more possibilities to reduce common mode voltage. A description of common mode voltage of multilevel inverters is investigated in Chapter 6. Chapter 7 investigates the elimination techniques of the shaft voltage in a DFIG based on the methods presented in the literature by the use of simulation results. However, it could be shown that every solution to reduce the shaft voltage in DFIG systems has its own characteristics, and these have to be taken into account in determining the most effective strategy. Calculation of the capacitive coupling and electric fields between the outer and inner races and the balls at different motor speeds in symmetrical and asymmetrical shaft and balls positions is discussed in Chapter 8. The analysis is carried out using finite element simulations to determine the conditions which will increase the probability of high rates of bearing failure due to current discharges through the balls and races.

Les travaux développés durant cette thèse concernent la détection et l'identification des défauts simples et multiples d'ouverture des transistors dans un convertisseur statique associé à une machine asynchrone. Pour aborder cette problématique, nous avons commencé par l'analyse des potentialités, des faiblesses et des incertitudes des techniques qui ont initiés notre démarche. Ensuite, nous avons présenté deux méthodologies permettant d'analyser les performances du moteur asynchrone en présence des défauts dans une ou plusieurs cellules de commutation. Cette étude préliminaire nous a permis ainsi de proposer deux nouvelles stratégies de diagnostic sans référence basées sur l'approche signal. Les signaux électriques (courants ou tensions) disponibles à la sortie du convertisseur statique sont utilisés pour alimenter le processus de diagnostic. La première stratégie retenue est basée sur l'analyse qualitative des tensions de sortie entre phases du convertisseur et des signaux de commande appliqués aux transistors pendant les instants de commutation. Grâce à une représentation instantanée de ces grandeurs, à l'échelle de la période de découpage, nous avons pu mettre en évidence des caractéristiques favorables à la détection des défauts simples et multiples d'ouverture des transistors. L'implémentation pratique de cette première approche a été réalisée au moyen d'une technologie analogique permettant ainsi de minimiser le temps de retard à la détection jusqu'à quelques dizaines de microsecondes
The main goal of this thesis concerns the detection and identification of simple and multiple open-circuit faults in voltage source inverters (VSIs)-fed induction motor drives. In first step, the potentialities, the weaknesses as well as the uncertainties of the previously published works have been discussed. The second step was dedicated to the study of the inverter faults impact on the induction motor. For this purpose, we have proposed two methodologies permitting the characterization of the electromagnetic torque behaviour as well as the electric variables of the induction motor under the open- and short-circuit faults. These preliminary studies allowed to propose two novel signal-based approaches for open-circuit fault diagnosis in voltage source inverter. The measured outputs inverter voltages and currents have been used as the input quantities for the fault detection and identification (FDI) process. The first approach consists in analyzing the pulse-width modulation (PWM) switching signals and the line-to-line voltage levels during the switching times, under both healthy and faulty operating conditions. For this purpose, we have adopted an instantaneous representation of these variables, which permits their analysis over one switching period. The fault diagnosis scheme is achieved using simple analog device. This circuit allows an accurate single and multiple faults diagnosis, and a minimization of the fault detection time which becomes about a few tens of microseconds

The inverter dead-time is integral to the safety of a voltage source inverter (VSI). Dead-time is introduced between the complementary gating signals of the top and bottom switches in each VSI leg to prevent shoot-through fault. This thesis reports and investigates dead-time induced sub-harmonic oscillations in open-loop induction motor drives of different power levels, under light-load conditions. The thesis develops mathematical models that help understand and predict the oscillatory behaviour of such motor drives due to dead-time act. Models are also developed to study the impact of under-compensation and over-compensation of dead-time act on stability. The various models are validated through extensive simulations and experimental results. The thesis also proposes and validates active damping schemes for mitigation of such sub-harmonic oscillations. The thesis reports high-amplitude sub-harmonic oscillations in the stator current, torque and speed of a 100-kW open-loop induction motor drive in the laboratory, operating under no-load. Experimental studies, carried out on 22-kW, 11-kW, 7.5-kW and 3.7-kW open-loop induction motor drives, establish the prevalence of dead-time induced sub-harmonic oscillations in open-loop motor drives of different power levels. An experimental procedure is established for systematic study of this phenomenon in industrial drives. This procedure yields the operating region, if any, where the motor drive is oscillatory. As a first step towards understanding the oscillatory behaviour of the motor drive, a mathematical model of the VSI is derived in a synchronously revolving reference frame (SRF), incorporating the of dead-time on the inverter output voltage. This leads to a modified dynamic model of the inverter-fed induction motor in the SRF, inclusive of the dead-time act. While the rotor dynamic equations are already non-linear, dead-time is found to introduce nonlinearities in the stator dynamic equations as well. The nonlinearities in the modified dynamic model make even the steady solution non-trivial. Under steady conditions, the dead-time can be modelled as the drop across an equivalent resistance (Req0) in the stator circuit. A precise method to evaluate the equivalent resistance Req0 and a simple method to arrive at the steady solution are proposed and validated. For the purpose of stability analysis, a small-signal model of the drive is then derived by linearizing the non-linear dynamic equations of the motor drive, about a steady-state operating point. The proposed small-signal model shows that dead-time contributes to different values of equivalent resistances along the q-axis and d-axis and also to equivalent cross-coupling reactance’s that appear in series with the stator windings. Stability analysis performed using the proposed model brings out the region of oscillatory behaviour (or region of small-signal instability) of the 100-kW motor drive on the voltage versus frequency (V- f) plane, considering no-load. The oscillatory region predicted by the small-signal analysis is in good agreement with simulations and practical observations for the 100-kW motor drive. The small-signal analysis is also able to predict the region of oscillatory behaviour of an 11-kW motor drive, which is con consumed by simulations and experiments. The analysis also predicts the frequencies of sub-harmonic oscillations at different operating points quite well for both the drives. Having the validity of the small-signal analysis at different power levels, this analytical procedure is used to predict the regions of oscillatory behaviour of 2-pole, 4-pole, 6-pole and 8-pole induction motors rated 55 kW and 110 kW. The impact of dead-time on inverter output voltage has been studied widely in literature. This thesis studies the influence of dead-time on the inverter input current as well. Based on this study, the dynamic model of the inverter fed induction motor is extended to include the dc-link dynamics as well. Simulation results based on this extended model tally well with the experimentally measured dc-link voltage and stator current waveforms in the 100-kW drive. Dead-time compensation may be employed to mitigate the dead-time and oscillatory behaviour of the drive. However, accurate dead-time compensation is challenging to achieve due to various factors such as delays in gate drivers, device switching characteristics, etc. Effects of under-compensation and over-compensation of dead time are investigated in this thesis. Under-compensation is shown to result in the same kind of oscillatory behaviour as observed with dead-time, but the fundamental frequency range over which such oscillations occur is reduced. On the other hand, over-compensation of dead-time effect is shown to result in a different kind of oscillatory behaviour. These two types of oscillatory behaviour due to under- and over-compensation, respectively, are distinguished and demonstrated by analyses, simulations and experiments on the 100-kW drive. To mitigate the oscillatory behaviour of the drive, an active damping scheme is proposed. This scheme emulates the effect of an external inductor in series with the stator winding. A small-signal model is proposed for an induction motor drive with the proposed active damping scheme. Simulations and experiments on the 100-kW drive demonstrate effective mitigation of light-load instability with this active damping scheme. In the above inductance emulation scheme, the emulated inductance is seen by the sub-harmonic components, fundamental component as well as low-order harmonic components of the motor current. Since the emulated inductance is also seen by the fundamental component, there is a fundamental voltage drop across the emulated inductance, leading to reduced co-operation of the induction motor. Hence, an improved active damping scheme is proposed wherein the emulated inductance is seen only by the sub-harmonic and low-order harmonic components. This is achieved through appropriate altering in the synchronously revolving domain. The proposed improved active damping scheme is shown to mitigate the sub-harmonic oscillation effectively without any reduction in flux.

The inverter dead-time is integral to the safety of a voltage source inverter (VSI). Dead-time is introduced between the complementary gating signals of the top and bottom switches in each VSI leg to prevent shoot-through fault. This thesis reports and investigates dead-time induced sub-harmonic oscillations in open-loop induction motor drives of different power levels, under light-load conditions. The thesis develops mathematical models that help understand and predict the oscillatory behaviour of such motor drives due to dead-time act. Models are also developed to study the impact of under-compensation and over-compensation of dead-time act on stability. The various models are validated through extensive simulations and experimental results. The thesis also proposes and validates active damping schemes for mitigation of such sub-harmonic oscillations. The thesis reports high-amplitude sub-harmonic oscillations in the stator current, torque and speed of a 100-kW open-loop induction motor drive in the laboratory, operating under no-load. Experimental studies, carried out on 22-kW, 11-kW, 7.5-kW and 3.7-kW open-loop induction motor drives, establish the prevalence of dead-time induced sub-harmonic oscillations in open-loop motor drives of different power levels. An experimental procedure is established for systematic study of this phenomenon in industrial drives. This procedure yields the operating region, if any, where the motor drive is oscillatory. As a first step towards understanding the oscillatory behaviour of the motor drive, a mathematical model of the VSI is derived in a synchronously revolving reference frame (SRF), incorporating the of dead-time on the inverter output voltage. This leads to a modified dynamic model of the inverter-fed induction motor in the SRF, inclusive of the dead-time act. While the rotor dynamic equations are already non-linear, dead-time is found to introduce nonlinearities in the stator dynamic equations as well. The nonlinearities in the modified dynamic model make even the steady solution non-trivial. Under steady conditions, the dead-time can be modelled as the drop across an equivalent resistance (Req0) in the stator circuit. A precise method to evaluate the equivalent resistance Req0 and a simple method to arrive at the steady solution are proposed and validated. For the purpose of stability analysis, a small-signal model of the drive is then derived by linearizing the non-linear dynamic equations of the motor drive, about a steady-state operating point. The proposed small-signal model shows that dead-time contributes to different values of equivalent resistances along the q-axis and d-axis and also to equivalent cross-coupling reactance’s that appear in series with the stator windings. Stability analysis performed using the proposed model brings out the region of oscillatory behaviour (or region of small-signal instability) of the 100-kW motor drive on the voltage versus frequency (V- f) plane, considering no-load. The oscillatory region predicted by the small-signal analysis is in good agreement with simulations and practical observations for the 100-kW motor drive. The small-signal analysis is also able to predict the region of oscillatory behaviour of an 11-kW motor drive, which is con consumed by simulations and experiments. The analysis also predicts the frequencies of sub-harmonic oscillations at different operating points quite well for both the drives. Having the validity of the small-signal analysis at different power levels, this analytical procedure is used to predict the regions of oscillatory behaviour of 2-pole, 4-pole, 6-pole and 8-pole induction motors rated 55 kW and 110 kW. The impact of dead-time on inverter output voltage has been studied widely in literature. This thesis studies the influence of dead-time on the inverter input current as well. Based on this study, the dynamic model of the inverter fed induction motor is extended to include the dc-link dynamics as well. Simulation results based on this extended model tally well with the experimentally measured dc-link voltage and stator current waveforms in the 100-kW drive. Dead-time compensation may be employed to mitigate the dead-time and oscillatory behaviour of the drive. However, accurate dead-time compensation is challenging to achieve due to various factors such as delays in gate drivers, device switching characteristics, etc. Effects of under-compensation and over-compensation of dead time are investigated in this thesis. Under-compensation is shown to result in the same kind of oscillatory behaviour as observed with dead-time, but the fundamental frequency range over which such oscillations occur is reduced. On the other hand, over-compensation of dead-time effect is shown to result in a different kind of oscillatory behaviour. These two types of oscillatory behaviour due to under- and over-compensation, respectively, are distinguished and demonstrated by analyses, simulations and experiments on the 100-kW drive. To mitigate the oscillatory behaviour of the drive, an active damping scheme is proposed. This scheme emulates the effect of an external inductor in series with the stator winding. A small-signal model is proposed for an induction motor drive with the proposed active damping scheme. Simulations and experiments on the 100-kW drive demonstrate effective mitigation of light-load instability with this active damping scheme. In the above inductance emulation scheme, the emulated inductance is seen by the sub-harmonic components, fundamental component as well as low-order harmonic components of the motor current. Since the emulated inductance is also seen by the fundamental component, there is a fundamental voltage drop across the emulated inductance, leading to reduced co-operation of the induction motor. Hence, an improved active damping scheme is proposed wherein the emulated inductance is seen only by the sub-harmonic and low-order harmonic components. This is achieved through appropriate altering in the synchronously revolving domain. The proposed improved active damping scheme is shown to mitigate the sub-harmonic oscillation effectively without any reduction in flux.

This thesis deals with modeling, simulation and implementation of Load Commutated SCR based current source Inverter (LCI) fed squirrel cage induction motor drive with sinusoidal voltage and sinusoidal current. In the proposed system, the induction motor is fed by an LCI. A three level diode clamped voltage source inverter (VSI) is connected at the motor terminal with ac chokes connected in series with it. The VSI currents are controlled in such a manner that it injects the reactive current demanded by the induction motor and the LCI for successful commutation of the SCRs in the LCI. Additionally, it absorbs the harmonic frequency currents to ensure that the induction motor draws sinusoidal current. As a result, the nature of the motor terminal voltage is also sinusoidal. The concept of load commutation of the SCRs in the LCI feeding an induction motor load is explained with necessary waveforms and phasor diagrams. The necessity of reactive compensation by the active filter connected at the motor terminal for the load commutation of the thyristors, is elaborated with the help of analytical equations and phasor diagrams. The requirement of harmonic compensation by the same active filter to achieve sinusoidal motor current and motor voltage, is also described. Finally, to achieve the aforementioned induction motor drive, the VA ratings of the active filter (VSI) and the CSI with respect to VA rating of the motor, are determined theoretically. The proposed drive scheme is simulated under idealized condition. Simulation results show good steady state and dynamic response of the drive system. Load commutation of the SCRs in the LCI and the sinusoidal profile of motor current and voltage, have been demonstrated. As in LCI fed synchronous motor drives, a special mode of operation is required to run up the induction motor from standstill. As the SCRs of the LCI are load commutated, they need motor terminal voltages for commutation. At standstill these voltages are zero. So, a starting strategy has been proposed and adopted to start the motor with the aid of the current controlled VSI to accelerate until the motor terminal voltages are high enough for the commutation of the SCRs in the LCI. The proposed drive is implemented on an experimental setup in the laboratory. The IGBT based three level diode clamped VSI has been fabricated following the design of the standard module in the laboratory. A generalized digital control platform is also developed using a TMS320F2407A DSP. Two, three phase thyristor bridges with necessary firing pulse circuits have been used as the phase controlled rectifier and the LCI respectively. Appropriate protection scheme for such a drive is developed and adopted to operate the drive. Relevant experimental results are presented. They are observed to be in good agreement with the simulation results. The effect of capacitors connected at the output of the LCI in the commutation process of the SCRs in the LCI is studied and analyzed. From the analysis, it is understood that the capacitors form a parallel resonating pair with filter inductor and the motor leakage inductance, which results in an undesired oscillation in the terminal voltage during each of the commutation intervals leading to commutation failure. So, in the final system, the capacitors are removed to eliminate any chance of commutation failure of the SCRs in the LCI. It is shown by experiment that the commutation of the SCRs takes place reliably in the absence of the capacitors also. The commutation process is studied and analyzed without the capacitors to understand the motor terminal voltage waveform of the experimental results.

This thesis deals with modeling, simulation and implementation of Load Commutated SCR based current source Inverter (LCI) fed squirrel cage induction motor drive with sinusoidal voltage and sinusoidal current. In the proposed system, the induction motor is fed by an LCI. A three level diode clamped voltage source inverter (VSI) is connected at the motor terminal with ac chokes connected in series with it. The VSI currents are controlled in such a manner that it injects the reactive current demanded by the induction motor and the LCI for successful commutation of the SCRs in the LCI. Additionally, it absorbs the harmonic frequency currents to ensure that the induction motor draws sinusoidal current. As a result, the nature of the motor terminal voltage is also sinusoidal. The concept of load commutation of the SCRs in the LCI feeding an induction motor load is explained with necessary waveforms and phasor diagrams. The necessity of reactive compensation by the active filter connected at the motor terminal for the load commutation of the thyristors, is elaborated with the help of analytical equations and phasor diagrams. The requirement of harmonic compensation by the same active filter to achieve sinusoidal motor current and motor voltage, is also described. Finally, to achieve the aforementioned induction motor drive, the VA ratings of the active filter (VSI) and the CSI with respect to VA rating of the motor, are determined theoretically. The proposed drive scheme is simulated under idealized condition. Simulation results show good steady state and dynamic response of the drive system. Load commutation of the SCRs in the LCI and the sinusoidal profile of motor current and voltage, have been demonstrated. As in LCI fed synchronous motor drives, a special mode of operation is required to run up the induction motor from standstill. As the SCRs of the LCI are load commutated, they need motor terminal voltages for commutation. At standstill these voltages are zero. So, a starting strategy has been proposed and adopted to start the motor with the aid of the current controlled VSI to accelerate until the motor terminal voltages are high enough for the commutation of the SCRs in the LCI. The proposed drive is implemented on an experimental setup in the laboratory. The IGBT based three level diode clamped VSI has been fabricated following the design of the standard module in the laboratory. A generalized digital control platform is also developed using a TMS320F2407A DSP. Two, three phase thyristor bridges with necessary firing pulse circuits have been used as the phase controlled rectifier and the LCI respectively. Appropriate protection scheme for such a drive is developed and adopted to operate the drive. Relevant experimental results are presented. They are observed to be in good agreement with the simulation results. The effect of capacitors connected at the output of the LCI in the commutation process of the SCRs in the LCI is studied and analyzed. From the analysis, it is understood that the capacitors form a parallel resonating pair with filter inductor and the motor leakage inductance, which results in an undesired oscillation in the terminal voltage during each of the commutation intervals leading to commutation failure. So, in the final system, the capacitors are removed to eliminate any chance of commutation failure of the SCRs in the LCI. It is shown by experiment that the commutation of the SCRs takes place reliably in the absence of the capacitors also. The commutation process is studied and analyzed without the capacitors to understand the motor terminal voltage waveform of the experimental results.

碩士
國立東華大學
電機工程學系
100
The thesis aims at development of a DSP controller-based voltage-fed inverter for both induction motor (IM) drive and permanent magnet synchronous motor (PMSM) drive. In the inverter development, the hardware circuit setup contains that 1) an intelligent power electronic module(IPM) with six IGBT switches and three-phase full-bridge rectifier is used for pulse-width modulation(PWM) devices, 2) three hall-effect current sensors for detecting three-phase ac current of the motor drives are adopted, 3) three differential amplifiers for encoder signals are adopted, 4) optical isolation circuits are used for PWM triggering signals to the IPM, and 5) a TMS320F2812-chip DSP development kit is taken for the control algorithm implementation. In the control algorithm development, the main techniques are as follows: 1) a space-vector PWM and field orientation control are used, 2) a proportional-integral-derivative (PID) speed controller is designed, and 3) a simple start-up scheme for PMSM drive is adopted. To verify the validity of the development, experimental results from a prototype DSP controller-based voltage-fed inverter are illustrated in the thesis.

Multi-level inverters play a significant role in high power drive systems for induction motors. Interest in multi-level inverters started with the three-level, neutral point clamped (NPC) inverter. Now there are many topologies for higher number of levels such as the, flying capacitor and cascaded H-bridge etc. The advantage of multi-level inverters is the reduced voltage stress on the switching devices, lower dv/dt and lower harmonic content. The voltage space vector structure in a multi-level inverter has a hexagonal periphery similar to that in a two-level inverter. In the over-modulation region in multi-level inverters, there is the presence of lower order harmonics such as 5th and 7th in the output voltage, and this can be avoided by using a voltage space vector scheme with more than six polygonal voltage space vectors such as 12, 18, 24 etc. These polygonal voltage space vectors can be generated by using multi-level inverter topologies, by cascading two-level inverter structures with asymmetric DC-links. This thesis deals with the development of 12-sided and 18-sided polygonal voltage space vector schemes for induction motor drives. With the 12-sided polygonal structure, all the 5th and 7th harmonic orders and 6n±1, n=1, 3, 5.. are absent throughout the modulation range, and in the 18-sided voltage space vector scheme, 5th, 7th, 11th and 13th harmonics are absent throughout the modulation range. With the absence of the low order frequencies in the proposed polygonal space vector structures, high frequency PWM schemes are not needed for voltage control. This is an advantage over conventional schemes. Also, due to the absence of lower order harmonics throughout the modulation range, special compensated synchronous reference frame PI controllers are not needed in current controlled vector control schemes in over-modulation. In this thesis a method is proposed for generating 12-sided polygonal voltage space vectors for an induction motor fed from one side. A cascaded combination of three two-level inverters is used with asymmetrical DC-links. A simple space vector PWM scheme based only on the sampled reference phase amplitudes are used for the inverter output voltage control. The reference space vector is sampled at different sampling rates depending on the frequency of operation. The number of samples in a sector is chosen to keep the overall switching frequency around 1kHz, in order to minimize switching losses. The voltage space vectors that make up the two sides of the sector in which the reference vector lies, are time averaged using volt-sec balance, to result in the reference vector. In the proposed 12-sided PWM scheme all the harmonics of the order 6n±1, n=1, 3, 5... are eliminated from the phase voltage, throughout the modulation range. In multi-level inverters steps are taken to eliminate common-mode voltage. Common-mode voltage is defined as one third of the sum of the three pole voltages of the inverter for a three phase system. Bearings are found to fail prematurely in drives with fast rising voltage pulses and high frequency switching. The alternating common-mode voltage generated by the PWM inverter contributes to capacitive couplings from stator body to rotor body. This generates motor shaft voltages causing bearing currents to flow from rotor to stator body and then to the ground. There can be a flashover between the bearing races. Also a phenomenon termed EDM (Electro-discharge machining) effect occurs and may damage the bearings. Common-mode voltage has to be eliminated in order to overcome these effects. In multi-level inverters redundancy of space vector locations is used to eliminate common-mode voltages. In the present thesis a 12-sided polygonal voltage space vector based inverter with an open-end winding induction motor is proposed, in which the common-mode voltage variation at the poles of the inverter is eliminated. In this scheme, there is a three-level inverter on each side of the open-end winding of the induction motor. The three-level inverter is made by cascading two, two-level inverters with unequal DC-link voltages. Appropriate space vectors are selected from opposite sides such that the sum of the pole voltages on each side is a constant. Also during the PWM operation when the zero vector is applied, identical voltage levels are used on both sides of the open-end windings, in order to make the phase voltages zero, while the common-mode voltage is kept constant. This way, common-mode voltage variations are eliminated throughout the modulation range by appropriately selecting the voltage vectors from opposite ends. In this method all the harmonics of 6n±1, n=1, 3, 5.. and triplen orders are eliminated. In the 12-sided polygonal voltage space vector methods, the 11th and 13th harmonics though attenuated are not eliminated. In the 18-sided polygonal voltage space vector method the 11th and 13th harmonics are eliminated along with the 5th and 7th harmonics. This scheme consists of an open-end winding induction motor fed from one side by a two-level inverter and the other side by a three-level inverter comprising of two cascaded two-level inverters. Asymmetric DC-links of a particular ratio are present. The 12-sided and 18-sided polygonal voltage space vector methods have been first simulated using SIMULINK and then verified experimentally on a 1.5kW induction motor drive. In the simulation as well as the experimental setup the starting point is the generation of the three reference voltages v, vB and vC . A method for determining the sector in which the reference vector lies by comparing the values of the scaled sampled instantaneous reference voltages is proposed. For the reference vector lying in a sector between the two active vectors, the first vector is to be kept on for T1 duration and the second vector for T2 duration. These timing durations can be found from the derived formula, using the sampled instantaneous values of the reference voltages and the sector information. From the pulse widths and the sector number, the voltage level at which a phase in the inverter has to be maintained is uniquely determined from look-up tables. Thus, once the pole voltages are determined the phase voltages can be easily determined for simulation studies. By using a suitable induction motor model in the simulation, the effect of the PWM scheme on the motor current can be easily obtained. The simulation studies are experimentally verified on a 1.5kW open-end winding induction motor drive. A V/f control scheme is used for the study of the drive scheme for different speeds of operation. A DSP (TMS320LF2407A) is used for generating the PWM signals for variable speed operation. The 12-sided polygonal voltage space vector scheme with the motor fed from a single side has a simple power bus structure and it is also observed that the pole voltage is clamped to zero for 30% of the time duration of one cycle of operation. This will increase the overall efficiency. The proposed scheme eliminates all harmonics of the order 6n±1, n=1, 3, 5…for the complete modulation range. The 12-sided polygonal voltage space vector scheme with common-mode elimination requires the open-end winding configuration of the induction motor. Two asymmetrical DC-links are required which are common to both sides. The leg of the high voltage inverter is seen to be switched only for 50% duration in a cycle of operation. This will also reduce switching losses considerably. The proposed scheme not only eliminates all harmonics of the order 6n±1, n=1, 3, 5…for the complete modulation range, but also maintains the common-mode voltage on both sides constant. The common-mode voltage variation is eliminated. This eliminates bearing currents and shaft voltages which can damage the motor bearings. In the 18-sided polygonal voltage space vector based inverter, the 11th and 13th harmonics are eliminated along with the 5th and 7th. Here also an open-end winding induction motor is used, with a two-level inverter on one side and a three-level inverter on the other side. A pole of the two-level inverter is at clamped to zero voltage for 50% of the time and a pole of the three-level inverter is clamped to zero for 30% of the time for one cycle of operation. The 18-sided polygonal voltage space vectors show the highest maximum peak fundamental voltage in the 18-step mode of 0.663Vdc compared to 0.658Vdc in the 12-step mode of the 12-sided polygonal voltage space vector scheme and 0.637Vdc in the six-step mode of a two-level inverter or conventional multi-level inverter (where Vdc is the radius of the space vector polygon). Though the schemes proposed are verified on a low power laboratory prototype, the principle and the control algorithm development are general in nature and can be easily extended to induction motor drives for high power applications.

Multi-level inverters play a significant role in high power drive systems for induction motors. Interest in multi-level inverters started with the three-level, neutral point clamped (NPC) inverter. Now there are many topologies for higher number of levels such as the, flying capacitor and cascaded H-bridge etc. The advantage of multi-level inverters is the reduced voltage stress on the switching devices, lower dv/dt and lower harmonic content. The voltage space vector structure in a multi-level inverter has a hexagonal periphery similar to that in a two-level inverter. In the over-modulation region in multi-level inverters, there is the presence of lower order harmonics such as 5th and 7th in the output voltage, and this can be avoided by using a voltage space vector scheme with more than six polygonal voltage space vectors such as 12, 18, 24 etc. These polygonal voltage space vectors can be generated by using multi-level inverter topologies, by cascading two-level inverter structures with asymmetric DC-links. This thesis deals with the development of 12-sided and 18-sided polygonal voltage space vector schemes for induction motor drives. With the 12-sided polygonal structure, all the 5th and 7th harmonic orders and 6n±1, n=1, 3, 5.. are absent throughout the modulation range, and in the 18-sided voltage space vector scheme, 5th, 7th, 11th and 13th harmonics are absent throughout the modulation range. With the absence of the low order frequencies in the proposed polygonal space vector structures, high frequency PWM schemes are not needed for voltage control. This is an advantage over conventional schemes. Also, due to the absence of lower order harmonics throughout the modulation range, special compensated synchronous reference frame PI controllers are not needed in current controlled vector control schemes in over-modulation. In this thesis a method is proposed for generating 12-sided polygonal voltage space vectors for an induction motor fed from one side. A cascaded combination of three two-level inverters is used with asymmetrical DC-links. A simple space vector PWM scheme based only on the sampled reference phase amplitudes are used for the inverter output voltage control. The reference space vector is sampled at different sampling rates depending on the frequency of operation. The number of samples in a sector is chosen to keep the overall switching frequency around 1kHz, in order to minimize switching losses. The voltage space vectors that make up the two sides of the sector in which the reference vector lies, are time averaged using volt-sec balance, to result in the reference vector. In the proposed 12-sided PWM scheme all the harmonics of the order 6n±1, n=1, 3, 5... are eliminated from the phase voltage, throughout the modulation range. In multi-level inverters steps are taken to eliminate common-mode voltage. Common-mode voltage is defined as one third of the sum of the three pole voltages of the inverter for a three phase system. Bearings are found to fail prematurely in drives with fast rising voltage pulses and high frequency switching. The alternating common-mode voltage generated by the PWM inverter contributes to capacitive couplings from stator body to rotor body. This generates motor shaft voltages causing bearing currents to flow from rotor to stator body and then to the ground. There can be a flashover between the bearing races. Also a phenomenon termed EDM (Electro-discharge machining) effect occurs and may damage the bearings. Common-mode voltage has to be eliminated in order to overcome these effects. In multi-level inverters redundancy of space vector locations is used to eliminate common-mode voltages. In the present thesis a 12-sided polygonal voltage space vector based inverter with an open-end winding induction motor is proposed, in which the common-mode voltage variation at the poles of the inverter is eliminated. In this scheme, there is a three-level inverter on each side of the open-end winding of the induction motor. The three-level inverter is made by cascading two, two-level inverters with unequal DC-link voltages. Appropriate space vectors are selected from opposite sides such that the sum of the pole voltages on each side is a constant. Also during the PWM operation when the zero vector is applied, identical voltage levels are used on both sides of the open-end windings, in order to make the phase voltages zero, while the common-mode voltage is kept constant. This way, common-mode voltage variations are eliminated throughout the modulation range by appropriately selecting the voltage vectors from opposite ends. In this method all the harmonics of 6n±1, n=1, 3, 5.. and triplen orders are eliminated. In the 12-sided polygonal voltage space vector methods, the 11th and 13th harmonics though attenuated are not eliminated. In the 18-sided polygonal voltage space vector method the 11th and 13th harmonics are eliminated along with the 5th and 7th harmonics. This scheme consists of an open-end winding induction motor fed from one side by a two-level inverter and the other side by a three-level inverter comprising of two cascaded two-level inverters. Asymmetric DC-links of a particular ratio are present. The 12-sided and 18-sided polygonal voltage space vector methods have been first simulated using SIMULINK and then verified experimentally on a 1.5kW induction motor drive. In the simulation as well as the experimental setup the starting point is the generation of the three reference voltages v, vB and vC . A method for determining the sector in which the reference vector lies by comparing the values of the scaled sampled instantaneous reference voltages is proposed. For the reference vector lying in a sector between the two active vectors, the first vector is to be kept on for T1 duration and the second vector for T2 duration. These timing durations can be found from the derived formula, using the sampled instantaneous values of the reference voltages and the sector information. From the pulse widths and the sector number, the voltage level at which a phase in the inverter has to be maintained is uniquely determined from look-up tables. Thus, once the pole voltages are determined the phase voltages can be easily determined for simulation studies. By using a suitable induction motor model in the simulation, the effect of the PWM scheme on the motor current can be easily obtained. The simulation studies are experimentally verified on a 1.5kW open-end winding induction motor drive. A V/f control scheme is used for the study of the drive scheme for different speeds of operation. A DSP (TMS320LF2407A) is used for generating the PWM signals for variable speed operation. The 12-sided polygonal voltage space vector scheme with the motor fed from a single side has a simple power bus structure and it is also observed that the pole voltage is clamped to zero for 30% of the time duration of one cycle of operation. This will increase the overall efficiency. The proposed scheme eliminates all harmonics of the order 6n±1, n=1, 3, 5…for the complete modulation range. The 12-sided polygonal voltage space vector scheme with common-mode elimination requires the open-end winding configuration of the induction motor. Two asymmetrical DC-links are required which are common to both sides. The leg of the high voltage inverter is seen to be switched only for 50% duration in a cycle of operation. This will also reduce switching losses considerably. The proposed scheme not only eliminates all harmonics of the order 6n±1, n=1, 3, 5…for the complete modulation range, but also maintains the common-mode voltage on both sides constant. The common-mode voltage variation is eliminated. This eliminates bearing currents and shaft voltages which can damage the motor bearings. In the 18-sided polygonal voltage space vector based inverter, the 11th and 13th harmonics are eliminated along with the 5th and 7th. Here also an open-end winding induction motor is used, with a two-level inverter on one side and a three-level inverter on the other side. A pole of the two-level inverter is at clamped to zero voltage for 50% of the time and a pole of the three-level inverter is clamped to zero for 30% of the time for one cycle of operation. The 18-sided polygonal voltage space vectors show the highest maximum peak fundamental voltage in the 18-step mode of 0.663Vdc compared to 0.658Vdc in the 12-step mode of the 12-sided polygonal voltage space vector scheme and 0.637Vdc in the six-step mode of a two-level inverter or conventional multi-level inverter (where Vdc is the radius of the space vector polygon). Though the schemes proposed are verified on a low power laboratory prototype, the principle and the control algorithm development are general in nature and can be easily extended to induction motor drives for high power applications.

Current-Controlled Pulse Width Modulated (CC-PWM) Voltage Source Inverters (VSIs) are extensively employed in high performance drives (HPD) because of the considerable advantages offered by them, such as, excellent dynamic response and inherent over-current protection, as compared to the voltage-controlled PWM (VC-PWM) VSIs. Amongst the different types of CC-PWM techniques, hysteresis current controllers offer significant simplicity in implementation. However, conventional type of hysteresis controllers (with independent comparators) suffers from some well-known drawbacks, such as, limit cycle oscillations (especially at lower speeds of operation of machine), overshoot in current error, generation of sub-harmonic components in the current, and random (non-optimum) switching of inverter voltage vectors. Common problems associated with the conventional, as well as current error space phasor based hysteresis controllers with fixed bands (boundary), are the wide variation of switching frequency in the fundamental output cycle and variation of switching frequency with the change in speed of the load motor. These problems cause increased switching losses in the inverter, non-optimum current ripple, excess harmonics in the load current and subsequent additional machine heating. A continuously varying parabolic boundary for the current error space phasor is proposed previously to get the switching frequency variation pattern of the output voltage of the hysteresis controller based PWM inverter similar to that of voltage controlled space vector PWM (VC SVPWM) based VSI. But the major problem associated with this technique is the requirement of two outer parabolas outside the current error space phasor boundary for the identification of sector change which gives rise to some switching frequency variations in one fundamental cycle and over the entire operating speed range. It also introduces 5th and 7th harmonic components in the voltage causing 5th and 7th harmonic currents in the induction motor. These harmonic currents causes 6th harmonic torque pulsations in the machine. This thesis proposes a new technique which replaces the outer parabolas and uses current errors along orthogonal axes for detecting the sector change, so that a fast and accurate detection of sector change is possible. This makes the voltage harmonic spectrum of the proposed hysteresis controller based inverter exactly matching with that of a constant switching frequency SVPWM based inverter. This technique uses the property that the current error along one of the orthogonal axis changes its direction during sector change. So the current error never goes outside the parabolic boundary as in the case of outer parabolas based sector change technique. So the proposed new technique for sector change eliminates the 5th and 7th harmonic components from the applied voltage and thus eliminates the 5th and 7th harmonic currents in the motor. So there will be no introduction of 6th harmonic torque pulsations in the motor. Using the proposed scheme for sector change and parabolic boundary for current error space phasor, simulation study was carried out using Matlab-Simulink. Simulation study showed that the switching frequency variations in a fundamental cycle and over the entire speed range of the machine upto six step mode operation is similar to that of a VC-SVPWM based VSI. The proposed hysteresis controller is experimentally verified on a 3.7 kW IM drive fed with a two-level VSI using vector control. The proposed current error space phasor based hysteresis controller providing constant switching frequency is completely implemented on the TI TMS320LF2812 DSP controller platform. The three-phase reference currents are generated depending on the frequency command and the controller is tested with drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and transient results of the proposed drive are presented in this thesis. This thesis also proposes a new hysteresis controller which eliminates parabolic boundary and replaces it with a simple online computation of the boundary. In this proposed new hysteresis controller the boundary computed in the present sampling interval is used for identifying next vector to be switched. This thesis gives a detailed mathematical explanation of how the boundary is computed and how it is used for selecting vector to be switched in a sector. It also explains how the sector in which stator voltage vector is present is determined. The most important part of this proposed hysteresis controller is the estimation of stator voltages along alpha and beta axes during active and zero vector periods. Estimation of stator voltages are carried out using current errors along alpha and beta axes and steady state equivalent circuit of induction motor. Using this estimated stator voltages along alpha and beta axes, instantaneous phase voltages are computed and used for finding individual voltage vector switching times. These switching times are used for the computation of hysteresis boundary for individual vectors. So the hysteresis boundary for individual vectors are exactly calculated and used for vector change detection, making phase voltage harmonic spectrum exactly similar to that of constant switching frequency VC SVPWM inverter. Sector change detection is very simple, since we have the estimated stator voltages along alpha and beta axes to give exact position of stator voltage vector. Simulation study to verify the steady state as well as transient performance of the proposed controller based VSI fed IM drive is carried out using Simulink tool box of Matlab Simulation Software. The proposed hysteresis controller is experimentally verified on a 3.7 kW IM drive fed with a two-level VSI using vector control. The proposed current error space phasor based hysteresis controller providing constant switching frequency profile for phase voltage is implemented on the TI TMS320LF2812 DSP controller platform. The three-phase reference currents are generated depending on the frequency command and the proposed hysteresis controller is tested with drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and transient results of the proposed drive are presented for different operating conditions.

Current-Controlled Pulse Width Modulated (CC-PWM) Voltage Source Inverters (VSIs) are extensively employed in high performance drives (HPD) because of the considerable advantages offered by them, such as, excellent dynamic response and inherent over-current protection, as compared to the voltage-controlled PWM (VC-PWM) VSIs. Amongst the different types of CC-PWM techniques, hysteresis current controllers offer significant simplicity in implementation. However, conventional type of hysteresis controllers (with independent comparators) suffers from some well-known drawbacks, such as, limit cycle oscillations (especially at lower speeds of operation of machine), overshoot in current error, generation of sub-harmonic components in the current, and random (non-optimum) switching of inverter voltage vectors. Common problems associated with the conventional, as well as current error space phasor based hysteresis controllers with fixed bands (boundary), are the wide variation of switching frequency in the fundamental output cycle and variation of switching frequency with the change in speed of the load motor. These problems cause increased switching losses in the inverter, non-optimum current ripple, excess harmonics in the load current and subsequent additional machine heating. A continuously varying parabolic boundary for the current error space phasor is proposed previously to get the switching frequency variation pattern of the output voltage of the hysteresis controller based PWM inverter similar to that of voltage controlled space vector PWM (VC SVPWM) based VSI. But the major problem associated with this technique is the requirement of two outer parabolas outside the current error space phasor boundary for the identification of sector change which gives rise to some switching frequency variations in one fundamental cycle and over the entire operating speed range. It also introduces 5th and 7th harmonic components in the voltage causing 5th and 7th harmonic currents in the induction motor. These harmonic currents causes 6th harmonic torque pulsations in the machine. This thesis proposes a new technique which replaces the outer parabolas and uses current errors along orthogonal axes for detecting the sector change, so that a fast and accurate detection of sector change is possible. This makes the voltage harmonic spectrum of the proposed hysteresis controller based inverter exactly matching with that of a constant switching frequency SVPWM based inverter. This technique uses the property that the current error along one of the orthogonal axis changes its direction during sector change. So the current error never goes outside the parabolic boundary as in the case of outer parabolas based sector change technique. So the proposed new technique for sector change eliminates the 5th and 7th harmonic components from the applied voltage and thus eliminates the 5th and 7th harmonic currents in the motor. So there will be no introduction of 6th harmonic torque pulsations in the motor. Using the proposed scheme for sector change and parabolic boundary for current error space phasor, simulation study was carried out using Matlab-Simulink. Simulation study showed that the switching frequency variations in a fundamental cycle and over the entire speed range of the machine upto six step mode operation is similar to that of a VC-SVPWM based VSI. The proposed hysteresis controller is experimentally verified on a 3.7 kW IM drive fed with a two-level VSI using vector control. The proposed current error space phasor based hysteresis controller providing constant switching frequency is completely implemented on the TI TMS320LF2812 DSP controller platform. The three-phase reference currents are generated depending on the frequency command and the controller is tested with drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and transient results of the proposed drive are presented in this thesis. This thesis also proposes a new hysteresis controller which eliminates parabolic boundary and replaces it with a simple online computation of the boundary. In this proposed new hysteresis controller the boundary computed in the present sampling interval is used for identifying next vector to be switched. This thesis gives a detailed mathematical explanation of how the boundary is computed and how it is used for selecting vector to be switched in a sector. It also explains how the sector in which stator voltage vector is present is determined. The most important part of this proposed hysteresis controller is the estimation of stator voltages along alpha and beta axes during active and zero vector periods. Estimation of stator voltages are carried out using current errors along alpha and beta axes and steady state equivalent circuit of induction motor. Using this estimated stator voltages along alpha and beta axes, instantaneous phase voltages are computed and used for finding individual voltage vector switching times. These switching times are used for the computation of hysteresis boundary for individual vectors. So the hysteresis boundary for individual vectors are exactly calculated and used for vector change detection, making phase voltage harmonic spectrum exactly similar to that of constant switching frequency VC SVPWM inverter. Sector change detection is very simple, since we have the estimated stator voltages along alpha and beta axes to give exact position of stator voltage vector. Simulation study to verify the steady state as well as transient performance of the proposed controller based VSI fed IM drive is carried out using Simulink tool box of Matlab Simulation Software. The proposed hysteresis controller is experimentally verified on a 3.7 kW IM drive fed with a two-level VSI using vector control. The proposed current error space phasor based hysteresis controller providing constant switching frequency profile for phase voltage is implemented on the TI TMS320LF2812 DSP controller platform. The three-phase reference currents are generated depending on the frequency command and the proposed hysteresis controller is tested with drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and transient results of the proposed drive are presented for different operating conditions.

This thesis deals with a new solution for medium voltage drives. Load Commutated Inverter (LCI) fed synchronous motor drive is a popular solution for high power drive applications. Though the induction machine is more rugged and cheaper compared to the synchronous machine, LCI fed induction motor drive solution is not available. The basic advantage of a synchronous machine over an induction machine is the fact that the synchronous machine can operate at leading power factor. Due to this property load commutation of SCR switches of the LCI is achievable for synchronous machine. On the contrary an induction machine always draws lagging power factor current; this makes it unsuitable as a drive motor for LCI technology. In this thesis a new LCI fed induction motor drive configuration is developed as an alternative for synchronous motor drives. A new variant of six phase induction motor is proposed in this context. The machine is named as Active Reactive Induction Machine (ARIM). The ARIM contains two sets of three-phase windings with isolated neutral. Both the windings have a common axis. One winding carries the active power and can be wound for higher voltage (say 11kV). The other winding supplies the total reactive power of the machine and can be wound for lower voltage (say 2.2 kV). The rotor is a standard squirrel cage. High power induction machines usually demand lesser magnitude of reactive power compared to the total power rating of the machine ( 20% ). Therefore excitation winding has a smaller fraction of the total machine rating compared to the power winding. A VSI with an LC filter supplies reactive power to the ARIM through the excitation winding and ensures leading power factor at the power winding. This is similar to the excitation control of the LCI fed synchronous machine. The direct VSI connection is possible due to the lower voltage rating for the excitation winding. In this way, the VSI voltage rating does not limit the highest motor voltage that can be handled. An LCI supplies the real power into the ARIM from the power winding. The LCI currents are quasi square wave in shape. Therefore they have rich low order harmonic content. They cause 6th and 12th harmonic torque pulsations in the machine. This is a problem for the LCI fed synchronous machine drive. In the proposed drive, the VSI can compensate these low frequency m.m.f. harmonics inside the machine air gap to remove torque pulsation and rotor harmonic losses. The advantage of the proposed topology is that no transformer is required to drive an 11kV machine. It is always desirable to feed sinusoidal voltage and current to both the power winding and the excitation winding. To address this problem, a second configuration is proposed. A low power three-level VSI is connected in shunt at the power winding with the proposed ARIM drive as discussed above. This VSI compensates the low frequency harmonic currents to achieve sinusoidal motor currents at the motor winding. This VSI acts as a shunt active filter and compensates for the lower order harmonics injected by the LCI. The proposed topologies have LC filters to maintain sinusoidal motor voltages and currents by absorbing the VSI switching frequency components. But the motor terminal voltage oscillates at system resonant frequency due to the presence of LC filters. These resonant components in the terminal voltages are required to be eliminated for smooth terminal voltages and safe load commutation of the thyristors. In this thesis a simple active damping method is proposed to mitigate these issues. The proposed topologies are experimentally verified with an ARIM with 415 V power winding and 220 V excitation winding. The control is carried out on a digital platform having a TMS 320LF 2407A DSP processor and an ALTERA CYCLONE FPGA processor. Results from the prototype experimental drive are presented to show the feasibility and performance of the proposed drive configurations.

This thesis deals with a new solution for medium voltage drives. Load Commutated Inverter (LCI) fed synchronous motor drive is a popular solution for high power drive applications. Though the induction machine is more rugged and cheaper compared to the synchronous machine, LCI fed induction motor drive solution is not available. The basic advantage of a synchronous machine over an induction machine is the fact that the synchronous machine can operate at leading power factor. Due to this property load commutation of SCR switches of the LCI is achievable for synchronous machine. On the contrary an induction machine always draws lagging power factor current; this makes it unsuitable as a drive motor for LCI technology. In this thesis a new LCI fed induction motor drive configuration is developed as an alternative for synchronous motor drives. A new variant of six phase induction motor is proposed in this context. The machine is named as Active Reactive Induction Machine (ARIM). The ARIM contains two sets of three-phase windings with isolated neutral. Both the windings have a common axis. One winding carries the active power and can be wound for higher voltage (say 11kV). The other winding supplies the total reactive power of the machine and can be wound for lower voltage (say 2.2 kV). The rotor is a standard squirrel cage. High power induction machines usually demand lesser magnitude of reactive power compared to the total power rating of the machine ( 20% ). Therefore excitation winding has a smaller fraction of the total machine rating compared to the power winding. A VSI with an LC filter supplies reactive power to the ARIM through the excitation winding and ensures leading power factor at the power winding. This is similar to the excitation control of the LCI fed synchronous machine. The direct VSI connection is possible due to the lower voltage rating for the excitation winding. In this way, the VSI voltage rating does not limit the highest motor voltage that can be handled. An LCI supplies the real power into the ARIM from the power winding. The LCI currents are quasi square wave in shape. Therefore they have rich low order harmonic content. They cause 6th and 12th harmonic torque pulsations in the machine. This is a problem for the LCI fed synchronous machine drive. In the proposed drive, the VSI can compensate these low frequency m.m.f. harmonics inside the machine air gap to remove torque pulsation and rotor harmonic losses. The advantage of the proposed topology is that no transformer is required to drive an 11kV machine. It is always desirable to feed sinusoidal voltage and current to both the power winding and the excitation winding. To address this problem, a second configuration is proposed. A low power three-level VSI is connected in shunt at the power winding with the proposed ARIM drive as discussed above. This VSI compensates the low frequency harmonic currents to achieve sinusoidal motor currents at the motor winding. This VSI acts as a shunt active filter and compensates for the lower order harmonics injected by the LCI. The proposed topologies have LC filters to maintain sinusoidal motor voltages and currents by absorbing the VSI switching frequency components. But the motor terminal voltage oscillates at system resonant frequency due to the presence of LC filters. These resonant components in the terminal voltages are required to be eliminated for smooth terminal voltages and safe load commutation of the thyristors. In this thesis a simple active damping method is proposed to mitigate these issues. The proposed topologies are experimentally verified with an ARIM with 415 V power winding and 220 V excitation winding. The control is carried out on a digital platform having a TMS 320LF 2407A DSP processor and an ALTERA CYCLONE FPGA processor. Results from the prototype experimental drive are presented to show the feasibility and performance of the proposed drive configurations.

Z-Source inverter is a one stage power converter and used for buck or boost the voltage without using additional dc-dc converter bridge. It uses a special network which connects main circuit and power supply, and hence providing special features which will not be achieved by using traditional current and voltage-source inverters, where capacitor and inductor arranged together in X-fashion. It provides voltage buck or boost properties and reduces voltage stress across capacitors and thereby increases efficiency of circuit. This topology finds many applications in renewable energy source where voltage varying from time to time. Actual speed of an induction motor can be sensed by connecting speed sensor which is compared with reference speed. During voltage changes and normal operating conditions it will provide effective speed control of drive. This paper presents performance characteristics of induction motor drives fed with ZSI. To make easy understanding of speed control of ZSI fed induction motor drive, V/F control with simple boost control PWM technique is used. A PI controller is used in this circuit which helps in running motor at reference speed. Simulation is done in MATLAB/ Simulink and Simulation results of induction motor drive with z-source inverter compared with traditional VSI fed induction motor drive which gives good performance at variable speed and torque characteristics.

碩士
國立臺灣科技大學
電機工程系
88
This thesis investigates the motor terminal overvoltage, ringing and common-mode voltage in pulse-width modulation (PWM) inverter-fed ac motor drive system where long leads are required. These phenomena may stress the motor winding insulation, and cause shaft voltage, bearing current, and conducted electromagnetic interference (EMI). Premature motor bearing failures and electronic equipment malfunctions have been reported to be directly related to bearing current and EMI. In this paper, parallel resistor, first-order and second-order shunt filter are designed to reduce the overvoltage and ringing at motor terminals, and methods to eliminate common-mode voltage using a three-level sinusoidal PWM inverter are presented. Simulation and experimental results are presented to verify the proposed filter design for 220-V PWM inverter-fed induction motor drive system with 10 meter lead lengths.

In DC to AC power conversion, voltage source inverters (VSI) based current controllers are usually preferred for today’s high performance AC drive which requires excellent dynamic and steady state performances at different transient and load conditions, with the additional advantages like inherent short circuit and over current protection. Out of different types of current controllers, hysteresis controllers are widely used due to their simplicity and ability to meet the requirements for a high performance AC drives. But the conventional hysteresis controllers suffers from wide variation of PWM switching frequency, overshoot in current errors, sub-harmonic components in the current waveform and non-optimum switching at different operating point of the drive system. To mitigate these problems, particularly to control the switching frequency variation, which is the root cause of all other problems, several methodologies like ramp comparison based controller, predictive current controller, etc. were proposed in the literature. But amplitude and phase offset error in the ramp comparison based controllers and complexities involved in the predictive controllers have limited the use of these controllers. Moreover, these type of controllers, which uses three separate and independently controlled tolerance band (sinusoidal type or adaptive) to control the 3-phase currents, shows limited dynamic responses and they are not simple to implement. To tackle the problem of controlling 3-phase currents simultaneously, space vector based hysteresis current controller is very effective as it combines the current errors of all the three phases as a single entity called current error space vector. It has a single controller’s logic with a hysteresis boundary for controlling this current error space vector. Several papers on space vector based hysteresis controllers for 2-level inverter with constant switching frequency have been published, but the application of the constant switching frequency based hysteresis current controllers for multi¬level inverter fed drive system, has not been addressed properly. Use of multi-level inverter in modern high performance drive for medium and high voltage levels is more prominent because of multi-level’s inherent advantages like good power quality, good electromagnetic compatibility (EMC), better DC link voltage utilization, reduced device voltage rating, so on. Even though some of the earlier works describe three-level space vector based hysteresis current controller techniques, they are specific to the particular level of inverters and does not demonstrate constant switching frequency of operation. This thesis proposes a novel approach where nearly constant switching frequency based hysteresis controller can be implemented for any general n-level inverter and it is also independent of inverter topology. In this work, varying parabolic boundary is used as the hysteresis current error boundary for controlling the current in a multi-level space vector structure. The computation of the parabolic boundary is accomplished offline and all the necessary boundary parameters at different operating points are stored in the look-up tables. The varying parabolic boundary for the multi-level space vector structure depends on the sampled reference phase voltage values which are estimated from stator current error information and then using the equivalent circuit model of induction motors. Here, a mapping technique is adopted to bring down all the three phase references to the inner- most carrier region, which results in mapping any outer triangular structure where tip of the voltage space vector is located, to one of the sectors of the inner most hexagon of the multi-level space vector structure. In this way, the required mapped sector information is easily found out to fix the correct orientation of the parabolic boundary in the space vector plane. This mapping technique simplifies the controller’s logic similar to that of a 2-level inverter. For online identification of the inverter switching voltage vectors constructing the present outer triangle of the multi-level space vector structure, the proposed controller utilizes the sampled phase voltage references. This identification technique is novel and also generic for any n-level inverter structure. This controller is having all the advantages of a space vector based hysteresis current controller and that of a multi-level inverter apart from having a nearly constant switching frequency spectrum similar to that of a voltage controlled space vector PWM (VC-SVPWM). Using the proposed controller, simulation study of a five-level inverter fed induction motor (IM) drive scheme, was carried out using Matlab-Simulink. Simulation study showed that the switching frequency variations in a fundamental cycle and over the entire speed range of the linear modulation region, is similar to that of a VC-SVPWM based multi-level VSI. The proposed hysteresis controller is experimentally verified on a 7.5 kW IM vector control drive fed with a five-level VSI. The proposed current error space vector based hysteresis controller providing nearly constant switching frequency is implemented on a TI TMS320LF2812 DSP and Xilinx XC3S200FT256 FPGA based platform. The three-phase reference currents are generated depending on the frequency command and the controller is tested with the drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and quick transient results of the proposed drive are presented in this thesis. This thesis also proposes another type of hysteresis controller, firstly for 2-level inverter and then for general n-level multi-level inverter, which eliminates the parabolic boundary and replaces it with a boundary which is computed online and does not use any look up table for boundary selection. The current error boundary for the proposed hysteresis controller is computed online in a very simple way, using the information of estimated fundamental stator voltages along α and β axes of space vector plane. The method adopted for the proposed controller to compute the boundary does not involve any complicated computations and it selects the optimal vector for switching when current error space vector crosses the boundary. This way adjacent voltage vector switching similar to VC-SVPWM can be ensured. For 2-level inverter, it precisely determines the sector, in which reference voltage vector is present. In multi-level inverter, this controller also finds out the mapped sector information using the same mapping techniques as explained in the first part of this thesis. In both 2-level and multi-level inverter, the proposed controller does not use any look up table for finding individual voltage vector switching times from the estimated voltage references. These switching times are used for the computation of hysteresis boundary for individual vectors. Thus the hysteresis boundary for individual vectors is exactly calculated and the boundary is similar to that of VC-SVPWM scheme for the respective levels of inverter. In the present scheme, the phase voltage harmonic spectrum is very close to that of a constant switching frequency VC-SVPWM inverter. In this thesis, at first, the proposed on line boundary computation scheme is implemented for a 2-level inverter based controller for the initial study, so that it can be executed as fast as 10 µs in a DSP platform, which is required for accurate current control. Then the same algorithm of 2-level inverter is extended for multi-level inverter with the additional logic for online identification of nearest switching voltage vectors (also used in the parabolic boundary case) for the present sampling interval. Previously mentioned mapping technique for multi-level inverter, is also implemented here to bring down the phase voltage references to the inner-most carrier region to realize the multi-level current control strategy equivalent to that of a 2-level inverter PWM current control. Simulation study to verify the steady state as well as transient performance of the proposed controller for both 2-level as well as five-level VSI fed IM drive is carried out using Simulink tool box of MATLAB Simulation Software. The proposed hysteresis controllers are experimentally verified on a 7.5 kW IM vector control drive fed with a two-level VSI and five-level VSI separately. The proposed current error space vector based hysteresis controller providing nearly constant switching frequency profile for phase voltage is implemented on the TI TMS320LF2812 DSP and Xilinx XC3S200FT256 FPGA based platform. The three-phase reference currents are generated depending on the frequency command and the proposed hysteresis controllers are tested with drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and transient results of the proposed drive are also presented for different operating conditions, through the simulation study followed by experimental verifications. Even though the simulation and experimental verifications are done on a 5-level inverter to explain the proposed hysteresis controller, it can be easily implemented for any general n-level inverter, as described in this thesis.

In DC to AC power conversion, voltage source inverters (VSI) based current controllers are usually preferred for today’s high performance AC drive which requires excellent dynamic and steady state performances at different transient and load conditions, with the additional advantages like inherent short circuit and over current protection. Out of different types of current controllers, hysteresis controllers are widely used due to their simplicity and ability to meet the requirements for a high performance AC drives. But the conventional hysteresis controllers suffers from wide variation of PWM switching frequency, overshoot in current errors, sub-harmonic components in the current waveform and non-optimum switching at different operating point of the drive system. To mitigate these problems, particularly to control the switching frequency variation, which is the root cause of all other problems, several methodologies like ramp comparison based controller, predictive current controller, etc. were proposed in the literature. But amplitude and phase offset error in the ramp comparison based controllers and complexities involved in the predictive controllers have limited the use of these controllers. Moreover, these type of controllers, which uses three separate and independently controlled tolerance band (sinusoidal type or adaptive) to control the 3-phase currents, shows limited dynamic responses and they are not simple to implement. To tackle the problem of controlling 3-phase currents simultaneously, space vector based hysteresis current controller is very effective as it combines the current errors of all the three phases as a single entity called current error space vector. It has a single controller’s logic with a hysteresis boundary for controlling this current error space vector. Several papers on space vector based hysteresis controllers for 2-level inverter with constant switching frequency have been published, but the application of the constant switching frequency based hysteresis current controllers for multi¬level inverter fed drive system, has not been addressed properly. Use of multi-level inverter in modern high performance drive for medium and high voltage levels is more prominent because of multi-level’s inherent advantages like good power quality, good electromagnetic compatibility (EMC), better DC link voltage utilization, reduced device voltage rating, so on. Even though some of the earlier works describe three-level space vector based hysteresis current controller techniques, they are specific to the particular level of inverters and does not demonstrate constant switching frequency of operation. This thesis proposes a novel approach where nearly constant switching frequency based hysteresis controller can be implemented for any general n-level inverter and it is also independent of inverter topology. In this work, varying parabolic boundary is used as the hysteresis current error boundary for controlling the current in a multi-level space vector structure. The computation of the parabolic boundary is accomplished offline and all the necessary boundary parameters at different operating points are stored in the look-up tables. The varying parabolic boundary for the multi-level space vector structure depends on the sampled reference phase voltage values which are estimated from stator current error information and then using the equivalent circuit model of induction motors. Here, a mapping technique is adopted to bring down all the three phase references to the inner- most carrier region, which results in mapping any outer triangular structure where tip of the voltage space vector is located, to one of the sectors of the inner most hexagon of the multi-level space vector structure. In this way, the required mapped sector information is easily found out to fix the correct orientation of the parabolic boundary in the space vector plane. This mapping technique simplifies the controller’s logic similar to that of a 2-level inverter. For online identification of the inverter switching voltage vectors constructing the present outer triangle of the multi-level space vector structure, the proposed controller utilizes the sampled phase voltage references. This identification technique is novel and also generic for any n-level inverter structure. This controller is having all the advantages of a space vector based hysteresis current controller and that of a multi-level inverter apart from having a nearly constant switching frequency spectrum similar to that of a voltage controlled space vector PWM (VC-SVPWM). Using the proposed controller, simulation study of a five-level inverter fed induction motor (IM) drive scheme, was carried out using Matlab-Simulink. Simulation study showed that the switching frequency variations in a fundamental cycle and over the entire speed range of the linear modulation region, is similar to that of a VC-SVPWM based multi-level VSI. The proposed hysteresis controller is experimentally verified on a 7.5 kW IM vector control drive fed with a five-level VSI. The proposed current error space vector based hysteresis controller providing nearly constant switching frequency is implemented on a TI TMS320LF2812 DSP and Xilinx XC3S200FT256 FPGA based platform. The three-phase reference currents are generated depending on the frequency command and the controller is tested with the drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and quick transient results of the proposed drive are presented in this thesis. This thesis also proposes another type of hysteresis controller, firstly for 2-level inverter and then for general n-level multi-level inverter, which eliminates the parabolic boundary and replaces it with a boundary which is computed online and does not use any look up table for boundary selection. The current error boundary for the proposed hysteresis controller is computed online in a very simple way, using the information of estimated fundamental stator voltages along α and β axes of space vector plane. The method adopted for the proposed controller to compute the boundary does not involve any complicated computations and it selects the optimal vector for switching when current error space vector crosses the boundary. This way adjacent voltage vector switching similar to VC-SVPWM can be ensured. For 2-level inverter, it precisely determines the sector, in which reference voltage vector is present. In multi-level inverter, this controller also finds out the mapped sector information using the same mapping techniques as explained in the first part of this thesis. In both 2-level and multi-level inverter, the proposed controller does not use any look up table for finding individual voltage vector switching times from the estimated voltage references. These switching times are used for the computation of hysteresis boundary for individual vectors. Thus the hysteresis boundary for individual vectors is exactly calculated and the boundary is similar to that of VC-SVPWM scheme for the respective levels of inverter. In the present scheme, the phase voltage harmonic spectrum is very close to that of a constant switching frequency VC-SVPWM inverter. In this thesis, at first, the proposed on line boundary computation scheme is implemented for a 2-level inverter based controller for the initial study, so that it can be executed as fast as 10 µs in a DSP platform, which is required for accurate current control. Then the same algorithm of 2-level inverter is extended for multi-level inverter with the additional logic for online identification of nearest switching voltage vectors (also used in the parabolic boundary case) for the present sampling interval. Previously mentioned mapping technique for multi-level inverter, is also implemented here to bring down the phase voltage references to the inner-most carrier region to realize the multi-level current control strategy equivalent to that of a 2-level inverter PWM current control. Simulation study to verify the steady state as well as transient performance of the proposed controller for both 2-level as well as five-level VSI fed IM drive is carried out using Simulink tool box of MATLAB Simulation Software. The proposed hysteresis controllers are experimentally verified on a 7.5 kW IM vector control drive fed with a two-level VSI and five-level VSI separately. The proposed current error space vector based hysteresis controller providing nearly constant switching frequency profile for phase voltage is implemented on the TI TMS320LF2812 DSP and Xilinx XC3S200FT256 FPGA based platform. The three-phase reference currents are generated depending on the frequency command and the proposed hysteresis controllers are tested with drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and transient results of the proposed drive are also presented for different operating conditions, through the simulation study followed by experimental verifications. Even though the simulation and experimental verifications are done on a 5-level inverter to explain the proposed hysteresis controller, it can be easily implemented for any general n-level inverter, as described in this thesis.

Use of multilevel inverters are inevitable in medium and high voltage drives. This is due to the fact that the multilevel inverters can produce voltages in smaller steps which will reduce the harmonic content and result in more sinusoidal voltages and currents as compared to voltages and currents from two-level inverters. Due to the device limitations, use of two-level inverters is not possible in medium and high voltage drive applications. Though multiple devices can be connected both in series and parallel to achieve two-level operation, the output voltages still suffer from high harmonic content. Multilevel inverters have multiple DC voltage levels with switches that enable one of the voltage steps to be applied to the load. Due to decrease in step size during each switching instant, output voltages and currents of the multilevel inverters have considerably less harmonic content. As the number of levels increase, the switching step reduces thereby the harmonic content also reduces drastically. Due to their advantages, multilevel inverters have gained lot of acceptance in the industry even at lower voltages. The three main configurations that have gained popularity are the neutral point clamped converter, the flying capacitor converter and the cascaded H-bridge converter. Each converter has its own set of advantages and disadvantages. Based on the requirements of various applications, it is possible to fabricate hybrid multilevel topologies that are combinations of the three basic topologies. Researchers around the world have proposed several such converters for diverse applications so as to suit particular requirements like modularity, ease of control, improved reliability, fault tolerant capability etc. The present thesis explores multilevel converters with single DC link to be used for motor drive and grid connected applications. A novel five-level inverter topology formed by cascading a floating capacitor H-bridge module to a regular three-level flying capacitor inverter has been explored in chapter 2. The three-level flying capacitor inverter can generate pole voltages of 0, VDC /2 and VDC . By cascading it with another floating capacitor H-bridge of voltage magnitude VDC /4, pole voltages of 0, VDC /4, VDC/2, 3VDC /4 and VDC . Each of these pole voltage levels can have one or more switching combinations. However each switching combination has a unique effect on the state of the two capacitor voltages. By switching through redundant switching combinations for the same pole voltage, the two capacitors present in each phase can be balanced. The proposed topology also has an advantage that if one of the devices in the H-bridge fails, the topology can still be operated as a regular three-level flying capacitor inverter that can supply full load at rated power by bypassing the faulty H-bridge. This fault tolerant operation of the converter will enable it to be used in applications like traction and marine drives where high reliability is needed. The proposed converter needs a single DC link. All the required voltage levels can be generated from the single DC link. This enables back to back grid connected operation possible where multiple converters can interact with a single DC link. Various pole voltage switching combination and its effect on individual capacitor has been studied. A control algorithm to balance the capacitor voltages by switching through multiple redundancies for the same pole voltage has been developed. The proposed configuration has been implemented in hardware using IGBT H-bridge modules and the control circuitry is realized using DSP and FPGA. The performance of the drive is verified for various frequencies and modulation indices during steady state by running a three phase induction motor at no load. The stability of the drive during transients has been studied by accelerating the machine suddenly at no load and analyzing the performance of the drive. The capacitor voltages are made to deviate from their intended values and the capacitor balancing algorithm has been verified for its ability to bring the capacitor voltages back to their intended values. The experimental results have been presented and discussed in detail in the chapter 2. In the third chapter a common-mode voltage eliminated three-level inverter using a single DC link has been proposed. The power schematic is similar to the one presented in chapter 2. In this chapter the space vector polygon formed by the three phases of the proposed topology has been presented. The common-mode voltage generated by different pole voltage combinations for same space vector location and the redundant switching state combinations has been studied. The pole voltage combinations with zero common mode voltage have been studied. The switching state redundancies for the the pole voltage have been studied. The space vector polygon formed with the pole voltage combinations has been analyzed. A drive is made with the proposed common-mode voltage eliminated inverter. The performance of the drive is tested for various modulation indices and frequencies by running a three phase squirrel cage induction motor at no load. The transient performance is verified by accelerating the motor suddenly and checking the common-mode voltage along with the capacitor voltages. The results have been presented and discussed in detail in chapter 3. This converter has advantages like use of single DC supply, ability to operate as a regular three level converter in case of failure of one of the H-bridges. The work presented in fourth chapter proposes a novel three phase 17-level inverter configuration which utilizes a single DC supply. The rest of voltages are generated using three floating capacitor H-bridges. The redundant switching combinations for generating various pole voltages and their effect on the capacitors have been studied and suitable capacitor balancing algorithm has been developed. The proposed topology has been realized in hardware and the performance of the drive during steady state has been studied by running an induction motor at various modulation indices and frequencies. The transient response of the drive has been observed by accelerating the motor suddenly under no load. The results have been presented in detail in chapter four. This configuration also needs a single DC link. The advantages of this configuration is in case of failure of any devices in the H-bridge, the drive can be operated at reduced number of levels while supplying full load current. This feature helps the drive to be used in fault tolerant applications like marine and traction drives where reliability of the drive is of prime importance. All the topologies that have been presented in the previous chapters have mentioned about the usage of the proposed genre of topologies use single DC link and hence will enable back to back grid tied inverter connection. In the fifth chapter this has has been verified experimentally. The three phase squirrel cage induction motor is driven by using the seventeen-level inverter drive proposed in chapter four. A five-level active front-end is realized by the converter topology proposed in chapter two. The converter is run and the performance of the drive is studied at various modulation indices and speeds of the motor. Various aspects like re-generation operation, acceleration and other aspects of the drive have been studied experimentally and the results are presented in detail. For experimental setup, Semikron SKM75GB12T4 IGBT modules have been used to realize the power topology. These IGBTs are driven by M56972L drivers. The control circuit is realized using TMS320F2812 DSP along with Xilinx Spartan 3 FPGA (XC3S200) has been used. The voltages and currents are sensed using LEM LV-20P and LA 55-P hall effect based sensors.

Use of multilevel inverters are inevitable in medium and high voltage drives. This is due to the fact that the multilevel inverters can produce voltages in smaller steps which will reduce the harmonic content and result in more sinusoidal voltages and currents as compared to voltages and currents from two-level inverters. Due to the device limitations, use of two-level inverters is not possible in medium and high voltage drive applications. Though multiple devices can be connected both in series and parallel to achieve two-level operation, the output voltages still suffer from high harmonic content. Multilevel inverters have multiple DC voltage levels with switches that enable one of the voltage steps to be applied to the load. Due to decrease in step size during each switching instant, output voltages and currents of the multilevel inverters have considerably less harmonic content. As the number of levels increase, the switching step reduces thereby the harmonic content also reduces drastically. Due to their advantages, multilevel inverters have gained lot of acceptance in the industry even at lower voltages. The three main configurations that have gained popularity are the neutral point clamped converter, the flying capacitor converter and the cascaded H-bridge converter. Each converter has its own set of advantages and disadvantages. Based on the requirements of various applications, it is possible to fabricate hybrid multilevel topologies that are combinations of the three basic topologies. Researchers around the world have proposed several such converters for diverse applications so as to suit particular requirements like modularity, ease of control, improved reliability, fault tolerant capability etc. The present thesis explores multilevel converters with single DC link to be used for motor drive and grid connected applications. A novel five-level inverter topology formed by cascading a floating capacitor H-bridge module to a regular three-level flying capacitor inverter has been explored in chapter 2. The three-level flying capacitor inverter can generate pole voltages of 0, VDC /2 and VDC . By cascading it with another floating capacitor H-bridge of voltage magnitude VDC /4, pole voltages of 0, VDC /4, VDC/2, 3VDC /4 and VDC . Each of these pole voltage levels can have one or more switching combinations. However each switching combination has a unique effect on the state of the two capacitor voltages. By switching through redundant switching combinations for the same pole voltage, the two capacitors present in each phase can be balanced. The proposed topology also has an advantage that if one of the devices in the H-bridge fails, the topology can still be operated as a regular three-level flying capacitor inverter that can supply full load at rated power by bypassing the faulty H-bridge. This fault tolerant operation of the converter will enable it to be used in applications like traction and marine drives where high reliability is needed. The proposed converter needs a single DC link. All the required voltage levels can be generated from the single DC link. This enables back to back grid connected operation possible where multiple converters can interact with a single DC link. Various pole voltage switching combination and its effect on individual capacitor has been studied. A control algorithm to balance the capacitor voltages by switching through multiple redundancies for the same pole voltage has been developed. The proposed configuration has been implemented in hardware using IGBT H-bridge modules and the control circuitry is realized using DSP and FPGA. The performance of the drive is verified for various frequencies and modulation indices during steady state by running a three phase induction motor at no load. The stability of the drive during transients has been studied by accelerating the machine suddenly at no load and analyzing the performance of the drive. The capacitor voltages are made to deviate from their intended values and the capacitor balancing algorithm has been verified for its ability to bring the capacitor voltages back to their intended values. The experimental results have been presented and discussed in detail in the chapter 2. In the third chapter a common-mode voltage eliminated three-level inverter using a single DC link has been proposed. The power schematic is similar to the one presented in chapter 2. In this chapter the space vector polygon formed by the three phases of the proposed topology has been presented. The common-mode voltage generated by different pole voltage combinations for same space vector location and the redundant switching state combinations has been studied. The pole voltage combinations with zero common mode voltage have been studied. The switching state redundancies for the the pole voltage have been studied. The space vector polygon formed with the pole voltage combinations has been analyzed. A drive is made with the proposed common-mode voltage eliminated inverter. The performance of the drive is tested for various modulation indices and frequencies by running a three phase squirrel cage induction motor at no load. The transient performance is verified by accelerating the motor suddenly and checking the common-mode voltage along with the capacitor voltages. The results have been presented and discussed in detail in chapter 3. This converter has advantages like use of single DC supply, ability to operate as a regular three level converter in case of failure of one of the H-bridges. The work presented in fourth chapter proposes a novel three phase 17-level inverter configuration which utilizes a single DC supply. The rest of voltages are generated using three floating capacitor H-bridges. The redundant switching combinations for generating various pole voltages and their effect on the capacitors have been studied and suitable capacitor balancing algorithm has been developed. The proposed topology has been realized in hardware and the performance of the drive during steady state has been studied by running an induction motor at various modulation indices and frequencies. The transient response of the drive has been observed by accelerating the motor suddenly under no load. The results have been presented in detail in chapter four. This configuration also needs a single DC link. The advantages of this configuration is in case of failure of any devices in the H-bridge, the drive can be operated at reduced number of levels while supplying full load current. This feature helps the drive to be used in fault tolerant applications like marine and traction drives where reliability of the drive is of prime importance. All the topologies that have been presented in the previous chapters have mentioned about the usage of the proposed genre of topologies use single DC link and hence will enable back to back grid tied inverter connection. In the fifth chapter this has has been verified experimentally. The three phase squirrel cage induction motor is driven by using the seventeen-level inverter drive proposed in chapter four. A five-level active front-end is realized by the converter topology proposed in chapter two. The converter is run and the performance of the drive is studied at various modulation indices and speeds of the motor. Various aspects like re-generation operation, acceleration and other aspects of the drive have been studied experimentally and the results are presented in detail. For experimental setup, Semikron SKM75GB12T4 IGBT modules have been used to realize the power topology. These IGBTs are driven by M56972L drivers. The control circuit is realized using TMS320F2812 DSP along with Xilinx Spartan 3 FPGA (XC3S200) has been used. The voltages and currents are sensed using LEM LV-20P and LA 55-P hall effect based sensors.

This thesis aims to extend the knowledge about the performance of different cascaded multilevel inverter induction motor drives through harmonic analysis. Large electric drives and utility applications require advanced power electronics converter to meet the high power demands. As a result, multilevel power converter structure has been introduced as an alternative in high power and medium voltage situations. A multilevel converter not only achieves high power ratings, but also improves the performance of the whole system in terms of harmonics, dv/dt stresses, and stresses in the bearings of a motor. Several multilevel converter topologies have been developed; i) diode clamped, ii) flying capacitors, and iii) cascaded or H-bridge. Referring to the literature reviews, the cascaded multilevel inverter (CMI) with separated DC sources is clearly the most feasible topology for use as a power converter for medium & high power applications due to their modularization and extensibility. The H-bridge inverter eliminates the excessively large number of (i) bulky transformers required by conventional multilevel inverters, (ii) clamping diodes required by multilevel diode-clamped inverters, , and (iii) flying capacitors required by multilevel flying-capacitor inverter.

碩士
國立臺灣科技大學
電機工程系
87
The object of this thesis is to investigate the electromagnetic interference (EMI) problem of inverter-fed induction motor drives. It is determined that the pulse width modulation inverter system generates considerable impulse currents through the power leads feeding the system resulting in serious conducted electromagnetic interference problem in the power system. A proposed high frequency mathematical model of the inverter drive system for the propose of evaluation of EMI are developed. Some strategies for reduce electromagnetic interference of the pulse width modulation inverter are then proposed. An experimental measurement system is also developed to verify the proposed methods.

Thesis (Ph. D.)--University of Wisconsin--Madison, 1994.
Typescript. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references (leaves 165-167).

MU LT I L E V E L inverters are becoming the preferred choice for medium voltage high power applications. Multilevel inverters have a number of inherent advantages over conventional two level inverters. The output voltage has multiple steps or levels, resulting in reduced dV/dt, which leads to lower electromagnetic interference, making it easier to meet electromagnetic compatibility (EMC) regulations. Multilevel inverters have a much lower effective switching frequency, which leads to a reduction in switching losses. The output voltage of multilevel inverters has a much lower harmonic content. In applications such as power conversion or grid-connection, filters need to be much smaller, or can be eliminated. In motor drive applications, the low harmonic content results in smoother, ripple-free shaft torque. The neutral-point clamped (NPC), cascaded H-bridge (CHB) and flying capacitor (FC) topologies were among the earliest multilevel topologies. NPC topologies require additional clamping diodes to clamp the output to the DC bus midpoint. CHB topologies use a number of isolated DC suplies to generate multilevel output. FC topologies work with a single DC link but use additional floating capacitors. Since then, a number derivatives and improvements to these topologies have been proposed. Topologies with low switch counts are desirable because of the corresponding reduction in system size and cost. A low total component count is also desirable since it results in better reliability. Induction motors in high power applications are often operated in the open-end configuration. Here, the start terminals of the motor phase windings are connected to one three phase inverter, while the end terminals are connected to a second three-phase inverter. The two inverters are typically powered by isolated supplies to prevent the flow of common mode currents through the motor. The open end configuration has a number of advantages It can be used with nearly all high power motors with no need for electrical or mechanical modification, since all six winding terminal are available externally. The two inverters driving the open-end motor are effectively cascaded. As a result, two inverters of lower voltage and power rating can replace a single inverter with higher voltage and power rating. In addition, if one of the inverter fails, it can be bypassed and the system can be operated at reduced power. In many applications such as heating, ventilation and air conditioning (HVAC), the load power is proportional to the cube of the shaft speed, so a 50% reduction in power translates to only 20% reduction in speed, thereby improving overall system reliability. The cascading of inverters also enables multilevel operation, which is exploited for the topologies proposed in this thesis. In the open-end configuration it is important to ensure that both the DC supplies deliver power to the load. Otherwise, power can circulate through the motor windings. In addition, if the two inverters are powered by rectifier supplies, the DC bus of one inverter can charge uncontrollably, resulting in distortion of phase voltages and currents. If DC bus overcharging continues unchecked the DC bus voltage can even exceed the system rating, resulting in permanent damage. This thesis proposes two novel topologies for open-end induction motor drives with low switch counts. Both topologies are powered by two unequal, isolated DC sources having DC voltages in a 3:1 ratio. Multiple levels in the output voltage are obtained using a number of floating capacitors in each phase. Modulation and control schemes are also proposed for both topologies to ensure that DC bus overcharging never occurs, while all the capacitor voltages are kept balanced at their nominal values. The first of these two topologies is a nine level inverter for open end induction motor drives. It consists of two three-level flying capacitor inverters connected to the induction motor in the open end configuration. The two inverters are powered by DC sources of voltage 6VDC/8 and 2VDC/8, which generates an effective phase voltage having nine levels in steps of VDC/8. This topology has only eight switches and two floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 217 space vector locations. A space-vector based formulation is used to determine the pole voltage of the inverter such that DC bus over charging is prevented. In addition, selection of switching states is used to balance the voltages of all floating capacitors. This scheme allows the floating capacitors to be charged up during system startup, thereby eliminating the need for separate pre-charging circuitry. A level-shifted carrier PWM based modulation scheme has been developed, which can be used with both scalar and vector control schemes. The gating signal for switches turning on must be delayed by a small amount (to allow the complementary switch to turn of), failing which current shoot through can occur. This delay is called dead time, during which gate signals to both complementary devices are turned of. Under certain conditions in the flying capacitor topology, the pole voltage can contain large undesirable transients during the dead time which result in phase current distortion, and electromagnetic noise. A novel scheme to eliminate this problem is proposed using a digital state machine approach. The switching state for each subsequent switching interval is determined based on the present switching state such that the pole voltage does not contain a transient, without affecting the phase voltage of the inverter, and irrespective of the current magnitude or direction. The state machine was implemented using an FPGA, and required an additional computation time of just 20ns, which is much smaller than the inverter dead time duration of typically 2.5µs. The second novel topology proposed in this thesis is a seventeen level inverter for an open end induction motor drive. Here, one three-level inverter and one seven-level inverter are connected to the two ends of the induction machine. The three-level inverter is a flying capacitor inverter. The seven-level inverter is a hybrid topology – it consists of an H-bridge cascaded to each phase of a three level flying capacitor inverter. This scheme is also powered by two isolated DC sources in 3:1 ratio with magnitudes 12VDC/16 and 4VDC/16. The effective phase voltage has seventeen levels in steps of VDC/16. This topology has a total of twelve switches and three floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 817 space-vector locations. Space vector analysis was used to determine the pole voltages, and the switching states such that DC bus overcharging is prevented while also balancing the voltages of the floating capacitors. A non-iterative algorithm was developed for determining the switching states, suitable for implementation in digital logic using an FPGA. The scheme is able to charge the all capacitors at startup as well, eliminating the need for separate pre-charging circuits. Hardware prototypes were built for both the topologies described above for experimental verification, and used to drive a three phase 50Hz, 1.5kW, four pole induction motor in V/f control mode. The inverters topologies were built using 1200V, 75A IGBT half-bridge modules (Semikron SKM75GB12T4) with hybrid opto-isolated gate drivers (Mitsubishi M57962). Three phase rectifiers were used to create the asymmetric DC supplies Hall effect sensors were used to sense the DC link and floating capacitor voltages and phase currents (LEM LV20P voltage sensors and LA55 current sensors). Signal conditioning circuitry was built using discrete components. The PWM signals and V/f controller were implemented using a digital signal processor (Texas Instruments TMS320F28335). Synchronous PWM with was used to eliminate sub-harmonics from the phase voltage, and to ensure three-phase and half-wave symmetry. The internal ADC of the DSP was used for sampling all voltages and currents. The remaining digital logic for switch state selection was implemented on a FPGA (Xilinx Spartan3 XC3S200). Dead time functionality was also implemented within the FPGA, eliminating the need for separate dead time hardware. Both topologies were first tested for steady state operation over the full modulation range, and the pole voltages, phase voltages and phase currents were recorded. System startup, and the ability of the controllers to balance all the capacitors at startup was tested next. The capacitor voltages were also observed during sudden loading, by quickly accelerating the motor. Finally, the phenomenon of DC bus overcharging was also demonstrated. These results demonstrate the suitability of the proposed topology for a number of applications, including industrial drives, alternate energy systems, power conversion and electric traction.

MU LT I L E V E L inverters are becoming the preferred choice for medium voltage high power applications. Multilevel inverters have a number of inherent advantages over conventional two level inverters. The output voltage has multiple steps or levels, resulting in reduced dV/dt, which leads to lower electromagnetic interference, making it easier to meet electromagnetic compatibility (EMC) regulations. Multilevel inverters have a much lower effective switching frequency, which leads to a reduction in switching losses. The output voltage of multilevel inverters has a much lower harmonic content. In applications such as power conversion or grid-connection, filters need to be much smaller, or can be eliminated. In motor drive applications, the low harmonic content results in smoother, ripple-free shaft torque. The neutral-point clamped (NPC), cascaded H-bridge (CHB) and flying capacitor (FC) topologies were among the earliest multilevel topologies. NPC topologies require additional clamping diodes to clamp the output to the DC bus midpoint. CHB topologies use a number of isolated DC suplies to generate multilevel output. FC topologies work with a single DC link but use additional floating capacitors. Since then, a number derivatives and improvements to these topologies have been proposed. Topologies with low switch counts are desirable because of the corresponding reduction in system size and cost. A low total component count is also desirable since it results in better reliability. Induction motors in high power applications are often operated in the open-end configuration. Here, the start terminals of the motor phase windings are connected to one three phase inverter, while the end terminals are connected to a second three-phase inverter. The two inverters are typically powered by isolated supplies to prevent the flow of common mode currents through the motor. The open end configuration has a number of advantages It can be used with nearly all high power motors with no need for electrical or mechanical modification, since all six winding terminal are available externally. The two inverters driving the open-end motor are effectively cascaded. As a result, two inverters of lower voltage and power rating can replace a single inverter with higher voltage and power rating. In addition, if one of the inverter fails, it can be bypassed and the system can be operated at reduced power. In many applications such as heating, ventilation and air conditioning (HVAC), the load power is proportional to the cube of the shaft speed, so a 50% reduction in power translates to only 20% reduction in speed, thereby improving overall system reliability. The cascading of inverters also enables multilevel operation, which is exploited for the topologies proposed in this thesis. In the open-end configuration it is important to ensure that both the DC supplies deliver power to the load. Otherwise, power can circulate through the motor windings. In addition, if the two inverters are powered by rectifier supplies, the DC bus of one inverter can charge uncontrollably, resulting in distortion of phase voltages and currents. If DC bus overcharging continues unchecked the DC bus voltage can even exceed the system rating, resulting in permanent damage. This thesis proposes two novel topologies for open-end induction motor drives with low switch counts. Both topologies are powered by two unequal, isolated DC sources having DC voltages in a 3:1 ratio. Multiple levels in the output voltage are obtained using a number of floating capacitors in each phase. Modulation and control schemes are also proposed for both topologies to ensure that DC bus overcharging never occurs, while all the capacitor voltages are kept balanced at their nominal values. The first of these two topologies is a nine level inverter for open end induction motor drives. It consists of two three-level flying capacitor inverters connected to the induction motor in the open end configuration. The two inverters are powered by DC sources of voltage 6VDC/8 and 2VDC/8, which generates an effective phase voltage having nine levels in steps of VDC/8. This topology has only eight switches and two floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 217 space vector locations. A space-vector based formulation is used to determine the pole voltage of the inverter such that DC bus over charging is prevented. In addition, selection of switching states is used to balance the voltages of all floating capacitors. This scheme allows the floating capacitors to be charged up during system startup, thereby eliminating the need for separate pre-charging circuitry. A level-shifted carrier PWM based modulation scheme has been developed, which can be used with both scalar and vector control schemes. The gating signal for switches turning on must be delayed by a small amount (to allow the complementary switch to turn of), failing which current shoot through can occur. This delay is called dead time, during which gate signals to both complementary devices are turned of. Under certain conditions in the flying capacitor topology, the pole voltage can contain large undesirable transients during the dead time which result in phase current distortion, and electromagnetic noise. A novel scheme to eliminate this problem is proposed using a digital state machine approach. The switching state for each subsequent switching interval is determined based on the present switching state such that the pole voltage does not contain a transient, without affecting the phase voltage of the inverter, and irrespective of the current magnitude or direction. The state machine was implemented using an FPGA, and required an additional computation time of just 20ns, which is much smaller than the inverter dead time duration of typically 2.5µs. The second novel topology proposed in this thesis is a seventeen level inverter for an open end induction motor drive. Here, one three-level inverter and one seven-level inverter are connected to the two ends of the induction machine. The three-level inverter is a flying capacitor inverter. The seven-level inverter is a hybrid topology – it consists of an H-bridge cascaded to each phase of a three level flying capacitor inverter. This scheme is also powered by two isolated DC sources in 3:1 ratio with magnitudes 12VDC/16 and 4VDC/16. The effective phase voltage has seventeen levels in steps of VDC/16. This topology has a total of twelve switches and three floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 817 space-vector locations. Space vector analysis was used to determine the pole voltages, and the switching states such that DC bus overcharging is prevented while also balancing the voltages of the floating capacitors. A non-iterative algorithm was developed for determining the switching states, suitable for implementation in digital logic using an FPGA. The scheme is able to charge the all capacitors at startup as well, eliminating the need for separate pre-charging circuits. Hardware prototypes were built for both the topologies described above for experimental verification, and used to drive a three phase 50Hz, 1.5kW, four pole induction motor in V/f control mode. The inverters topologies were built using 1200V, 75A IGBT half-bridge modules (Semikron SKM75GB12T4) with hybrid opto-isolated gate drivers (Mitsubishi M57962). Three phase rectifiers were used to create the asymmetric DC supplies Hall effect sensors were used to sense the DC link and floating capacitor voltages and phase currents (LEM LV20P voltage sensors and LA55 current sensors). Signal conditioning circuitry was built using discrete components. The PWM signals and V/f controller were implemented using a digital signal processor (Texas Instruments TMS320F28335). Synchronous PWM with was used to eliminate sub-harmonics from the phase voltage, and to ensure three-phase and half-wave symmetry. The internal ADC of the DSP was used for sampling all voltages and currents. The remaining digital logic for switch state selection was implemented on a FPGA (Xilinx Spartan3 XC3S200). Dead time functionality was also implemented within the FPGA, eliminating the need for separate dead time hardware. Both topologies were first tested for steady state operation over the full modulation range, and the pole voltages, phase voltages and phase currents were recorded. System startup, and the ability of the controllers to balance all the capacitors at startup was tested next. The capacitor voltages were also observed during sudden loading, by quickly accelerating the motor. Finally, the phenomenon of DC bus overcharging was also demonstrated. These results demonstrate the suitability of the proposed topology for a number of applications, including industrial drives, alternate energy systems, power conversion and electric traction.