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Relevant bibliographies by topics / Ise-tcad

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Academic literature on the topic 'Ise-tcad'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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Journal articles on the topic "Ise-tcad"

1

Chen, Ying-Yu, and Yu-Hsien Lin. "Comparison of bulk FinFET and SOI FinFET." MATEC Web of Conferences 201 (2018): 02009. http://dx.doi.org/10.1051/matecconf/201820102009.

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In this study, we compare the differences and advantages between Bulk FinFET and SOI FinFET. The results are simulated by using the ISE TCAD software. By changing the parameters of the gate voltage, drain voltage and gate length to analysis which characteristic is better. Through the experiment results, we demonstrate that the SOI FinFET have the better characteristics than bulk FinFET[1].

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Sun, Ying, Wei Guo, and Da Zhong Zhu. "Design and Research of Trench-Isolated LAPS Sensor Array." Applied Mechanics and Materials 734 (February 2015): 71–74. http://dx.doi.org/10.4028/www.scientific.net/amm.734.71.

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A new kind of SOI LAPS sensor array with trench and heavy doping structure was proposed. Photo current response, noise isolation and device performance were simulated with ISE-TCAD tools. The new structure LAPS sensor array effectively improves noise separation characteristics of adjacent array units. The SNR (signal-to-noise ratio) of LAPS array with trench-isolated structure is superior to that with only heavy doping regions. Trench isolation structure also improves the integration scales of LAPS array.

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Xu, Xiao Bo, He Ming Zhang, Hui Yong Hu, Jian Li Ma, and Li Jun Xu. "Generalized Early Voltage Model of Bipolar Transistors for Linearly Graded Germanium in Base." Applied Mechanics and Materials 110-116 (October 2011): 3311–15. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.3311.

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The standard Early voltage of the SPICE Gummel-Poon model (SGP) is generalized for SiGe npn heterojunction bipolar transistors (HBTs). An accurate model for Early effects compatible with the SGP model is obtained considering graded germanium induced bandgap narrowing effect in the base in modern SiGe HBTs and simplified to a compact model which is consistent with ISE TCAD simulation results. The presentation of the Early effect model is significant for the design and simulation of the high performance SiGe BiCMOS technology.

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Maragliano, C., M. Stefancich, S. Rampino, and L. Colace. "Realistic simulation of polycrystalline CIGS absorbers and experimental verification." MRS Proceedings 1493 (2013): 153–60. http://dx.doi.org/10.1557/opl.2013.401.

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AbstractCu(InGa)Se2 solar cells modeling is challenging due to their complex electronic structure, to the presence of interface states between layer and grains and to the microcrystalline structure of the absorber. Here we present a ISE-TCAD based realistic absorber 3D model, with the specific objective to take into account, among several effects, these challenging aspects. The CdS/Cu(InGa)Se2 solar cell is modeled as an array of columnar microcells, connected in parallel, mimicking the polycrystalline nature of the absorber. The model optical and electrical parameters are optimized based on a review of available experimental material characterization and realization results. Simulation outcomes are compared with experimental data in order to validate the model.

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Eun, Dong, Li Chang, Cheol Sang, Kyun Nam, Qui Jian, and Bin Ji. "Design of High-Power Reverse-Conducting Gate-Commutated Thyristors." Facta universitatis - series: Electronics and Energetics 15, no. 1 (2002): 41–50. http://dx.doi.org/10.2298/fuee0201041e.

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Different structures of Reserve-Conducting Gate-Commutated\break Thyristor (RC-GCT) are considered in this paper. The non-punch-through and punch-through structures were recommended for blocking voltages of 2.5 kV and 4.5 kV, respectively. The photomasks were designed upon the high turn-off capability of GCT and the monolithic integration of GCT and free wheeling diode (FWD). For a large-diameter RC-GCT device with a high turn-off current capacity, FWD and GCT were designed at the center region and the outer part of wafer, respectively. Mixed mode simulation results using the ISE-TCAD simulators give turn-on and turn-off waveforms of the considered structures. A modified isolation structure between GCT and FWD is proposed for RC-GCT.

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Sh. HUSSEIN, A., Z. HASSAN, H. ABU HASSAN, and S. M. THAHAB. "ELECTRICAL PROPERTIES OF AlGaN/GaN HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS (HFETs) WITH AND WITHOUT Mg-DOPED CARRIER CONFINEMENT LAYER." International Journal of Nanoscience 09, no. 04 (August 2010): 263–67. http://dx.doi.org/10.1142/s0219581x10006776.

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AlGaN/GaN -based heterostructure field-effect transistors (HFETs) with and without Mg -doped semi-insulating carrier confinement layer were simulated by using ISE TCAD software, respectively. The detailed study on the electrical properties of these samples was performed. The effect of inserting Mg -doped GaN layer on the source–drain (S–D) leakage current was investigated. Higher values of drain current and extrinsic transconductance were achieved with conventional HFETs (without Mg -doped). The source-to-drain (S–D) leakage current of conventional HFETs was also higher. However, the S–D leakage current was reduced with the insertion of the Mg -doped semi-insulating carrier confinement layer. Our results are in good agreement with the experimental results obtained by other researchers.

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7

Jia, Hujun, Yuan Liang, Tao Li, Yibo Tong, Shunwei Zhu, Xingyu Wang, Tonghui Zeng, and Yintang Yang. "Improved DRUS 4H-SiC MESFET with High Power Added Efficiency." Micromachines 11, no. 1 (December 27, 2019): 35. http://dx.doi.org/10.3390/mi11010035.

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A 4H-SiC metal semiconductor field effect transistor (MESFET) with layered doping and undoped space regions (LDUS-MESFET) is proposed and simulated by ADS and ISE-TCAD software in this paper. The structure (LDUS-MESFET) introduced layered doping under the lower gate of the channel, while optimizing the thickness of the undoped region. Compared with the double-recessed 4H-SiC MESFET with partly undoped space region (DRUS-MESFET), the power added efficiency of the LDUS-MESFET is increased by 85.8%, and the saturation current is increased by 27.4%. Although the breakdown voltage of the device has decreased, the decrease is within an acceptable range. Meanwhile, the LDUS-MESFET has a smaller gate-source capacitance and a large transconductance. Therefore, the LDUS-MESFET can better balance DC and AC characteristics and improve power added efficiency (PAE).

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8

Alahyarizadeh, Ghasem, Hassan Zainuriah, Sabah M. Thahab, Maryam Amirhoseiny, and Alaa J. Ghazai. "Effects of Cavity Length on Optical Characteristics of Deep Violet InGaN DQW Lasers." Advanced Materials Research 626 (December 2012): 605–9. http://dx.doi.org/10.4028/www.scientific.net/amr.626.605.

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The performance characteristics and their dependence to cavity length of deep violet InGaN DQW lasers emitting at 390 nm have been investigated using the Integrated System Engineering Technical Computer Aided Design (ISE TCAD) software. The focus of simulation was on the study of optical properties which were carried out with varying cavity length from 200µm to 600µm. The simulation results indicated that the cavity length strongly affects the optical properties of the violet InGaN DQW laser. They showed that the parameters related to the output power such as optical intensity increases by increasing cavity length due to increase of applied current to the laser system. The results also indicated that the parameters such as optical material gain, stimulated and radiative recombination which are related to quantum efficiencies and laser performance decrease by increasing cavity length. It was shown that the laser structure with the longer cavity length has the lower optical loss.

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Jia, Hujun, Yibo Tong, Tao Li, Shunwei Zhu, Yuan Liang, Xingyu Wang, Tonghui Zeng, and Yintang Yang. "An Improved 4H-SiC MESFET with a Partially Low Doped Channel." Micromachines 10, no. 9 (August 23, 2019): 555. http://dx.doi.org/10.3390/mi10090555.

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An improved 4H-SiC metal semiconductor field effect transistor (MESFET) based on the double-recessed MESFET (DR-MESFET) for high power added efficiency (PAE) is designed and simulated in this paper and its mechanism is explored by co-simulation of ADS and ISE-TCAD software. This structure has a partially low doped channel (PLDC) under the gate, which increases the PAE of the device by decreasing the absolute value of the threshold voltage (Vt), gate-source capacitance (Cgs) and saturation current (Id). The simulated results show that with the increase of H, the PAE of the device increases and then decreases when the value of NPLDC is low enough. The doping concentration and thickness of the PLDC are respectively optimized to be NPLDC = 1 × 1015 cm−3 and H = 0.15 μm to obtain the best PAE. The maximum PAE obtained from the PLDC-MESFET is 43.67%, while the PAE of the DR-MESFET is 23.43%; the optimized PAE is increased by 86.38%.

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Alahyarizadeh, Gh, M. Amirhoseiny, and Z. Hassan. "Effect of QW thickness and numbers on performance characteristics of deep violet InGaN MQW lasers." International Journal of Modern Physics B 29, no. 13 (May 18, 2015): 1550081. http://dx.doi.org/10.1142/s0217979215500812.

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The performance characteristics of deep violet indium gallium nitride (InGaN) multiquantum well (MQW) laser diodes (LDs) with an emission wavelength of around 390 nm have been investigated using the integrated system engineering technical computer aided design (ISE-TCAD) software. A comparative study on the effect of quantum well (QW) thickness and number on electrical and optical performance of deep violet In 0.082 Ga 0.918 N/GaN MQW LDs have been carried out. The simulation results showed that the highest slope efficiency and external differential quantum efficiency (DQE), as well as the lowest threshold current are obtained when the number of wells is two. The different QW thickness values of 2.2, 2.5, 2.8, 3 and 3.2 nm were compared and the best results were achieved for 2.5 nm QW thickness. The radiative recombination rate decreases with increasing QW thickness because of decreasing electron and hole carrier densities in wells. By increasing QW thickness, output power decreases and threshold current increases.

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Dissertations / Theses on the topic "Ise-tcad"

1

Contaret, Thierry. "Modélisations électrique et physique du bruit de fond dans les transistors MOS submicroniques : simulations avec les logiciels ELDO et ISE-TCAD." Montpellier 2, 2003. http://www.theses.fr/2003MON20035.

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Besse, Patrice. "Tenue en énergie de structures LDMOS avancées de puissance intégrée dans les domaines temporels de la nanoseconde à la milliseconde." Toulouse 3, 2004. http://www.theses.fr/2004TOU30297.

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Ce mémoire traite de la tenue aux décharges électrostatiques (ESD) et inductives de transistors de puissance LDMOS, réalisés dans des technologies BiCMOS. Des simulations physiques bidimensionnelles, corrélées avec des analyses de défaillances et des résultats de mesures ont permis d'établir et de valider les mécanismes électriques de défaillance du transistor LDMOS. Des règles de dessin sont données pour améliorer sa robustesse face aux ESD, pour différentes polarisations de sa grille. Ces règles n'engendrent aucune modification technologique et ne dégradent pas les caractéristiques électriques du transistor de puissance en régime de fonctionnement normal. Une étude approfondie de structures de protection vis-à-vis des ESD a été menée. Ces structures associées en parallèle avec le transistor LDMOS permettent d'atteindre des niveaux de robustesse plus élevés. Une gamme de structures bipolaires a été conçue, et leur optimisation a porté, sur la surface, la tension de déclenchement variable (12V à 60V) et leur robustesse (> 2,6V HBM/ µm² ). Ces structures peuvent être aussi avantageusement utilisées pour la protection du transistor contre les décharges inductives. Des solutions d'intégration de ces structures de protection au sein du composant de puissance ont été proposées. Différents brevets industriels ont été déposés et finalisent cette étude
This thesis deals with the electrostatic (ESD) and inductive discharge capability of a LDMOS power transistor, designed under BiCMOS technology. Physical and bidimensional simulations were correlated with failure analyses to validate electrical mechanisms that lead to the transistor destruction. Design guidelines were provided to increase its ESD robustness, considering various gate biasing conditions. These rules do not impact the transistor electrical characteristics during a normal operating mode. A detailed study of ESD protection structures was lead. These structures were associated in parallel with the LDMOS transistor to reach a higher level of robustness. A range of structures has been developed. Their improvement was performed taking into account the surface, the triggering voltage (12V to 60V) and the robustness (> 2. 6V HBM / µm²). These structures can be cleverly used to protect the transistor against inductive discharges. Solutions were described to integrate these structures inside the power transistor. Various patents have been filed and finalize this study

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3

Petit, Sophie. "Étude des méthodes de prédiction de taux d'erreurs en orbite dans les mémoires : nouvelle approche empirique." Toulouse, ENSAE, 2006. http://www.theses.fr/2006ESAE0015.

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Le phénomène de Single Event Upset (SEU) correspond au basculement logique d'un point mémoire suite au passage d'une particule énergétique. Les composants de type SRAM et DRAM, soumis à l'environnement spatial, sont sensibles aux SEU, il est alors primordial de prévoir leur sensibilité avant de les intégrer dans les missions spatiales. L'enjeu actuel est de concevoir un modèle de prédiction fiable utilisable pour tout type de mémoire, même fortement intégrée. La première phase de ce travail est une analyse des retours d'expériences embarquées qui a permis d'évaluer les modèles de prédiction standard, basés sur la modélisation IRPP, en comparant directement les taux d'erreurs en vol aux taux prédits, et démontrant leur incapacité à fournir des prédictions correctes. L'analyse des sources d'erreurs possibles a montré la difficulté d'améliorer les modèles standard, nous amenant alors à proposer une tout autre technique de prédiction. Ainsi, la méthode de prédiction empirique, basée sur la sensibilité mesurée des composants aux SEU, pour plusieurs angles d'incidence des particules, est présentée et mise en œuvre sur un ensemble de composants ; elle donne des résultats très encourageants. Une étude des événements multiples a été menée : elle montre que la diffusion des porteurs est à prendre en compte dans la modélisation des mécanismes de collection de charge mis en jeu. Enﬁn, des simulations numériques 3D couplées à des modèles analytiques simples permettent l'étude quantitative des mécanismes de collection dans une des structures ayant volé : ces outils ont confirmé le rôle majeur de la diffusion dans les SEU.

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4

Fang, Jen-Hung, and 方仁宏. "Using C-R Method & ISE TCAD on The Study of Threshold Voltage in Advanced CMOS Devices." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/04849275652315757951.

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碩士
國立臺北科技大學
機電整合研究所
90
Abstract Threshold voltage is a key parameter in CMOS design. Depending on the dimensions of MOSFET scaling, the threshold voltage must decrease in proportion to applied voltage in short channel devices. In devices with short channel lengths, the drain field tends to penetrate the channel toward the source, and potential distribution begins to require a 2D description. This 2D effect, referred to as the "Short Channel Effect" (SCE), results in the dependence of the threshold voltage on the channel length, as well as on punchthrough (Vt rolling-off). We will therefore use the C-R method to extract the process parameters (including Lovlap & Leff) and optimize the tilt angle of the halo implant. Furthermore, a suitable halo implant will minimize both Vt roll-off/roll-up by controlling the threshold voltage. Not only can the C-R method help monitor the source/drain structure, but also verify simulation data concerning process parameters. It is evident that the lower the threshold voltage, the higher the current drive, and hence the faster the switching speed. From the point of view of CMOS performance, it is desirable to keep the threshold voltage as low as possible. This, of course, is counterbalanced by the maximum-off-current requirement that the MOSFET turn off at Vg = 0. Many variables must be taken into consideration in lower Vt designs, such as process tolerances (gate-oxide thickness, Vt adjustment implant dose etc.) and characteristic of the material (gate work function etc.). To meet the maximum-off-current requirement, we will derive high on-state currents by means of process simulation under different conditions, and try to find appropriate variables of those process conditions.

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Book chapters on the topic "Ise-tcad"

1

Mohankumar, N. "Device Simulation Using ISE-TCAD." In Technology Computer Aided Design, 155–86. CRC Press, 2013. http://dx.doi.org/10.1201/b14860-5.

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Conference papers on the topic "Ise-tcad"

1

Bezrukov, Y. S. "User interface capabilities extension in technological modeling system (ISE TCAD)." In 2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551). IEEE, 2004. http://dx.doi.org/10.1109/pesc.2004.241080.

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Vorogeykin, D. V., and E. A. Makarov. "Simulation of CMOS inverter with the help of TCAD ISE package." In 2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551). IEEE, 2004. http://dx.doi.org/10.1109/pesc.2004.241075.

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Rogozhin, A. E., I. A. Khorin, D. G. Drozdov, and A. G. Vasiliev. "Modeling of vertical transistor with electrically variable junctions in ISE TCAD." In SPIE Proceedings, edited by Kamil A. Valiev and Alexander A. Orlikovsky. SPIE, 2008. http://dx.doi.org/10.1117/12.802536.

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4

Zhang Bing, Chai Changchun, Ding Ruixue, and Xi Xiaowen. "Design of a novel dual pathway ESD protection device using ISE-TCAD." In 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA). IEEE, 2009. http://dx.doi.org/10.1109/ipfa.2009.5232615.

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Agapov, A. M. "Modeling of the SOI structures in layers of amorphous silicon using the ISE TCAD." In 2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551). IEEE, 2004. http://dx.doi.org/10.1109/pesc.2004.241079.

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Kaur, R., R. Chaujar, M. Saxena, and R. S. Gupta. "TCAD performance investigation of a novel MOSFET architecture of dual material gate insulated shallow extension silicon on nothing (DMG ISE SON) MOSFET for ULSI era." In 2008 Asia Pacific Microwave Conference. IEEE, 2008. http://dx.doi.org/10.1109/apmc.2008.4958643.

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Reports on the topic "Ise-tcad"

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Chow, Louis C., and Robert J. Mauriello. Utilizing ISE-TCAD Software to Simulate Power MOSFET Devices Operating at Cryogenic Temperatures. Fort Belvoir, VA: Defense Technical Information Center, April 2001. http://dx.doi.org/10.21236/ada387644.

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