Journal articles: 'Ise-tcad'

1

Chen, Ying-Yu, and Yu-Hsien Lin. "Comparison of bulk FinFET and SOI FinFET." MATEC Web of Conferences 201 (2018): 02009. http://dx.doi.org/10.1051/matecconf/201820102009.

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In this study, we compare the differences and advantages between Bulk FinFET and SOI FinFET. The results are simulated by using the ISE TCAD software. By changing the parameters of the gate voltage, drain voltage and gate length to analysis which characteristic is better. Through the experiment results, we demonstrate that the SOI FinFET have the better characteristics than bulk FinFET[1].

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Sun, Ying, Wei Guo, and Da Zhong Zhu. "Design and Research of Trench-Isolated LAPS Sensor Array." Applied Mechanics and Materials 734 (February 2015): 71–74. http://dx.doi.org/10.4028/www.scientific.net/amm.734.71.

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A new kind of SOI LAPS sensor array with trench and heavy doping structure was proposed. Photo current response, noise isolation and device performance were simulated with ISE-TCAD tools. The new structure LAPS sensor array effectively improves noise separation characteristics of adjacent array units. The SNR (signal-to-noise ratio) of LAPS array with trench-isolated structure is superior to that with only heavy doping regions. Trench isolation structure also improves the integration scales of LAPS array.

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Xu, Xiao Bo, He Ming Zhang, Hui Yong Hu, Jian Li Ma, and Li Jun Xu. "Generalized Early Voltage Model of Bipolar Transistors for Linearly Graded Germanium in Base." Applied Mechanics and Materials 110-116 (October 2011): 3311–15. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.3311.

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The standard Early voltage of the SPICE Gummel-Poon model (SGP) is generalized for SiGe npn heterojunction bipolar transistors (HBTs). An accurate model for Early effects compatible with the SGP model is obtained considering graded germanium induced bandgap narrowing effect in the base in modern SiGe HBTs and simplified to a compact model which is consistent with ISE TCAD simulation results. The presentation of the Early effect model is significant for the design and simulation of the high performance SiGe BiCMOS technology.

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Maragliano, C., M. Stefancich, S. Rampino, and L. Colace. "Realistic simulation of polycrystalline CIGS absorbers and experimental verification." MRS Proceedings 1493 (2013): 153–60. http://dx.doi.org/10.1557/opl.2013.401.

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AbstractCu(InGa)Se2 solar cells modeling is challenging due to their complex electronic structure, to the presence of interface states between layer and grains and to the microcrystalline structure of the absorber. Here we present a ISE-TCAD based realistic absorber 3D model, with the specific objective to take into account, among several effects, these challenging aspects. The CdS/Cu(InGa)Se2 solar cell is modeled as an array of columnar microcells, connected in parallel, mimicking the polycrystalline nature of the absorber. The model optical and electrical parameters are optimized based on a review of available experimental material characterization and realization results. Simulation outcomes are compared with experimental data in order to validate the model.

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Eun, Dong, Li Chang, Cheol Sang, Kyun Nam, Qui Jian, and Bin Ji. "Design of High-Power Reverse-Conducting Gate-Commutated Thyristors." Facta universitatis - series: Electronics and Energetics 15, no. 1 (2002): 41–50. http://dx.doi.org/10.2298/fuee0201041e.

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Different structures of Reserve-Conducting Gate-Commutated\break Thyristor (RC-GCT) are considered in this paper. The non-punch-through and punch-through structures were recommended for blocking voltages of 2.5 kV and 4.5 kV, respectively. The photomasks were designed upon the high turn-off capability of GCT and the monolithic integration of GCT and free wheeling diode (FWD). For a large-diameter RC-GCT device with a high turn-off current capacity, FWD and GCT were designed at the center region and the outer part of wafer, respectively. Mixed mode simulation results using the ISE-TCAD simulators give turn-on and turn-off waveforms of the considered structures. A modified isolation structure between GCT and FWD is proposed for RC-GCT.

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6

Sh. HUSSEIN, A., Z. HASSAN, H. ABU HASSAN, and S. M. THAHAB. "ELECTRICAL PROPERTIES OF AlGaN/GaN HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS (HFETs) WITH AND WITHOUT Mg-DOPED CARRIER CONFINEMENT LAYER." International Journal of Nanoscience 09, no. 04 (August 2010): 263–67. http://dx.doi.org/10.1142/s0219581x10006776.

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AlGaN/GaN -based heterostructure field-effect transistors (HFETs) with and without Mg -doped semi-insulating carrier confinement layer were simulated by using ISE TCAD software, respectively. The detailed study on the electrical properties of these samples was performed. The effect of inserting Mg -doped GaN layer on the source–drain (S–D) leakage current was investigated. Higher values of drain current and extrinsic transconductance were achieved with conventional HFETs (without Mg -doped). The source-to-drain (S–D) leakage current of conventional HFETs was also higher. However, the S–D leakage current was reduced with the insertion of the Mg -doped semi-insulating carrier confinement layer. Our results are in good agreement with the experimental results obtained by other researchers.

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7

Jia, Hujun, Yuan Liang, Tao Li, Yibo Tong, Shunwei Zhu, Xingyu Wang, Tonghui Zeng, and Yintang Yang. "Improved DRUS 4H-SiC MESFET with High Power Added Efficiency." Micromachines 11, no. 1 (December 27, 2019): 35. http://dx.doi.org/10.3390/mi11010035.

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A 4H-SiC metal semiconductor field effect transistor (MESFET) with layered doping and undoped space regions (LDUS-MESFET) is proposed and simulated by ADS and ISE-TCAD software in this paper. The structure (LDUS-MESFET) introduced layered doping under the lower gate of the channel, while optimizing the thickness of the undoped region. Compared with the double-recessed 4H-SiC MESFET with partly undoped space region (DRUS-MESFET), the power added efficiency of the LDUS-MESFET is increased by 85.8%, and the saturation current is increased by 27.4%. Although the breakdown voltage of the device has decreased, the decrease is within an acceptable range. Meanwhile, the LDUS-MESFET has a smaller gate-source capacitance and a large transconductance. Therefore, the LDUS-MESFET can better balance DC and AC characteristics and improve power added efficiency (PAE).

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8

Alahyarizadeh, Ghasem, Hassan Zainuriah, Sabah M. Thahab, Maryam Amirhoseiny, and Alaa J. Ghazai. "Effects of Cavity Length on Optical Characteristics of Deep Violet InGaN DQW Lasers." Advanced Materials Research 626 (December 2012): 605–9. http://dx.doi.org/10.4028/www.scientific.net/amr.626.605.

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The performance characteristics and their dependence to cavity length of deep violet InGaN DQW lasers emitting at 390 nm have been investigated using the Integrated System Engineering Technical Computer Aided Design (ISE TCAD) software. The focus of simulation was on the study of optical properties which were carried out with varying cavity length from 200µm to 600µm. The simulation results indicated that the cavity length strongly affects the optical properties of the violet InGaN DQW laser. They showed that the parameters related to the output power such as optical intensity increases by increasing cavity length due to increase of applied current to the laser system. The results also indicated that the parameters such as optical material gain, stimulated and radiative recombination which are related to quantum efficiencies and laser performance decrease by increasing cavity length. It was shown that the laser structure with the longer cavity length has the lower optical loss.

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9

Jia, Hujun, Yibo Tong, Tao Li, Shunwei Zhu, Yuan Liang, Xingyu Wang, Tonghui Zeng, and Yintang Yang. "An Improved 4H-SiC MESFET with a Partially Low Doped Channel." Micromachines 10, no. 9 (August 23, 2019): 555. http://dx.doi.org/10.3390/mi10090555.

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An improved 4H-SiC metal semiconductor field effect transistor (MESFET) based on the double-recessed MESFET (DR-MESFET) for high power added efficiency (PAE) is designed and simulated in this paper and its mechanism is explored by co-simulation of ADS and ISE-TCAD software. This structure has a partially low doped channel (PLDC) under the gate, which increases the PAE of the device by decreasing the absolute value of the threshold voltage (Vt), gate-source capacitance (Cgs) and saturation current (Id). The simulated results show that with the increase of H, the PAE of the device increases and then decreases when the value of NPLDC is low enough. The doping concentration and thickness of the PLDC are respectively optimized to be NPLDC = 1 × 1015 cm−3 and H = 0.15 μm to obtain the best PAE. The maximum PAE obtained from the PLDC-MESFET is 43.67%, while the PAE of the DR-MESFET is 23.43%; the optimized PAE is increased by 86.38%.

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10

Alahyarizadeh, Gh, M. Amirhoseiny, and Z. Hassan. "Effect of QW thickness and numbers on performance characteristics of deep violet InGaN MQW lasers." International Journal of Modern Physics B 29, no. 13 (May 18, 2015): 1550081. http://dx.doi.org/10.1142/s0217979215500812.

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The performance characteristics of deep violet indium gallium nitride (InGaN) multiquantum well (MQW) laser diodes (LDs) with an emission wavelength of around 390 nm have been investigated using the integrated system engineering technical computer aided design (ISE-TCAD) software. A comparative study on the effect of quantum well (QW) thickness and number on electrical and optical performance of deep violet In 0.082 Ga 0.918 N/GaN MQW LDs have been carried out. The simulation results showed that the highest slope efficiency and external differential quantum efficiency (DQE), as well as the lowest threshold current are obtained when the number of wells is two. The different QW thickness values of 2.2, 2.5, 2.8, 3 and 3.2 nm were compared and the best results were achieved for 2.5 nm QW thickness. The radiative recombination rate decreases with increasing QW thickness because of decreasing electron and hole carrier densities in wells. By increasing QW thickness, output power decreases and threshold current increases.

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11

Yuan, Bo, Shi Bin Chen, and Xiao Jia. "Analysis and Simulation of Temperature and I-V Characteristics for SiC Schottky Barrier Diodes." Advanced Materials Research 875-877 (February 2014): 690–94. http://dx.doi.org/10.4028/www.scientific.net/amr.875-877.690.

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In this paper, semiconductor simulation software ISE TCAD 10.0 was used to simulate W/SiC SBD forward voltage characteristics and reverse voltage characteristics at different temperatures on the basis of theoretical analysis, and the valuable results were achieved. Under the temperature range from 73 K to 773 K, the simulation results of W/SiC Schottky barrier diode forward voltage characteristics showed that forward characteristics were significant influenced by the temperature. At room temperature (303K), if bias voltage was low, the current will be exponential growing with voltage, and the turn-on voltage of W/SiC Schottky barrier diode was about 0.2V. If bias voltage was high, the current increased will be high, and the series resistance effect will become obvious. Under lower bias (2V), a different temperature from 73K to 573K had small impact on reverse current-voltage characteristics. The results showed that the device had the good rectifier characteristics, small reverse current, high breakdown voltage, and the device can steadily and long-term work in high temperature and other complex environment.

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12

Goharrizi, A. Zandi, Gh Alahyarizadeh, Z. Hassan, and H. Abu Hassan. "The influence of quaternary electron blocking layer on the performance characteristics of intracavity-contacted oxide-confined InGaN-based vertical cavity surface emitting lasers." International Journal of Modern Physics B 29, no. 31 (December 2015): 1550230. http://dx.doi.org/10.1142/s0217979215502306.

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The effect of electron blocking layer (EBL) on the performance characteristics of InGaN-based vertical cavity surface emitting lasers (VCSELs) was numerically investigated using an integrated system engineering technical computer aided design (ISE TCAD) simulation program. Simulation results indicated that the performance characteristics of InGaN quantum well VCSEL were improved by the ternary [Formula: see text] EBL. Better performance was also obtained when [Formula: see text] EBL was replaced by a polarization-matched [Formula: see text] EBL having the same energy bandgap. The quaternary EBL enhances the output power and differential quantum efficiency (DQE) as well as reduces the threshold current compared with the ternary EBL. Enhancement in the value of the optical intensity was also observed in the VCSEL structure with quaternary EBL. Furthermore, the effect of Al composition of AlInGaN EBL on the performance of InGaN-based VCSEL structure that uses the quaternary AlInGaN EBL was studied. In mole fraction was 0.115, Al mole fraction changed from 0.260 to 0.290 by step 0.005, and optimum performance was achieved in 0.275 Al mole fraction of AlInGaN EBL.

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13

Chien, Feng-Tso, Jing Ye, Wei-Cheng Yen, Chii-Wen Chen, Cheng-Li Lin, and Yao-Tsung Tsai. "Raised Source/Drain (RSD) and Vertical Lightly Doped Drain (LDD) Poly-Si Thin-Film Transistor." Membranes 11, no. 2 (February 1, 2021): 103. http://dx.doi.org/10.3390/membranes11020103.

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The raised source/drain (RSD) structure is one of thin film transistor designs that is often used to improve device characteristics. Many studies have mentioned that the high impact ionization rate occurring at a drain side can be reduced, owing to a raised source/drain area that can disperse the drain electric field. In this study, we will discuss how the electric field at the drain side of an RSD device is reduced by a vertical lightly doped drain (LDD) scheme rather than a RSD structure. We used different raised source/drain forms to simulate the drain side electric field for each device, as well as their output characteristics, using Integrated Systems Engineering (ISE-TCAD) simulators. Different source and drain thicknesses and doping profiles were applied to verify the RSD mechanism. We found that the electric fields of a traditional device and uniform doping RSD structures are almost the same (~2.9 × 105 V/cm). The maximum drain electric field could be reduced to ~2 × 105 V/cm if a vertical lightly doped drain RSD scheme was adopted. A pure raised source/drain structure did not benefit the device characteristics if a vertical lightly doped drain design was not included in the raised source/drain areas.

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14

Chien, Feng-Tso, Zhi-Zhe Wang, Cheng-Li Lin, Tsung-Kuei Kang, Chii-Wen Chen, and Hsien-Chin Chiu. "150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers." Micromachines 11, no. 5 (May 15, 2020): 504. http://dx.doi.org/10.3390/mi11050504.

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A rating voltage of 150 and 200 V split-gate trench (SGT) power metal-oxide- semiconductor field-effect transistor (Power MOSFET) with different epitaxial layers was proposed and studied. In order to reduce the specific on-resistance (Ron,sp) of a 150 and 200 V SGT power MOSFET, we used a multiple epitaxies (EPIs) structure to design it and compared other single-EPI and double-EPIs devices based on the same fabrication process. We found that the bottom epitaxial (EPI) layer of a double-EPIs structure can be designed to support the breakdown voltage, and the top one can be adjusted to reduce the Ron,sp. Therefore, the double-EPIs device has more flexibility to achieve a lower Ron,sp than the single-EPI one. When the required voltage is over 100 V, the on-state resistance (Ron) of double-EPIs device is no longer satisfying our expectations. A triple-EPIs structure was designed and studied, to reduce its Ron, without sacrificing the breakdown voltage. We used an Integrated System Engineering-Technology Computer-Aided Design (ISE-TCAD) simulator to investigate and study the 150 V SGT power MOSFETs with different EPI structures, by modulating the thickness and resistivity of each EPI layer. The simulated Ron,sp of a 150 V triple-EPIs device is only 62% and 18.3% of that for the double-EPIs and single-EPI structure, respectively.

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15

Jia, Hujun, Xiaowei Wang, Mengyu Dong, Shunwei Zhu, and Yintang Yang. "An Improved P-Type Doped Barrier Surface AlGaN/GaN High Electron Mobility Transistor with High Power-Added Efficiency." Micromachines 12, no. 9 (August 28, 2021): 1035. http://dx.doi.org/10.3390/mi12091035.

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An improved P-type doped barrier surface AlGaN/GaN high electron mobility transistor with high power-added efficiency (PDBS-HEMT) is proposed in this paper. Through the modelling and simulation of ISE-TCAD and ADS software, the influence of the P-type doped region on the performance parameters is studied, and the power-added efficiency (PAE) obtained and effectively improved is further verified. The drain saturation current and the threshold voltage of PDBS-HEMT has no major change compared with the traditional structure; the peak transconductance decreases slightly, but the breakdown voltage is significantly enhanced. Furthermore, the gate-source capacitance and gate-drain capacitance are reduced by 14.6% and 14.3%, respectively. By simulating the RF output characteristics of the device, the maximum oscillation frequency of the proposed structure is increased from 57 GHz to 63 GHz, and the saturated output power density is 10.9 W/mm, 9.3 W/mm and 6.4 W/mm at the frequency of 600 MHz, 1200 MHz and 2400 MHz, respectively. The highest PAE of 88.4% was obtained at 1200 MHz. The results show that the PDBS structure has an excellent power and efficiency output capability. Through the design of the P-type doped region, the DC and RF parameters and efficiency of the device are balanced, demonstrating the great potential of PDBS structure in high energy efficiency applications.

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16

Verma, Ajay K., Philip Brisk, and Paolo Ienne. "Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, no. 3 (March 2010): 341–54. http://dx.doi.org/10.1109/tcad.2010.2041849.

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17

Agapov, Aleksey M., Valeri V. Kalinin, Alexandre M. Myasnikov, Vincent M. C. Poon, and Bert Vermeire. "TCAD Modeling of Metal Induced Lateral Crystallization of Amorphous Silicon." MRS Proceedings 862 (2005). http://dx.doi.org/10.1557/proc-862-a6.6.

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AbstractIn our previous publications [1, 2] nickel diffusion and spreading resistance probe (SRP) measurements for quality control of metal induced lateral crystallization (MILC) of amorphous silicon (a-Si) were studied. Now we present TCAD modeling and an explanation of experimental results. By using ISE TCAD the Ni concentration distributions were calculated and compared with results obtained by experiments using SIMS analysis.

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18

Watabe, Yuki, Taku Tajima, and Tohru Nakamura. "Degradation of Current Gain for Ion Implanted 4H-SiC Bipolar Junction Transistor." MRS Proceedings 1195 (2009). http://dx.doi.org/10.1557/proc-1195-b08-04.

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AbstractDegradation of current gain for ion implanted 4H-SiC bipolar junction transistor is described. The influence of bandgap-narrowing to the collector and base currents of the transistor was investigated using ISE-TCAD simulator. Simulated results show good agreement with the measured results, which show that the common emitter current gain of 3.9 is obtained at a maximum base concentration of 2×1017/cm3 and a maximum emitter concentration of 4×1019/cm3 for ion implanted 4H-SiC BJTs.

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19

Jin, Yawei, Lei Ma, Chang Zeng, Krishnanshu Dandu, and Doug William Barlage. "Structure and Process Parameter Optimization for Sub-10nm Gate Length Fully Depleted N-Type SOI MOSFETs by TCAD Modeling and Simulation." MRS Proceedings 913 (2006). http://dx.doi.org/10.1557/proc-0913-d01-10.

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AbstractAccording to most recent 2004 International Technology Roadmap for Semiconductor (2004 ITRS), the high performance (HP) MOSFET physical gate length will be scaled to 9nm (22nm technology node) in 2016. We investigate the manufacturability of this sub-10nm gate length fully depleted SOI MOSFET by TCAD simulation. The commercial device simulator ISE TCAD is used. While it is impractical for experiments currently, this study can be used to project performance goals for aggressively scaled devices. In this paper, we will optimize different structure and process parameters at this gate length, such as body thickness, oxide thickness, spacer width, source/drain doping concentration, source/drain doping abruptness, channel doping concentration etc. The sensitivity of device electrical parameters, such as Ion, Ioff, DIBL, Sub-threshold Swing, threshold voltage, trans-conductance etc, to physical variations will be considered. The main objective of this study is to identify the key design issues for sub-10nm gate length Silicon based fully depleted MOSFET at the end of the ITRS. The paper will present the final optimized device structure and optimized performance will be reported.

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20

Ma, Lei, Yawei Jin, Chang Zeng, Krishnanshu Dandu, Mark Johnson, and Doug William Barlage. "TCAD Modeling and Simulation of Sub-100nm Gate Length Silicon and GaN based SOI MOSFETs." MRS Proceedings 913 (2006). http://dx.doi.org/10.1557/proc-0913-d05-09.

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AbstractSub-100nm gate length silicon and GaN based SOI n-type MOSFET are modeled and simulated using ISE-TCAD (now synopsys_sentaurus). Several silicon SOI structures such as planar fully depleted SOI, FinFET, Tri-Gate MOSFET, cylindrical channel (OMFET) and triangular channel MOSFETs have been studied to compare the structure dependence of the device performance. Silicon and GaN as channel materials are also compared for these different SOI structures for projecting the device performance for very short channel SOI MOSFETs. Our study shows that for sub-100nm gate length, GaN based transistors have better Ion/Ioff ratio and higher small signal transconductance than silicon based transistors. And GaN and Si based devices have comparable performance such as sub-threshold slope and threshold roll off, etc. However for sub 20nm gate length, simulation shows that while it is not satisfying for silicon based device for digital applications, GaN based transistors with lower off state leakage current, less short channel effect than Silicon based transistors are still good candidates for digital applications . The TCAD study shows that GaN could be a promising candidate for making very short channel device as the GaN processing technology is advancing.

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Journal articles on the topic 'Ise-tcad'

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