Academic literature on the topic 'Iterative Logic Array'
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Journal articles on the topic "Iterative Logic Array"
Ye, B. Y., I. Y. Chen, S. Y. Kuo, and P. Y. Yeh. "Scalable and bijective cells for C-testable iterative logic array architectures." IET Circuits, Devices & Systems 3, no. 4 (2009): 172–81. http://dx.doi.org/10.1049/iet-cds.2008.0296.
Full textVarma, P., and Y. Tohma. "A knowledge-based test generator for standard cell and iterative array logic circuits." IEEE Journal of Solid-State Circuits 23, no. 2 (1988): 428–36. http://dx.doi.org/10.1109/4.1003.
Full textMiyazaki, Daisuke, Sunao Kakizaki, Tsuyoshi Konishi, Jun Tanida, and Yoshiki Ichioka. "Iterative processing on a hybrid optical parallel array logic system with a selectable coherent correlator." Applied Optics 32, no. 17 (1993): 3053. http://dx.doi.org/10.1364/ao.32.003053.
Full textDOKOUZYANNIS, STAVROS P., and ARGIRIS P. MOKIOS. "EVALUATION STUDY OF SYSTOLIC ARRAY PROCESSORS OPTIMIZATION AND MAPPING ON k-LUT FPGA DEVICES." Journal of Circuits, Systems and Computers 22, no. 04 (2013): 1350025. http://dx.doi.org/10.1142/s0218126613500254.
Full textChen-Wen Wu and P. R. Cappello. "Easily testable iterative logic arrays." IEEE Transactions on Computers 39, no. 5 (1990): 640–52. http://dx.doi.org/10.1109/12.53577.
Full textQinghong Wu, C. Y. R. Chen, and B. S. Carlson. "LILA: layout generation for iterative logic arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 14, no. 11 (1995): 1359–69. http://dx.doi.org/10.1109/43.469662.
Full textCheng, W. T., and J. H. Patel. "Testing in two-dimensional iterative logic arrays." Computers & Mathematics with Applications 13, no. 5-6 (1987): 443–54. http://dx.doi.org/10.1016/0898-1221(87)90074-5.
Full textBecker, Bernd, Ralf Hahn, Joachim Hartmann, and Uwe Sparmann. "On the testability of iterative logic arrays." Integration 18, no. 2-3 (1995): 201–18. http://dx.doi.org/10.1016/0167-9260(95)00002-w.
Full textLu, Shyue-Kung, Cheng-Wen Wu, and Ruei-Zong Hwang. "Cell delay fault testing for iterative logic arrays." Journal of Electronic Testing 9, no. 3 (1996): 311–16. http://dx.doi.org/10.1007/bf00134694.
Full textShyue-Kung Lu, Jen-Chuan Wang, and Cheng-Wen Wu. "C-testable design techniques for iterative logic arrays." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3, no. 1 (1995): 146–52. http://dx.doi.org/10.1109/92.365462.
Full textDissertations / Theses on the topic "Iterative Logic Array"
Modi, Harmish Rajeshkumar. "In-System Testing of Configurable Logic Blocks in Xilinx 7-Series FPGAs." Thesis, Virginia Tech, 2015. http://hdl.handle.net/10919/55123.
Full textCHEN, YUN, and 陳雲. "Fault detection and location of iterative logic array." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/24416569214981023057.
Full textCHEN, CUN-MU, and 陳春木. "The testing of iterative logic array and matrix multiplier." Thesis, 1988. http://ndltd.ncl.edu.tw/handle/53231203482524722621.
Full textYeh, Po-Yuan, and 葉柏園. "Testable Iterative Logic Arrays Based on Scalable and Bijective Cells." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/66792575816595508407.
Full textLu, Mau-Jung, and 盧茂中. "BIST and DFT Techniques for Delay Faults Testing of Iterative Logic Arrays." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/68294205604193052076.
Full textBooks on the topic "Iterative Logic Array"
Book chapters on the topic "Iterative Logic Array"
Becker, Bernd, and Joachim Hartmann. "Some remarks on the test complexity of iterative logic arrays." In Mathematical Foundations of Computer Science 1992. Springer Berlin Heidelberg, 1992. http://dx.doi.org/10.1007/3-540-55808-x_12.
Full textCimatti, Alessandro, Alberto Griggio, and Gianluca Redondi. "Universal Invariant Checking of Parametric Systems with Quantifier-free SMT Reasoning." In Automated Deduction – CADE 28. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-79876-5_8.
Full textConference papers on the topic "Iterative Logic Array"
Ye, Bo-Yuan, Po-Yu Yeh, Sy-Yen Kuo, and Shyue-Kung Lu. "Scalable arithmetic cells for iterative logic array." In 2008 International Conference on Electrical and Computer Engineering. IEEE, 2008. http://dx.doi.org/10.1109/icece.2008.4769226.
Full textHratch Mangassarian, Andreas Veneris, Sean Safarpour, Marco Benedetti, and Duncan Smith. "A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test." In 2007 IEEE/ACM International Conference on Computer-Aided Design. IEEE, 2007. http://dx.doi.org/10.1109/iccad.2007.4397272.
Full textNicolaidis, M. "Improving the theory of truth table verification of iterative logic arrays." In Digest of Papers. 1992 IEEE VLSI Test Symposium. IEEE, 1992. http://dx.doi.org/10.1109/vtest.1992.232776.
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