Academic literature on the topic 'Iterative Logic Array'

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Iterative Logic Array.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Iterative Logic Array"

1

Ye, B. Y., I. Y. Chen, S. Y. Kuo, and P. Y. Yeh. "Scalable and bijective cells for C-testable iterative logic array architectures." IET Circuits, Devices & Systems 3, no. 4 (2009): 172–81. http://dx.doi.org/10.1049/iet-cds.2008.0296.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Varma, P., and Y. Tohma. "A knowledge-based test generator for standard cell and iterative array logic circuits." IEEE Journal of Solid-State Circuits 23, no. 2 (1988): 428–36. http://dx.doi.org/10.1109/4.1003.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Miyazaki, Daisuke, Sunao Kakizaki, Tsuyoshi Konishi, Jun Tanida, and Yoshiki Ichioka. "Iterative processing on a hybrid optical parallel array logic system with a selectable coherent correlator." Applied Optics 32, no. 17 (1993): 3053. http://dx.doi.org/10.1364/ao.32.003053.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

DOKOUZYANNIS, STAVROS P., and ARGIRIS P. MOKIOS. "EVALUATION STUDY OF SYSTOLIC ARRAY PROCESSORS OPTIMIZATION AND MAPPING ON k-LUT FPGA DEVICES." Journal of Circuits, Systems and Computers 22, no. 04 (2013): 1350025. http://dx.doi.org/10.1142/s0218126613500254.

Full text
Abstract:
This paper analyzes the design automation of embedded Systolic Array Processors (SAPs), into large scale Field Programmable Gate Array (FPGA) devices. SAPs are hardware implementations of a class of iterative, high-level language algorithms, for applications where the high-speed of processing has the principal meaning of a design. Embedding SAPs onto FPGAs is a complex process. The optimization phase in this process reduces the SAP significantly, thus less FPGA area is occupied by the embedded design, without any loss in the final performance. The present paper examines the effect of Projectio
APA, Harvard, Vancouver, ISO, and other styles
5

Chen-Wen Wu and P. R. Cappello. "Easily testable iterative logic arrays." IEEE Transactions on Computers 39, no. 5 (1990): 640–52. http://dx.doi.org/10.1109/12.53577.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Qinghong Wu, C. Y. R. Chen, and B. S. Carlson. "LILA: layout generation for iterative logic arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 14, no. 11 (1995): 1359–69. http://dx.doi.org/10.1109/43.469662.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Cheng, W. T., and J. H. Patel. "Testing in two-dimensional iterative logic arrays." Computers & Mathematics with Applications 13, no. 5-6 (1987): 443–54. http://dx.doi.org/10.1016/0898-1221(87)90074-5.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Becker, Bernd, Ralf Hahn, Joachim Hartmann, and Uwe Sparmann. "On the testability of iterative logic arrays." Integration 18, no. 2-3 (1995): 201–18. http://dx.doi.org/10.1016/0167-9260(95)00002-w.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Lu, Shyue-Kung, Cheng-Wen Wu, and Ruei-Zong Hwang. "Cell delay fault testing for iterative logic arrays." Journal of Electronic Testing 9, no. 3 (1996): 311–16. http://dx.doi.org/10.1007/bf00134694.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Shyue-Kung Lu, Jen-Chuan Wang, and Cheng-Wen Wu. "C-testable design techniques for iterative logic arrays." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3, no. 1 (1995): 146–52. http://dx.doi.org/10.1109/92.365462.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Dissertations / Theses on the topic "Iterative Logic Array"

1

Modi, Harmish Rajeshkumar. "In-System Testing of Configurable Logic Blocks in Xilinx 7-Series FPGAs." Thesis, Virginia Tech, 2015. http://hdl.handle.net/10919/55123.

Full text
Abstract:
FPGA fault recovery techniques, such as bitstream scrubbing, are only limited to detecting and correcting soft errors that corrupt the configuration memory. Scrubbing and related techniques cannot detect permanent faults within the FPGA fabric, such as short circuits and open circuits in FPGA transistors that arise from electromigration effects. Several Built-In Self-Test (BIST) techniques have been proposed in the past to detect and isolate such faults. These techniques suffer from routing congestion problems in modern FPGAs that have a large number of logic blocks. This thesis presents an im
APA, Harvard, Vancouver, ISO, and other styles
2

CHEN, YUN, and 陳雲. "Fault detection and location of iterative logic array." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/24416569214981023057.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

CHEN, CUN-MU, and 陳春木. "The testing of iterative logic array and matrix multiplier." Thesis, 1988. http://ndltd.ncl.edu.tw/handle/53231203482524722621.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Yeh, Po-Yuan, and 葉柏園. "Testable Iterative Logic Arrays Based on Scalable and Bijective Cells." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/66792575816595508407.

Full text
Abstract:
博士<br>臺灣大學<br>電子工程學研究所<br>98<br>In order to achieve testable designs, it is necessary to modify the original designs properly. For different applications, the modifications can be made at either module-level or bit-level circuits to achieve best results. In general, conventional test schemes at module-level or bit-level lead to large number of test patterns (NTP) or significant hardware overhead (HO), respectively. In order to circumvent these problems, we propose a novel test technique to achieve both acceptable NTP and HO by finding a balance between them in this paper. We propose novel bi
APA, Harvard, Vancouver, ISO, and other styles
5

Lu, Mau-Jung, and 盧茂中. "BIST and DFT Techniques for Delay Faults Testing of Iterative Logic Arrays." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/68294205604193052076.

Full text
Abstract:
碩士<br>輔仁大學<br>電子工程學系<br>91<br>Iterative Logic Arrays (ILAs) are widely used in many applications, e.g., general-purpose processors, digital signal processors, and embedded processors. The rapid growth in VLSI technology is increasing the degree of circuit integration. So more and more complicated testing and more realistic fault models such as sequential fault models and delay fault models should be used today. A cell delay fault occurs if and only if an input transition cannot be propagated to the cell’s output through a path in the cell in a specified clock period. It has been shown that all
APA, Harvard, Vancouver, ISO, and other styles

Books on the topic "Iterative Logic Array"

1

Hennie, Frederick. Iterative arrays of logical circuits. MIT-Press, 2003.

Find full text
APA, Harvard, Vancouver, ISO, and other styles

Book chapters on the topic "Iterative Logic Array"

1

Becker, Bernd, and Joachim Hartmann. "Some remarks on the test complexity of iterative logic arrays." In Mathematical Foundations of Computer Science 1992. Springer Berlin Heidelberg, 1992. http://dx.doi.org/10.1007/3-540-55808-x_12.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Cimatti, Alessandro, Alberto Griggio, and Gianluca Redondi. "Universal Invariant Checking of Parametric Systems with Quantifier-free SMT Reasoning." In Automated Deduction – CADE 28. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-79876-5_8.

Full text
Abstract:
AbstractThe problem of invariant checking in parametric systems – which are required to operate correctly regardless of the number and connections of their components – is gaining increasing importance in various sectors, such as communication protocols and control software. Such systems are typically modeled using quantified formulae, describing the behaviour of an unbounded number of (identical) components, and their automatic verification often relies on the use of decidable fragments of first-order logic in order to effectively deal with the challenges of quantified reasoning.In this paper, we propose a fully automatic technique for invariant checking of parametric systems which does not rely on quantified reasoning. Parametric systems are modeled with array-based transition systems, and our method iteratively constructs a quantifier-free abstraction by analyzing, with SMT-based invariant checking algorithms for non-parametric systems, increasingly-larger finite instances of the parametric system. Depending on the verification result in the concrete instance, the abstraction is automatically refined by leveraging canditate lemmas from inductive invariants, or by discarding previously computed lemmas.We implemented the method using a quantifier-free SMT-based IC3 as underlying verification engine. Our experimental evaluation demonstrates that the approach is competitive with the state of the art, solving several benchmarks that are out of reach for other tools.
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Iterative Logic Array"

1

Ye, Bo-Yuan, Po-Yu Yeh, Sy-Yen Kuo, and Shyue-Kung Lu. "Scalable arithmetic cells for iterative logic array." In 2008 International Conference on Electrical and Computer Engineering. IEEE, 2008. http://dx.doi.org/10.1109/icece.2008.4769226.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Hratch Mangassarian, Andreas Veneris, Sean Safarpour, Marco Benedetti, and Duncan Smith. "A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test." In 2007 IEEE/ACM International Conference on Computer-Aided Design. IEEE, 2007. http://dx.doi.org/10.1109/iccad.2007.4397272.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Nicolaidis, M. "Improving the theory of truth table verification of iterative logic arrays." In Digest of Papers. 1992 IEEE VLSI Test Symposium. IEEE, 1992. http://dx.doi.org/10.1109/vtest.1992.232776.

Full text
APA, Harvard, Vancouver, ISO, and other styles
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!