Journal articles: 'JFET SiC normally-on'

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Casady, Jeff B., David C. Sheridan, Robin L. Kelley, Volodymyr Bondarenko, and Andrew Ritenour. "A Comparison of 1200 V Normally-OFF & Normally-on Vertical Trench SiC Power JFET Devices." Materials Science Forum 679-680 (March 2011): 641–44. http://dx.doi.org/10.4028/www.scientific.net/msf.679-680.641.

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Equivalent sized (4.5 mm2 die area), 1200 V, 4H-SiC, vertical trench Junction Field Effect Transistors (JFETs) were characterized in terms of DC and switching performance. The 100 mΩ Enhancement-Mode (EM) JFET was found to have natural advantages in safe operation being normally-off, whereas the Depletion-Mode (DM) JFET was found to have advantages with ~ twice as high saturation current, less on-resistance (85 mΩ) and no gate current required in the on-state. The JFETs were found to both have radically less (five to ten times) switching energies than corresponding 1200 V Si transistors, with the DM JFET and EM JFET having EON and EOFF of only 115 µJ and 173 µJ, respectively when tested at half-rated voltage (600 V) and 12 A.

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Rueschenschmidt, Kathrin, Michael Treu, Roland Rupp, Peter Friedrichs, Rudolf Elpelt, Dethard Peters, and Peter Blaschitz. "SiC JFET: Currently the Best Solution for an Unipolar SiC High Power Switch." Materials Science Forum 600-603 (September 2008): 901–6. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.901.

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Today a main focus in high efficiency power electronics based on silicon carbide (SiC) lies on the development of an unipolar SiC switch. This paper comments on the advantages of SiC switching devices in comparison to silicon (Si) switches, the decision for the SiC JFET against the SiC MOSFET, and will show new experimental results on SiC JFETs with focus on the production related topics like process window and parameter homogeneity which can be achieved with the presented device concept. Due to material properties unipolar SiC switches have, other than their Si high voltage counterparts, very low gate charge, good body diode performance, and reduced switching losses because of the potential of lower in- and output capacitances. The most common unipolar switch is the MOSFET. However, the big challenge in the case of a SiC MOSFET is the gate oxide. A gate oxide on SiC that provides adequate performance and reliability is missing until now. An alternative unipolar switching device is a normally-on JFET. The normally-on behavior is a benefit for current driven applications. If a normally-off behavior is necessary the JFET can be used together with a low voltage Si MOSFET in a cascode arrangement. Recently manufactured SiC JFETs show results in very good accordance to device simulation and demonstrate the possibility to fabricate a SiC JFET within a mass production. A growing market opportunity for such a SiC switch becomes visible.

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McNutt, Ty, John Reichl, Harold Hearne, Victor Veliadis, Megan McCoy, Eric J. Stewart, Stephen Van Campen, et al. "Demonstration of High-Voltage SiC VJFET Cascode in a Half-Bridge Inverter." Materials Science Forum 556-557 (September 2007): 979–82. http://dx.doi.org/10.4028/www.scientific.net/msf.556-557.979.

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This work utilizes silicon carbide (SiC) vertical JFETs in a cascode configuration to exploit the inherent advantages of SiC and demonstrate the device under application conditions. The all-SiC cascode circuit is made up of a low-voltage normally-off vertical JFET, and high-voltage normally on vertical JFET to form a normally-off cascode switch. In this work, a half-bridge inverter was developed with SiC cascode switches for DC to AC power conversion. The inverter uses high-side and a low-side cascode switches that are Pulse Width Modulated (PWM) from a 500 V bus to produce a 60 Hz sinusoid at the output. An inductor and a capacitor were used to filter the output, while a load resistor was used to model the steady-state current of a motor.

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Malhan, Rajesh Kumar, S. J. Rashid, Mitsuhiro Kataoka, Yuuichi Takeuchi, Naohiro Sugiyama, F. Udrea, G. A. J. Amaratunga, and T. Reimann. "Switching Performance of Epitaxially Grown Normally-Off 4H-SiC JFET." Materials Science Forum 600-603 (September 2008): 1067–70. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.1067.

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Static and dynamic behavior of the epitaxially grown dual gate trench 4H-SiC junction field effect transistor (JFET) is investigated. Typical on-state resistance Ron was 6 – 10mΩcm2 at VGS = 2.5V and the breakdown voltage between the range of 1.5 – 1.8kV was realized at VGS = −5V for normally-off like JFETs. It was found that the turn-on energy delivers the biggest part of the switching losses. The dependence of switching losses from gate resistor is nearly linear, suggesting that changing the gate resistor, a way similar to Si-IGBT technology, can easily control di/dt and dv/dt. Turn-on losses at 200°C are lower compared to those at 25°C, which indicates the influence of the high internal p-type gate layer resistance. Inductive switching numerical analysis suggested the strong influence of channel doping conditions on the turn-on switching performance. The fast switching normally-off JFET devices require heavily doped narrow JFET channel design.

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Cheng, Lin, Michael S. Mazzola, and David C. Sheridan. "High-Temperature Reliability Assessment of 4H-SiC Vertical-Channel JFET Including Forward Bias Stress." Materials Science Forum 615-617 (March 2009): 723–26. http://dx.doi.org/10.4028/www.scientific.net/msf.615-617.723.

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In this work, we report the most recent reliability results of the 1200-V SiC vertical-channel JFETs (VJFETs) under reverse and forward bias of the gate-source diode at temperatures up to 200 °C. The preliminary results indicate that continuous forward bias stress of the gate-source diode at 200 °C for 112 hours produced no observable change in the forward conduction or transient or reverse blocking characteristics of the vertical-channel JFET. This preliminary result suggests that devices based on this structure, such as the enhancement-mode (normally off) SiC VJFET, may not be effected by the recombination enhanced defect creation process and the associated increase in on-resistance, related to body-diode conduction in the SiC DMOSFET and the SiC lateral-channel depletion-mode JFET. Since the vertical-channel JFET has no body diode, no degradation is possible from the reverse conduction mode of operation.

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Kang, In Ho, Sung Jae Joo, Wook Bahng, Sang Cheol Kim, and Nam Kyun Kim. "Design and Characterization of 50W Switch Mode Power Supply Using Normally-On SiC JFET." Materials Science Forum 645-648 (April 2010): 1151–54. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.1151.

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The 50W Quasi-resonant mode SMPS which adopted a normally-on-type SiC JFET as a switch has been designed and characterized. A simple decision circuit and an auxiliary power supply was utilized to safely protect the JFET from an in-rush current at initial operation stage and to provide sufficient negative voltage for a complete JFET drive. Even without a refine engineering, the SMPS showed 96% efficiency at a full load state.

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Dubois, Fabien, Hervé Morel, Dominique Bergogne, and Régis Meuret. "Modeling of the Punch-Through Effect in Normally-On SiC JFET used in High Temperature Inverter for Aerospace Application." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (January 1, 2012): 000154–61. http://dx.doi.org/10.4071/hitec-2012-wa14.

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This paper presents a qualitative description of the punch-through mechanism in Silicon Carbide (SiC) JFET from Infineon/SiCED. A detailed one-dimensional analytical expression is derived for the current-voltage characteristic of the punch-through effect in the SiC JFET. The proposed model based on physical parameters is validated with experimental results for low current level.

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Henfling, Joseph A., Stan Atcitty, and Frank Maldonado. "Enhanced High Temperature Power Controller." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, HITEN (January 1, 2011): 000134–38. http://dx.doi.org/10.4071/hiten-paper1-jhenfling.

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This paper describes an implementation strategy used to develop a high temperature power controller. The system is based on using high-temperature (HT) silicon-on-insulator (SOI) technology with silicon carbide (SiC) based integrated circuits (ICs) to create an efficient, high-temperature power controller. Two drives were tested with this system, one using normally off JFET switching and the other using MOSFET switching. Normally off JFETs made from SiC were used to drive the output loads. Such circuit designs will improve the efficiency of future smart grid power controllers.

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Godignon, Phillippe, Silvia Massetti, X. Jordà, V. Soler, J. Moreno, D. Lopez, and E. Maset. "SiC Power Switches Evaluation for Space Applications Requirements." Materials Science Forum 858 (May 2016): 852–55. http://dx.doi.org/10.4028/www.scientific.net/msf.858.852.

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We have evaluated several SiC power switches available on the market, by defining and performing a global test campaign oriented to Space applications requirements, in order to define their main benefits but also the limits of current SiC technology. This allowed to identify a number of target applications where SiC could be used as a technology push for a new generation of space electronics units. Silicon devices qualified for space systems above 600V for the switches and 1200V for the rectifiers are not available due to performances limitations of Si. Among the typical static and dynamic characterization, we have performed temperature and power stress and HTRB tests. More remarkably, we have carried out a first batch of total dose and heavy ions radiation experiments on 3 types of power switches: normally-on JFET, normally-off JFET and power MOSFET. Due to its higher stability and radiation hardness, the normally-on JFET is today the more adequate and reliable switch for the space applications.

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Sankin, Igor, V. Bondarenko, Robin L. Kelley, and Jeff B. Casady. "SiC Smart Power JFET Technology for High-Temperature Applications." Materials Science Forum 527-529 (October 2006): 1207–10. http://dx.doi.org/10.4028/www.scientific.net/msf.527-529.1207.

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Wide bandgap semiconductor materials such as SiC or GaN are very attractive for use in high-power, high-temperature, and/or radiation resistant electronics. Monolithic or hybrid integration of a power transistor and control circuitry in a single or multi-chip wide bandgap power semiconductor module is highly desirable for such applications in order to improve the efficiency and reliability. This paper describes a new monolithic SiC JFET IC technology for high-temperature smart power applications that allows for on-chip integration of control circuitry and normally-off power switch. In order to demonstrate the feasibility of this technology, hybrid logic gates with maximum switching frequency > 20 MHz and normally-off 900 V power switch have been fabricated on alumina substrates using discrete enhanced and depletion mode vertical trench JFETs.

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Björk, Fanny, Michael Treu, Jochen Hilsenbeck, M. A. Kutschak, Daniel Domes, and Roland Rupp. "1200V SiC JFET in Cascode Light Configuration: Comparison versus Si and SiC Based Switches." Materials Science Forum 679-680 (March 2011): 587–90. http://dx.doi.org/10.4028/www.scientific.net/msf.679-680.587.

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A 1200 V SiC JFET has been demonstrated to achieve ultra-low switching losses ten times lower than for industrial grade 1200V Si IGBT. The low switching losses are also shown to compete with the fastest 600V class MOSFET in the market, yielding 1.1% higher PFC stage efficiency for 340 kHz switching frequency, when same device on-resistances were measured. The proposed normally-on JFET also differentiates over the IGBT by its purely Ohmic output characteristics without any voltage threshold, and by a monolithically integrated body diode with practically zero reverse recovery. In this paper we outline as well how the other pre-requisites for a 1200 V SiC switch in applications such as photovoltaic systems and UPS can be fulfilled by the proposed JFET solution: long-term reliability, product cost optimization by low specific on-resistance combined with reasonable process window expectations. Finally, a normally-off like safe operation behavior is ensured by a dedicated driving scheme utilizing a low-voltage Si MOSFET as protection device at system start-up and for system failure conditions.

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Ishikawa, Katsumi, Kaoru Katoh, Ayumu Hatanaka, Kazutoshi Ogawa, Haruka Shimizu, and Natsuki Yokoyama. "High-Speed Drive Circuit with Separate Source Terminal for 600 V / 40 A Normally-off SiC-JFET." Materials Science Forum 740-742 (January 2013): 1060–64. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.1060.

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When using JFETs with a threshold voltage lower than 2 V in a power supply system or inverter system, a high-speed drive circuit capable of precisely controlling the gate current and a mounting method are important to reduce the switching loss. In this paper, a drive circuit of a normally-off SiC-JFET with a separate source terminal is proposed and the effects are evaluated. By dividing the common source inductance and applying the speed-up capacitor, the turn-on time and turn-on energy losses can be decreased by 40% and 60%, respectively. A speed-up capacitor larger than 100 nF greatly decreases the rising time (tr) and turn-on energy losses. By applying the developed normally-off SiC-JFETs and proposed gate driver to PFC circuits and DC/DC circuits, a highly efficient power supply will be achieved.

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13

Steiner, B., S. B. Bayne, Victor Veliadis, H. C. Ha, D. Urciuoli, N. El Hinnawy, P. Borodulin, and C. Scozzie. "Reliable Operation of SiC Junction-Field-Effect-Transistor Subjected to over 2 Million 600-V Hard Switch Stressing Events." Materials Science Forum 740-742 (January 2013): 921–24. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.921.

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A necessity for the successful commercialization of SiC power devices is their long term reliability under the switching conditions encountered in the field. Normally-ON 1200 V SiC JFETs were stressed in repetitive hard-switching conditions to determine their fault handling capabilities. The switching pulses were generated from an RLC circuit, where energy initially stored in capacitors discharges through the JFET into a resistive load. The hard-switching included one million repetitive pulsed hard-switching events at 25 °C from a drain blocking-voltage of 600-V to an on-state current of 67 A, and an additional one million 600-V/63-A pulsed hard-switching events at 150 °C. The JFET conduction and blocking-voltage characteristics are virtually unchanged after over two million hard switching events proving the devices are reliable for handling high surge-current faults like those encountered in bidirectional circuit breaker applications.°

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Falahi, Khalil El, Luong Viêt Phung, Bruno Allard, Dominique Bergogne, and Fabien Dubois. "High temperature anti short circuit function for normally-on SiC JFET in an inverter leg configuration." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (January 1, 2012): 000087–92. http://dx.doi.org/10.4071/hitec-2012-tp14.

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The SiC JFET is commercially available as a normally-on device. In an inverter leg configuration, many temperature effects must be compensated. Moreover, specific safety functions have to be implemented and the JFET drivers are generally the best locations to implement latter requirements. The paper describes experimental results about a SOI CMOS core driver operated up to 250°C. Particularly, an option is presented to compensate for the decrease in the driver output current with temperature. It is also demonstrated primary results of the integration of an anti short-circuit solution previously verified as a hybrid vehicle. It is shown that the reactivity of the safety function is reduced to less than 5μs at 250°C compared to 100μs in earlier vehicle at 200°C.

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Dubois, Fabien, Dominique Bergogne, Damien Risaletto, Rémi Robutel, Hervé Morel, Régis Meuret, and Sonia Dhokkar. "High Temperature Inverter for Airborne Application." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (January 1, 2010): 000222–27. http://dx.doi.org/10.4071/hitec-fdubois-wa23.

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This paper reports the design, fabrication and experimental performance of a 2kW, 20kHz, High Temperature, three-phase, all-SiC JFET Voltage Source Inverter (VSI). The inverter includes a specific JFET driver and a DC-link capacitor. All these elements have been validated over a wide temperature range, between 25°C and 200°C. The power device used, a 1200V, 15A, JFET from SiCED has been characterized up to 200°C. An innovative reliable protection circuit for normally-on devices is also presented and validated.

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Veliadis, V., E. J. Stewart, H. Hearne, M. Snook, A. Lelis, and C. Scozzie. "A 9-kV Normally-on Vertical-Channel SiC JFET for Unipolar Operation." IEEE Electron Device Letters 31, no. 5 (May 2010): 470–72. http://dx.doi.org/10.1109/led.2010.2042030.

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Niu, Shi, Maxime Berthou, and Dominique Tournier. "Bulk Thickness and Short Circuit Capacity of a 1200V 4H-SiC VJFET." Materials Science Forum 821-823 (June 2015): 797–800. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.797.

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In many power electronic inverters, the gate drive failure may put the switch normally-on in short-circuit (SC) risk. The high power density generated thus leads rapidly to the transistor failure. This paper presents our study via electro-thermal simulation of a 1200 V JFET under short circuit. It provides deep insight of physical phenomena present in the JFET during the short-circuit and will allow further improvements and understanding of it.

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Lawson, Kevin, G. Alvarez, S. B. Bayne, Victor Veliadis, H. C. Ha, Damian Urciuoli, and C. Scozzie. "Reliable Operation of 1200-V SiC Vertical Junction-Field-Effect-Transistor Subjected to 16,000-Pulse Hard Switching Stressing." Materials Science Forum 717-720 (May 2012): 1021–24. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1021.

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A necessity for the successful commercialization of SiC power devices is their long term reliability under the switching conditions encountered in application. Normally-ON 1200 V SiC JFETs were stressed in hard-switching conditions to determine their fault handling capabilities. The hard-switching included single shot tests ranging from drain voltages of 100 V to 500 V and repetition rate tests at 1 Hz, 5 Hz, 10 Hz, and 100 Hz with peak currents exceeding 100 A (8 times the rated current at 250 W/cm22). The JFET conduction and blocking-voltage characteristics are unchanged after 4,000 pulsed and numerous single shot hard switching events proving the devices are reliable for handling high surge-current faults.

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Araújo, Samuel V., Benjamin Sahan, Peter Zacharias, Roland Rupp, and Xi Zhang. "Application of SiC Normally-On JFETs in Photovoltaic Power Converters: Suitable Circuits and Potentials." Materials Science Forum 645-648 (April 2010): 1111–14. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.1111.

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Photovoltaic systems have been considered as one of most promising fields of application for SiC semiconductors mainly due to the requirements for very high efficiency values. Several other system aspects like volume and cost may also profit from the interesting characteristics of such innovative devices. One promising example is the vertical JFET, mainly due to its relative structural simplicity. Nevertheless, its inherent normally-on characteristic calls for especially tailored topologies, as some suitable applications for photovoltaic systems will be presented.

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Vassilevski, Konstantin, Keith P. Hilton, Nicolas G. Wright, Michael J. Uren, A. G. Munday, Irina P. Nikitina, A. J. Hydes, Alton B. Horsfall, and C. Mark Johnson. "Silicon Carbide Vertical JFET Operating at High Temperature." Materials Science Forum 600-603 (September 2008): 1063–66. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.1063.

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Trenched and implanted vertical JFETs (TI-VJFETs) with blocking voltages of 700 V were fabricated on commercial 4H-SiC epitaxial wafers. Vertical p+-n junctions were formed by aluminium implantation in sidewalls of strip-like mesa structures. Normally-on 4H-SiC TI-VJFETs had specific on-state resistance (RO-S ) of 8 mW×cm2 measured at room temperature. These devices operated reversibly at a current density of 100 A/cm2 whilst placed on a hot stage at temperature of 500 °C and without any protective atmosphere. The change of RO-S with temperature rising from 20 to 500 °C followed a power law (~ T 2.4) which is close to the temperature dependence of electron mobility in 4H-SiC.

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URCIUOLI, D. P., and VICTOR VELIADIS. "BI-DIRECTIONAL SCALABLE SOLID-STATE CIRCUIT BREAKERS FOR HYBRID-ELECTRIC VEHICLES." International Journal of High Speed Electronics and Systems 19, no. 01 (March 2009): 183–92. http://dx.doi.org/10.1142/s0129156409006242.

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Power electronics in hybrid-electric military ground vehicles require fast fault isolation, and benefit additionally from bi-directional fault isolation. To prevent system damage or failure, maximum fault current interrupt speeds in tens to hundreds of microseconds are necessary. While inherently providing bi-directional fault isolation, mechanical contactors and circuit breakers do not provide adequate actuation speeds, and suffer severe degradation during repeated fault isolation. Instead, it is desired to use a scalable array of solid-state devices as a solid-state circuit breaker (SSCB) having a collectively low conduction loss to provide large current handling capability and fast transition speed for current interruption. Although, both silicon-carbide (SiC) JFET and SiC MOSFET devices having high breakdown voltages and low drain-to-source resistances have been developed, neither device structure alone is capable of reverse blocking at full voltage. Limitations exist for using a dual common-source structure for either device type. Small-scale SSCB experiments were conducted using 0.03 cm2 normally-on SiC VJFETs. Based on results of these tests, a normally-on VJFET device modification is made, and a proposed symmetric SiC JFET is considered for this application.

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Li, Yu Zhu, Petre Alexandrov, Jian Hui Zhang, Larry X. Li, and Jian Hui Zhao. "10 kV, 87 mΩcm² Normally-Off 4H-SiC Vertical Junction Field-Effect Transistors." Materials Science Forum 527-529 (October 2006): 1187–90. http://dx.doi.org/10.4028/www.scientific.net/msf.527-529.1187.

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SiC JFET, compared with SiC MOSFET, is attractive for high power, high temperature applications because it is free of gate oxide reliability issues. Trenched-and-Implanted VJFET (TIVJFET) does not require epi-regrowth and is capable of high current density. In this work we demonstrate two trenched-and-implanted normally-off 4H-SiC vertical junction field-effect transistors (TI-VJFET), based on 120μm, 4.9×1014cm-3 and 100μm, 6×1014cm-3 drift layers. The corresponding devices showed blocking voltage (VB) of 11.1kV and specific on-resistance (RSP_ON) of 124m7cm2, and VB of 10kV and RSP_ON of 87m7cm2. A record-high value for VB 2/RSP_ON of 1149MW/cm2 was achieved for normally-off SiC FETs.

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Akiyama, Satoru, Haruka Shimizu, Natsuki Yokoyama, Tomohiro Tamaki, Sadayuki Koido, Yoshikazu Tomizawa, Toyohiko Takahashi, and Takamitsu Kanazawa. "A 69-mΩ 600-V-Class Hybrid JFET." Materials Science Forum 740-742 (January 2013): 925–28. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.925.

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A hybrid silicon-carbide junction-gate field-effect transistor (HJT: hybrid JFET) is proposed. The HJT consists of a silicon-carbide (SiC) normally-on vertical JFET and a low-voltage normally-off silicon metal-oxide-semiconductor field-effect transistor (Si-MOS: silicon MOSFET). These two devices are connected by bonding wire as a cascode circuit [1] and packaged in a TO-3P split-lead-frame package with the same pin arrangement as conventional silicon power devices, which can thus be easily replaced by the proposed HJT. The vertical JFET has a steep-junction deep-trench structure in its channel region. This structure gives a low on-state resistance of under 60 mΩ and breakdown voltage of over 600 V with the die size of 6.25 mm2. Since the deep-trench structure also lowers the cutoff voltage of the JFET, required minimum breakdown voltage of the Si-MOS is reduced and on-state resistance of the Si-MOS is lowered. The HJT demonstrated on-state resistance of 69 mΩ and breakdown voltage of 783 V. These results indicate that the proposed HJT is a strong candidate for low-resistance high-power switching devices.

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Alexandrov, Petre, Xue Qing Li, and Jian Hui Zhao. "Optically Triggered Power Switch Based on 4H-SiC Vertical JFET." Materials Science Forum 679-680 (March 2011): 625–28. http://dx.doi.org/10.4028/www.scientific.net/msf.679-680.625.

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An optically controlled power switch based on 4H-SiC Trenched and Implanted Vertical JFETs (TIVJFET) was developed that comprises three parts: an LED light-source driver, light-triggered integrated gate buffer driver, and vertical high power normally-off switch. The light-triggered integrated gate buffer driver includes a photodiode and four stages of low voltage 4H-SiC TIVJFETs, which are hybrid integrated. Optically gated power switching was experimentally demonstrated with a maximum switching frequency of about 50 kHz, the system performance limiting factors were clearly identified and experimentally confirmed, and ways to substantially increase the switching frequency were shown. From calculations, based on realistically possible system parameters values, it could be seen that a maximum switching frequency around 1 MHz is theoretically possible with a proper choice of light source, detector, and buffer transistor parameters.

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Shimizu, Haruka, Yasuo Onose, Tomoyuki Someya, Hidekatsu Onose, and Natsuki Yokoyama. "Normally-Off 4H-SiC Vertical JFET with Large Current Density." Materials Science Forum 600-603 (September 2008): 1059–62. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.1059.

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We developed normally-off 4H-SiC vertical junction field effect transistors (JFETs) with large current density. The effect of forming an abrupt junction between the gate and the channel was simulated, and vertical JFETs were then fabricated with abrupt junctions. As a result, a large rated drain current density (500 A/cm2) and a low specific on-resistance (2.0 mWcm2) were achieved for small devices. The blocking voltage was 600 V. These results were due to a reduction of the threshold voltage by forming the abrupt junction between the gate and the channel.

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Vassilevski, Konstantin, Irina P. Nikitina, Alton B. Horsfall, Nicolas G. Wright, Andrew J. Smith, and C. Mark Johnson. "Silicon Carbide Vertical JFET with Self-Aligned Nickel Silicide Contacts." Materials Science Forum 679-680 (March 2011): 670–73. http://dx.doi.org/10.4028/www.scientific.net/msf.679-680.670.

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Trenched implanted vertical JFETs (TI-VJFETs) with self-aligned gate and source contacts were fabricated on commercial 4H-SiC epitaxial wafers. Gate regions were formed by aluminium implantation through the same silicon oxide mask which was used for etching mesa-structures. Self-aligned nickel silicide source and gate contacts were formed using a silicon oxide spacer formed on mesa-structure sidewalls by anisotropic thermal oxidation of silicon carbide followed by anisotropic reactive ion etching of oxide. Fabricated normally-on 4H-SiC TI-VJFETs demonstrated low gate leakage currents and blocking voltages exceeding 200 V.

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Koch, Immo, and Wolf Rüdiger Canders. "Discussion of Turn on Current Peaks of SiC Switches in Half Bridges." Materials Science Forum 645-648 (April 2010): 1177–80. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.1177.

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The optimal control parameters for semiconductor switches at the development state with new materials and structures are often unidentified. By using those sample switches with a gate control set by investigating one switch only, parasitic influences might lead to increased switching losses in half bridges [1, 2]. The focus of this paper is on an effect at turn on by using for example normally on JFET as high and low side switch. At this an increased current peak might occur which leads to higher switching losses. By adjusting the gate voltage losses can be economized.

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Lim, Jang Kwon, Georg Tolstoy, Dimosthenis Peftitsis, Jacek Rabkowski, Mietek Bakowski, and Hans Peter Nee. "Comparison of Total Losses of 1.2 kV SiC JFET and BJT in DC-DC Converter Including Gate Driver." Materials Science Forum 679-680 (March 2011): 649–52. http://dx.doi.org/10.4028/www.scientific.net/msf.679-680.649.

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The 1.2 kV SiC JFET and BJT devices have been investigated and compared with respect to total losses including the gate driver losses in a DC-DC converter configuration. The buried grid, Normally-on JFET devices with threshold voltage of -50 V and -10V are compared to BJT devices with ideal semiconductor and passivating insulator interface and an interface with surface recombination velocity of 4.5•104 cm/s yielding agreement to the reported experimental current gain values. The conduction losses of both types of devices are independent of the switching frequency while the switching losses are proportional to the switching frequency. The driver losses are proportional to the switching frequency in the JFET case but to a large extent independent of the switching frequency in the BJT case. The passivation of the emitter junction modeled here by surface recombination velocity has a significant impact on conduction losses and gate driver losses in the investigated BJT devices.

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Akiyama, Satoru, Kaoru Katoh, Haruka Shimizu, Ayumu Hatanaka, Takashi Ogawa, Natsuki Yokoyama, and Katsumi Ishikawa. "Gate-Drive Voltage Design for 600-V Vertical-Trench Normally-Off SiC JFETs toward 94% Efficiency Server Power Supply." Materials Science Forum 778-780 (February 2014): 875–78. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.875.

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A gate-drive voltage for a normally-off silicon-carbide vertical-trench junction-gate field-effect transistor (JFET) was designed for a server power supply with 94% efficiency. Since the on-state resistance of the JFET is strongly depends on the gate voltage and a large gate-leakage current between the gate electrode and source flows by applying an excessively high-gate voltage, we therefore must set an adequate turn-on gate-drive voltage to suppress the increase in power loss. The optimum gate-drive voltage design was estimated to be 2.1 V, resulting in a high efficiency of 94% even with a gate-drive voltage variation of ±0.3 V.

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Kelley, Robin L., T. Brignac, Michael S. Mazzola, and Jeff B. Casady. "Inherently Safe Resonant Reset Forward Converter Using a Bias-Enhanced SiC JFET." Materials Science Forum 527-529 (October 2006): 1211–14. http://dx.doi.org/10.4028/www.scientific.net/msf.527-529.1211.

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The power junction field effect transistor (JFET) is the second most mature SiC device, after the SiC Schottky diode, and is commonly associated with normally on functionality; but this feature is often viewed problematically for off-line dc-to-dc converter applications. Two inherently safe, single-switch dc-dc converter designs have been developed that put into practice pure SiC JFET devices (i.e., without cascoded devices) that possess enhancement-mode functionality and bias-enhanced blocking. These ‘Quasi-Off’ devices are designed to block half of the rated blocking voltage at zero gate bias and achieve full rated blocking voltage with a modest negative bias, typically between 0 and -5 V. Inherent safety is provided by utilizing the enhancement mode functionality of these devices as well as appropriate gate driver design. Bias enhanced blocking matches the dynamic stress encountered by modern high-frequency power supply topologies to the ratings of the device while recognizing that the larger dynamic stress is typically encountered only when the power supply (and especially the gate driver) is functioning properly.

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31

Vazquez, Aitor, Alberto Rodriguez, Marcos Fernandez, Marta M. Hernando, Enrique Maset, and Javier Sebastian. "On the Use of Front-End Cascode Rectifiers Based on Normally On SiC JFET and Si MOSFET." IEEE Transactions on Power Electronics 29, no. 5 (May 2014): 2418–27. http://dx.doi.org/10.1109/tpel.2013.2273274.

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32

Sugiyama, Naohiro, Yuuichi Takeuchi, Mitsuhiro Kataoka, Adolf Schöner, and Rajesh Kumar Malhan. "Growth Mechanism and 2D Aluminum Dopant Distribution of Embedded Trench 4H-SiC Region." Materials Science Forum 600-603 (September 2008): 171–74. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.171.

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The migration enhanced embedded epitaxy (ME3) mechanism and 2D dopant distribution of the embedded trench region is investigated with the aim to realize the all-epitaxial, normally-off junction field effect transistor (JFET). We found that the embedded growth consists of two main components. First one is the direct supply without gas scattering and the other one is the surface migration supply via the trench opening edge, which dominate the ME3 process. An inhomogeneous 2D distribution of Aluminum (Al) concentration was revealed for the first time in the 4H-SiC embedded trench regions by the combined analysis of secondary ion mass spectrometry (SIMS) and scanning spreading resistance microscopy (SSRM) results. The maximum variation of Al concentration in the trench is estimated to be about 4-times, which suggests that the Al concentration is highest for the (0001) plane and lowest for the trench corner (1-10x) plane. Al concentration in the (1-100) plane, which determines the JFET p-gate doping level is 1.5-times lower than (0001) plane for trench region fabricated on Si-face wafers.

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33

Veliadis, Victor, Harold Hearne, Eric J. Stewart, R. Howell, Aivars J. Lelis, and Charles Scozzie. "Feasibility of Efficient Power Switching Using Short-Channel 1200-V Normally-Off SiC VJFETs; Experimental Analysis and Simulations." Materials Science Forum 645-648 (April 2010): 929–32. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.929.

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A recessed implanted-gate short-channel 1290-V normally-OFF 4H-SiC vertical-channel JFET (VJFET), fabricated in seven photolithographic-levels, with a single masked ion-implantation and no epitaxial regrowth, is evaluated for efficient power conditioning. Under unipolar high-current-gain operation, which is required for efficient power switching, the 1200-V N-OFF (enhancement mode) VJFET exhibits prohibitively high on-state resistance. Comparison with 1200-V normally-ON VJFETs, fabricated on the same wafer, confirms experimentally that the strong gate-depletion-region overlap required for 1200-V normally-OFF blocking is the principal contributor to the prohibitively high specific on-state resistance observed under high current-gain VJFET operation. Recessed-implanted-gate VJFET channel-region optimization simulations (assuming a single commercial implantation and no epitaxial-regrowth) revealed that although aggressively increasing channel doping lowers resistance, the corresponding reduction in source mesa-width can prohibitively limit manufacturability.

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34

Suto, Takeru, Naoki Watanabe, Yuan Bu, Hiroshi Miki, Naoki Tega, Yuki Mori, Digh Hisamoto, and Akio Shima. "1.2-kV SiC Trench-Etched Double-Diffused MOS (TED-MOS)." Materials Science Forum 963 (July 2019): 617–20. http://dx.doi.org/10.4028/www.scientific.net/msf.963.617.

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A novel structure, trench-eched double-diffused MOS (TED-MOS), were proposed. In this study, we demonstrate compatibility of reliability and small loss for applications to electric vehicle. To suppress the dielectric breakdown of gate insulator, a field relaxation layer (FRL) are formed above JFET region. Device simulation shows an effective decrease of electric field on gate dioxide, and furthure improvement of switching-and conduction-loss were expected. The fabricated TED-MOS chip doesn’t show gate leakage current even over 1600 V. We confirmed stable normally-off characteristic of the chip at 175 °C, and its Ron was 66 mΩ under Vg = 20 V and 175 °C condition. As an uniqueness to FRL TED-MOS, capacitance shows a steep decline with several step, which may attributed to depletion between FRL and p-Body and should contributed to the reduction of switching loss.

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35

DiMarino, Christina, Zheng Chen, Dushan Boroyevich, Rolando Burgos, and Paolo Mattavelli. "High-Temperature Characterization and Comparison of 1.2 kV SiC Power Semiconductor Devices." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, HITEN (January 1, 2013): 000082–87. http://dx.doi.org/10.4071/hiten-mp15.

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Focused on high-temperature (200 °C) operation, this paper seeks to provide insight into state-of-the-art 1.2 kV Silicon Carbide (SiC) power semiconductor devices; namely the MOSFET, BJT, SJT, and normally-off JFET. This is accomplished by characterizing and comparing the latest generation of these wide bandgap devices from various manufacturers (Cree, GE, Rohm, Fairchild, GeneSiC, and SemiSouth). To carry out this study, the static and dynamic characterization of each device is performed under increasing temperatures (25–200 °C). Accordingly, this paper describes the experimental setup used and the different measurements conducted, which include: threshold voltage, current gain, specific on-resistance, and the turn-on and turn-off switching energies of the devices. The driving method used for each device is also detailed. Key trends and observations are reported in an unbiased manner throughout the paper and summarized in the conclusion.

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36

DiMarino, Christina, Zheng Chen, Dushan Boroyevich, Rolando Burgos, and Paolo Mattavelli. "High-Temperature Characterization and Comparison of 1.2 kV SiC Power Semiconductor Devices." Journal of Microelectronics and Electronic Packaging 10, no. 4 (October 1, 2013): 138–43. http://dx.doi.org/10.4071/imaps.393.

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Focused on high-temperature (200°C) operation, this paper seeks to provide insight into state-of-the-art 1.2 kV silicon carbide (SiC) power semiconductor devices; namely the MOSFET, BJT, SJT, and normally-off JFET. This is accomplished by characterizing and comparing the latest generation of these wide bandgap devices from various manufacturers (Cree, GE, ROHM, Fairchild, GeneSiC, and SemiSouth). To carry out this study, the static and dynamic characterization of each device is performed under increasing temperatures (25–200°C). Accordingly, this paper describes the experimental setup used and the different measurements conducted, which include: threshold voltage, current gain, specific on-resistance, and the turn-on and turn-off switching energies of the devices. The driving method used for each device is also detailed. Key trends and observations are reported in an unbiased manner throughout the paper and summarized in the conclusion.

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37

Lim, Jang Kwon, Mietek Bakowski, and Hans Peter Nee. "Design and Gate Drive Considerations for Epitaxial 1.2 kV Buried Grid N-on and N-off JFETs for Operation at 250°C." Materials Science Forum 645-648 (April 2010): 961–64. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.961.

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The 1.2 kV 4H-SiC buried-grid vertical JFET structures with Normally-on (N-on) and Normally-off (N-off) design were investigated by simulations. The conduction and switching properties were determined in the temperature range from -50°C to 250°C. In this paper, the characteristics of the N-on designs with threshold voltage (Vth) of -50 V and -10 V are compared with the N-off design (Vth=0). The presented data are for devices with the same channel length at 250°C. The results show that the on-resistance (Ron) decreases with increasing channel doping concentration and decreasing channel width. The presented turn-on, Eon, and turn-off, Eoff, energies per pulse are calculated under the switching conditions 100 A/cm2 and 600 V with a gate resistance of Rg=1 . For the two N-on designs the total switching losses, Esw=Eon+Eoff, differ less than 30% with Wch 0.7 m. With Wch=0.5 m the switching losses of N-off design are almost one order of magnitude higher than those of the N-on design with Vth = -50 V.

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38

Schöner, Adolf, Naohiro Sugiyama, Yuuichi Takeuchi, and Rajesh Kumar Malhan. "In Situ Nitrogen and Aluminum Doping in Migration Enhanced Embedded Epitaxial Growth of 4H-SiC." Materials Science Forum 600-603 (September 2008): 175–78. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.175.

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The in-situ doping of aluminum and nitrogen in migration enhanced embedded epitaxy (ME3) is investigated with the aim to apply it to the realization and fabrication of all-epitaxial, normally-off 4H-SiC JFET devices. This ME3 process consists of the epitaxial growth of an n-doped channel and a highly p-doped top gate in narrow trenches. We found that the nitrogen doping in the n-channel (a-face) is a factor 1.5 higher than layers grown with the same process on Si-face wafers. Due to the low C/Si ratio and the low silane flow rate used in the ME3 process, the growth of the p-doped top gate needs high flow rates of the aluminum precursor trimethylaluminum for several hours, which contaminates the CVD reactor and causes aluminum memory effects. These aluminum memory effects can be reduced by an extra high temperature bake-out run.

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39

Veliadis, V., T. McNutt, M. Snook, H. Hearne, P. Potyraj, and C. Scozzie. "A 1680-V (at 1 $\hbox{mA/cm}^{2}$) 54-A (at 780 $\hbox{W/cm}^{2}$) Normally ON 4H-SiC JFET With 0.143- $\hbox{cm}^{2}$ Active Area." IEEE Electron Device Letters 29, no. 10 (October 2008): 1132–34. http://dx.doi.org/10.1109/led.2008.2002907.

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40

Dubois, Fabien, Dominique Bergogne, Cyril Buttay, Hervé Morel, and Régis Meuret. "Normally-On SiC JFETs: Active Protections." EPE Journal 22, no. 3 (September 2012): 6–13. http://dx.doi.org/10.1080/09398368.2012.11463826.

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41

Veliadis, V., M. Snook, T. McNutt, H. Hearne, P. Potyraj, A. Lelis, and C. Scozzie. "A 2055-V (at 0.7 $\hbox{mA/cm}^{2}$) 24-A (at 706 $\hbox{W/cm}^{2}$) Normally On 4H-SiC JFET With 6.8- $\hbox{mm}^{2}$ Active Area and Blocking-Voltage Capability Reaching the Material Limit." IEEE Electron Device Letters 29, no. 12 (December 2008): 1325–27. http://dx.doi.org/10.1109/led.2008.2006766.

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42

Abbate, C., G. Busatto, and F. Iannuzzo. "Unclamped repetitive stress on 1200V normally-off SiC JFETs." Microelectronics Reliability 52, no. 9-10 (September 2012): 2420–25. http://dx.doi.org/10.1016/j.microrel.2012.06.097.

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43

Biela, Jürgen, Mario Schweizer, Stefan Waffler, Benjamin Wrzecionko, and Johann Walter Kolar. "SiC vs. Si - Evaluation of Potentials for Performance Improvement of Power Electronics Converter Systems by SiC Power Semiconductors." Materials Science Forum 645-648 (April 2010): 1101–6. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.1101.

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Switching devices based on wide band gap materials as SiC oer a signicant perfor- mance improvement on the switch level compared to Si devices. A well known example are SiC diodes employed e.g. in PFC converters. In this paper, the impact on the system level perfor- mance, i.e. eciency/power density, of a PFC and of a DC-DC converter resulting with the new SiC devices is evaluated based on analytical optimisation procedures and prototype systems. There, normally-on JFETs by SiCED and normally-off JFETs by SemiSouth are considered.

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44

Rabkowski, Jacek, Mariusz Zdanowski, Mietek Nowak, and Roman Barlik. "Fault Protection System for Current Source Inverter with Normally on SiC JFETs." Materials Science Forum 679-680 (March 2011): 750–53. http://dx.doi.org/10.4028/www.scientific.net/msf.679-680.750.

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This paper describes a simple fault protection system for Current Source Inverter built with normally-on SiC JFETs. Because all transistors are in on-state after loss of the gate drive(s) supply, list of possible fault modes is extended in reference to standard inverters. That is also why an additional normally off switch is introduced in the DC link. Operation principles of the protection system which follows the drain-source voltages of JFETs and the current of the DC link are presented. The 2kVA/100kHz model of the inverter equipped with the proposed system is validated via various laboratory tests including short-circuits and the auxiliary supply turn off.

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45

Schrader, R., K. Speer, J. Casady, V. Bondarenko, and D. Sheridan. "A performance comparison of normally-off and normally-on SiC JFETs toward use in high-temperature power modules." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, HITEN (January 1, 2011): 000098–103. http://dx.doi.org/10.4071/hiten-paper2-rschrader.

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The high-temperature static and dynamic characteristics of the new 1200 V, 45 mΩ, 9 mm2 depletion-mode SiC vertical trench junction field-effect transistor (vtJFET) are compared with those of a 1200 V, 50 mΩ, 9 mm2 enhancement-mode SiC vtJFET. It is shown that both devices are fully capable of high-temperature operation and that each type has its own unique advantages. For applications operating in extreme high-temperature environments, the larger saturation current (~2.5x) and lower on-state resistance (~150 mΩ at 250 °C) of the depletion-mode SiC vtJFET provide very attractive performance at temperatures beyond silicon's fundamental limitations. In addition, operating the normally-on vtJFET at VGS less than 2 V reduces the gate drive's current requirements to a negligible level, which is an important design factor for high-temperature power modules that use multiple die in parallel.

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46

Kranzer, Dirk, Bruno Burger, Nicolas Navarro, and Olivier Stalter. "Applications of SiC-Transistors in Photovoltaic Inverters." Materials Science Forum 615-617 (March 2009): 895–98. http://dx.doi.org/10.4028/www.scientific.net/msf.615-617.895.

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Currently there are several silicon carbide (SiC) field effect or bipolar transistor types in development with normally-on and normally-off characteristics. It is not yet clear, which transistor type will prevail in the market and which will remain a niche product. This is not only determined by their electrical characteristics, but also by their acceptance by engineers. In this paper the implementation and the performance of 1200 V / 20 A / 100 m SiC-DMOSFETS and 1200 V / 12 A / 125 m normally-off SiC-JFETs in photovoltaic inverters (PV-inverters) is shown.

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47

Kranzer, Dirk, Florian Reiners, Christian Wilhelm, and Bruno Burger. "System Improvements of Photovoltaic Inverters with SiC-Transistors." Materials Science Forum 645-648 (April 2010): 1171–76. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.1171.

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In this paper the system improvements of PV-inverters with SiC-transistors are demonstrated. The basic characteristics of engineering prototypes of normally-off SiC-JFETs and SiC-MOSFETs were measured and their differences in the application are considered. To demonstrate the improvement in PV-inverter performance, a 5 kW single-phase and a three-phase full bridge inverter with normally-off SiC-JFETs were developed at Fraunhofer ISE. Different switching frequencies up to 144 kHz were applied and the impact on production costs and inverter performance was rated under the aspects of an industrial product development. This means, the influences on the efficiency and power density. In this work, a world record in PV-inverter efficiency of 99 % was achieved in a single-phase inverter and for the three-pase inverter, the power density was tripled with respect to commercially available state of the art PV-inverters.

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48

Veliadis, Victor, Ty McNutt, Megan Snook, Harold Hearne, Paul Potyraj, Jeremy Junghans, and Charles Scozzie. "Large Area Silicon Carbide Vertical JFETs for 1200 V Cascode Switch Operation." International Journal of Power Management Electronics 2008 (June 9, 2008): 1–8. http://dx.doi.org/10.1155/2008/523721.

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SiC VJFETs are excellent candidates for reliable high-power/temperature switching as they only use pn junctions in the active device area where the high-electric fields occur. VJFETs do not suffer from forward voltage degradation, exhibit excellent short-circuit performance, and operate at 300°C. 0.19 cm2 1200 V normally-on and 0.15 cm2 low-voltage normally-off VJFETs were fabricated. The 1200-V VJFET outputs 53 A with a forward drain voltage drop of 2 V and a specific onstate resistance of 5.4 mΩ cm2. The low-voltage VJFET outputs 28 A with a forward drain voltage drop of 3.3 V and a specific onstate resistance of 15 mΩ cm2. The 1200-V SiC VJFET was connected in the cascode configuration with two Si MOSFETs and with a low-voltage SiC VJFET to form normally-off power switches. At a forward drain voltage drop of 2.2 V, the SiC/MOSFETs cascode switch outputs 33 A. The all-SiC cascode switch outputs 24 A at a voltage drop of 4.7 V.

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Veliadis, Victor, Eric J. Stewart, Harold Hearne, Ty McNutt, W. Chang, Megan Snook, Aivars J. Lelis, and Charles Scozzie. "Design and Yield of 9 kV Unipolar Normally-ON Vertical-Channel SiC JFETs." Materials Science Forum 679-680 (March 2011): 617–20. http://dx.doi.org/10.4028/www.scientific.net/msf.679-680.617.

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Normally-ON 9.1 kV (at 0.1 mA/cm2), 1.52 x 10-3 cm2 active-area vertical-channel SiC JFETs (VJFETs), were fabricated at a 52% yield with no epitaxial regrowth and a three-step junction-termination-extension edge termination, which is connected to the gate bus through an ion-implanted sloped sidewall. The VJFETs exhibit low gate-to-source leakage currents of less than 1 nA up to VGS = -60 V, and sharp onsets of breakdown occurring at VGS ~ -80 V. The gate-to-source and gate-to-drain diodes turn on at 2.75 V, with the latter diode exhibiting higher resistance due to the thick epitaxial drift layer. To realize unipolar operation with low on-state resistance, the VJFET is designed very normally-ON which minimizes the channel resistance contribution. Consequently, threshold voltages are in the -3 V to -4.5 V range and transconductance is relatively low at < 0.36 mS. At a gate bias of 0 V, the VJFETs output a drain current of 73 mA with a forward drain voltage drop of 5 V (240 W/cm2), a specific on-state resistance of 104 mΩ-cm2, and a current gain of ID/IG = 6.4 x 109. Thus, these VJFETs are capable of efficient power switching, i.e., high current-gain voltage-controlled operation at a low unipolar resistance.

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Guédon, F., S. K. Singh, R. A. McMahon, and F. Udrea. "Gate driver for SiC JFETs with protection against normally-on behaviour induced fault." Electronics Letters 47, no. 6 (2011): 375. http://dx.doi.org/10.1049/el.2011.0241.

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Journal articles on the topic 'JFET SiC normally-on'

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