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Dissertations / Theses on the topic 'Jitter'

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Published: 4 June 2021

Last updated: 25 July 2025

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1

Wang, Xin. "Automatically Measuring Neuromuscular Jitter." Thesis, University of Waterloo, 2005. http://hdl.handle.net/10012/956.

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The analysis of electromyographic (EMG) signals detected during muscle contraction provides important information to aid in the diagnosis and characterization of neuromuscular disorders. One important analysis measures neuromuscular jitter, which is the variability of the time intervals between two muscle fibre potentials (MFPs) belonging to the same motor unit over a set of discharges. Conventionally, neuromuscular jitter is measured using single fibre (SF) EMG techniques, which can identify individual MFPs by using a SF needle electrode. However, SF electrodes are expensive, very sen

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2

Price, Michael Ph D. (Michael R. ). Massachusetts Institute of Technology. "Asynchronous data-dependent jitter compensation." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/52771.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Includes bibliographical references (p. 95-96).<br>Data-dependent jitter (DDJ) caused by lossy channels is a limiting factor in the bit rates that can be achieved reliably over serial links. This thesis explains the causes of DDJ and existing equalization techniques, then develops an asynchronous (clock-agnostic) architecture fo

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3

Martwick, Andrew Wayne. "Clock Jitter in Communication Systems." PDXScholar, 2018. https://pdxscholar.library.pdx.edu/open_access_etds/4375.

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For reliable digital communication between devices, the sources that contribute to data sampling errors must be properly modeled and understood. Clock jitter is one such error source occurring during data transfer between integrated circuits. Clock jitter is a noise source in a communication link similar to electrical noise, but is a time domain noise variable affecting many different parts of the sampling process. Presented in this dissertation, the clock jitter effect on sampling is modeled for communication systems with the degree of accuracy needed for modern high speed data communication.

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4

Oulmane, Mourad. "Integrated solutions for timing jitter measurement." Thesis, McGill University, 2011. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=104524.

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In this thesis we present two integrated solutions suitable for measuring the timing jitter of digital signals in SoCs and data acquisition systems (mainly sampling ADCs). The presented methods are also suitable for time measurement in a variety of timing-based metrological applications. The first method is based on the amplification of the time difference to be measured using a time amplifier (TAMP). The result of the amplification is subsequently digitized using a low resolution time-to-digital converter (TDC). The amplifier is based on the principle of virtual charge sharing that allows for

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5

Helal, Belal M. 1971. "Techniques for low jitter clock multiplication." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/44417.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.<br>Includes bibliographical references (p. 115-121).<br>Phase realigning clock multipliers, such as Multiplying Delay-Locked Loops (MDLL), offer significantly reduced random jitter compared to typical Phase-Locked Loops (PLL). This is achieved by introducing the reference signal directly into their voltage controlled oscillators (VCO) to realign the phase to the clean reference. However, the typical cost of this benefit is a significant increase in deterministic jitter due to pat

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6

Lee, Li-Min. "Low-jitter multi-phase clock distribution." Diss., Restricted to subscribing institutions, 2008. http://proquest.umi.com/pqdweb?did=1610045471&sid=14&Fmt=2&clientId=1564&RQT=309&VName=PQD.

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7

Onunkwo, Uzoma Anaso. "Timing Jitter in Ultra-Wideband (UWB) Systems." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10465.

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Timing offsets result from the use of real clocks that are non-ideal in sampling intervals. These offsets also known as timing jitter were shown to degrade the performance of the two forms of UWB systems impulse radio and orthogonal frequency division multiplexing (OFDM)-based UWB. It was shown that for impulse radio, timing jitter distorts the correlation property of the transmitted signal and the resulting performance loss is proportional to the root-mean-square (RMS) value of the timing jitter. For the OFDM-based UWB, timing jitter introduced inter-channel interference (ICI) and the per

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8

Zhang, Peng Frank. "Jitter buffer management algorithms for voice communication." Thesis, University of Ottawa (Canada), 2002. http://hdl.handle.net/10393/6345.

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This thesis studies some jitter management algorithms for real-time applications. These algorithms are executed at a destination node, and assume no knowledge of the source characteristic or the impact of the network path characteristic. The work mainly focuses on prediction algorithms that make use of the information of the packets received in the past, and adjust buffer parameters in order to maintain certain level of quality of service (QoS). Two algorithms are proposed, first, to apply the least mean square method to predict the future packet interarrival time so that the buffer parameters

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9

Lazar, Mihai. "Empirical modeling of end-to-end jitter." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0019/MQ58472.pdf.

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10

Moradi, Hamid. "State-of-the-art within jitter measurement." Thesis, Högskolan i Gävle, Akademin för teknik och miljö, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-16148.

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The aim of this thesis is to study different types of jitter measurement methods and to make comparison between them. With this purpose, a literature study was performed by searching in different databases. The explored databases include: a) Recent research articles in jitter measurements appearing in IEEE xplorer with published date posterior to 1998, b) Application notes and white papers from leading companies as Agilent and Anritsu. In this study it is shown that the research method presented in [20] has more accuracy compared to ITU standard method due to that an specific signal from PDH

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11

Sickler, Jason William 1978. "Timing jitter studies in modelocked fiber lasers." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/87855.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.<br>Also issued in pages.<br>Includes bibliographical references (p. 107-109).<br>by Jason William Sickler.<br>S.M.

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12

Lee, Leonard T. "Jitter Sampling of Deterministic Signals and Noise." International Foundation for Telemetering, 1989. http://hdl.handle.net/10150/614730.

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International Telemetering Conference Proceedings / October 30-November 02, 1989 / Town & Country Hotel & Convention Center, San Diego, California<br>In the implementation of any digital signal processing system, noise can be introduced due to hardware limitations. Some examples of noise are aliasing and amplitude quantization noise. Another noise source that is often ignored is the result of jitter, or random fluctuations of the sample period. Since clock jitter is present in almost all oscillators, a digital signal processing system rarely has perfectly timed samples. In this paper, an appro

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13

Fitzpatrick, Justin Jennings. "Analysis and Design of Low-Jitter Oscillators." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd369.pdf.

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14

Watkins, R. Joseph. "The adaptive control of optical beam jitter." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2004. http://library.nps.navy.mil/uhtbin/hyperion/04Dec%5FWatkins%5FPhD.pdf.

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Thesis (Ph. D. in Mechanical Engineering)--Naval Postgraduate School, December 2004.<br>Thesis advisor(s): Brij N. Agrawal, Young S. Shin. Includes bibliographical references (p. 163-165). Also available online.

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15

Walker, Jacqueline. "Frame synchronization techniques and jitter generation : analysis, modelling and enhancement." Thesis, Curtin University, 1997. http://hdl.handle.net/20.500.11937/1715.

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Synchronization means the aligning of the significant instants of one signal to the significant instants of another. In digital systems, where timing transfer between systems is required, synchronization is an important function. In this thesis new results on the performance and design of synchronization processes are presented. An inescapable consequence of the synchronization of external autonomous inputs in digital systems is the possibility of failure of digital devices used to capture the external signal. The anomalous behaviour of these devices is referred to as metastability. The most c

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16

Brockmann-Bauser, Meike. "Improving jitter and shimmer measurements in normal voices." Thesis, University of Newcastle Upon Tyne, 2012. http://hdl.handle.net/10443/1472.

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Instrumental acoustic voice analysis is a widely used clinical assessment technique to assist differential diagnosis, documentation and evaluation of treatment for voice disorders. However recent reports criticise an unsatisfactory reliability and validity of acoustic assessments. The present work examines confounding factors associated with the usual clinical measurement procedure and how their influence might be reduced. Further, it was investigated what jitter and shimmer indicate, and how this could be applied in voice clinics. In a routine clinical voice assessment the individuals` speaki

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17

Neilson, Hilding, and Richard Ignace. "Convection, Granulation, and Period Jitter in Classical Cepheids." Digital Commons @ East Tennessee State University, 2014. https://dc.etsu.edu/etsu-works/6243.

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Analyses of recent observations of the sole classical Cepheid in the Kepler field, V1154 Cygni, found random changes of about 30 min in the pulsation period. These period changes challenge standard theories of pulsation and evolution because the period change is non-secular, and explaining this period jitter is necessary for understanding stellar evolution and the role of Cepheids as precise standard candles. We suggest that convection and convective hot spots can explain the observed period jitter. Convective hot spots alter the timing of flux maximum and minimum in the Cepheid light curve, h

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18

Mittal, Rishabh. "A sampling jitter tolerant continuous-time pipeline ADC." Thesis, Massachusetts Institute of Technology, 2020. https://hdl.handle.net/1721.1/128343.

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Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, February, 2020<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 43-45).<br>A sampling jitter tolerant continuous-time (CT) pipeline ADC has been presented in this thesis. In conventional discrete-time (DT) pipeline ADCs, the input is sampled upfront. The improvements in the bandwidth and sampling speed due to CMOS scaling have brought the deleterious effects of sampling clock jitter to the forefront. Any jitter in the sampling clock edge adds a r

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19

Mesgarzadeh, Behzad. "Low-Power Low-Jitter Clock Generation and Distribution." Doctoral thesis, Linköpings universitet, Elektroniska komponenter, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-14896.

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Today’s microprocessors with millions of transistors perform high-complexitycomputing at multi-gigahertz clock frequencies. Clock generation and clockdistribution are crucial tasks which determine the overall performance of amicroprocessor. The ever-increasing power density and speed call for newmethodologies in clocking circuitry, as the conventional techniques exhibit manydrawbacks in the advanced VLSI chips. A significant percentage of the total dynamicpower consumption in a microprocessor is dissipated in the clock distributionnetwork. Also since the chip dimensions increase, clock jitter

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20

Renneflott, Anette Cathrine. "Spatial and Temporal Aspects of the Jitter Aftereffect." Thesis, Griffith University, 2014. http://hdl.handle.net/10072/366835.

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The spatial and temporal parameters determining the duration of the jitter aftereffect (JAE) were examined. Experiment one showed the JAE is a luminance-based effect. Experiment two showed that element sizes 0.084 square (≈7 cpd) and temporal frequencies above 18 Hz were optimal. Experiment three showed that the JAE is dependent on the rate of change during adaptation, not the number of changes. Experiment four compared directional noise: linear, circular, and radial to adirectional dynamic random noise (DRN). Linear noise was better than circular or radial, but random noise was best. Experim

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21

Tomlin, Toby-Daniel. "Analysis and modelling of jitter and phase noise in electronic systems : phase noise in RF amplifiers and jitter in timing recovery circuits." University of Western Australia. School of Electrical, Electronic and Computer Engineering, 2004. http://theses.library.uwa.edu.au/adt-WU2004.0021.

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Timing jitter and phase noise are important design considerations in most electronic systems, particularly communication systems. The desire for faster transmission speeds and higher levels of integration, combined with lower signal levels and denser circuit boards has placed greater emphasis on managing problems related to phase noise, timing jitter, and timing distribution. This thesis reports original work on phase noise modelling in electronic systems. A new model is proposed which predicts the up-conversion of baseband noise to the carrier frequency in RF amplifiers. The new model is vali

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22

Channe, Gowda Anushree. "Latency and Jitter Control in 5G Ethernet Fronthaul Network." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2019. http://amslaurea.unibo.it/17651/.

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With 5G technology, networks are expected to offer high speed with ultra-low latency among different users. Maintaining the current network architecture will lead to an unsustainable transport delay and jitters increase. Limiting the transport delay and the jitters have become a necessity for mobile network operators. The main requirement in 5G networks is the demand of limiting the transport delay. This, thesis proposes a novel mechanism to minimize packet delay and delay variation in 5G Ethernet fronthaul network. The goal is to achieve bounded delay aggregation of traffic ,suitable for app

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23

Chan, Antonio. "Circuits for time and frequency domain characterization of jitter." Thesis, McGill University, 2002. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=29532.

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Jitter characterization has become significantly more important for systems running at multi-gigahertz data rates. Time and frequency domain characterization of jitter is thus a crucial element for system specification testing. Time domain jitter measurement on a data signal with sub-gate timing resolution can be achieved using two delay chains feeding into the clock and data lines of a series of D-latches known as a Vernier Delay Line (VDL). An important drawback to the VDL structure is that its measurement accuracy depends on the matching of the various delay elements. Although careful layou

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Fudoli, Tania Regina Tronco. "Redução de "jitter" de justificação na hierarquia digital sincrona." [s.n.], 1992. http://repositorio.unicamp.br/jspui/handle/REPOSIP/261589.

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Orientador : Rege Romeu Scarabucci<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica<br>Made available in DSpace on 2018-07-18T08:54:07Z (GMT). No. of bitstreams: 1 Fudoli_TaniaReginaTronco_M.pdf: 7393732 bytes, checksum: 998040acdd2f6b617d9e2cc0903c00c8 (MD5) Previous issue date: 1992<br>Resumo: A evolução das redes de comunicações digitais fez surgir novos tipos de multiplexadores que são otimizados para o transporte de sinais de dados s{ncronos. A padronização destes novos tipos de multiplexadores vem sendo feita pelo CCITT ("Intemational Tele

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25

Hutsel, Brian T. Kovaleski Scott D. "Runtime and jitter of a laser triggered gas switch." Diss., Columbia, Mo. : University of Missouri--Columbia, 2008. http://hdl.handle.net/10355/5783.

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The entire thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file; a non-technical public abstract appears in the public.pdf file. Title from PDF of title page (University of Missouri--Columbia, viewed on September 24, 2009). Thesis advisor: Dr. Scott Kovaleski. Includes bibliographical references.

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26

Chastang, Cyril. "Techniques et méthodologies de validation par la simulation des liens multi-gigahertz des cartes électroniques haute densité." Phd thesis, École normale supérieure de Cachan - ENS Cachan, 2013. http://tel.archives-ouvertes.fr/tel-00846476.

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La tendance dans la conception de cartes électroniques imprimées est de remplacer les traditionnels bus parallèles par des liens série rapides dont le débit peut atteindre plusieurs dizaines de Gigabit par seconde (Gbps). Cette thèse proposée par THALES Communications & Security en collaboration avec le laboratoire SATIE de l'ENS de Cachan a pour objectif de définir une approche adaptée au traitement des problèmes de liens multi-gigahertz, de manière à garantir le fonctionnement d'une carte numérique complexe (multicouches, haute densité d'intégration, ...) sans qu'une phase de prototypage ne

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27

Walker, Jacqueline. "Frame synchronization techniques and jitter generation : analysis, modelling and enhancement." Curtin University of Technology, Co-operative Research Centre for Broadband Telecommunications and Networking Telecommunications, 1997. http://espace.library.curtin.edu.au:80/R/?func=dbin-jump-full&object_id=10841.

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Synchronization means the aligning of the significant instants of one signal to the significant instants of another. In digital systems, where timing transfer between systems is required, synchronization is an important function. In this thesis new results on the performance and design of synchronization processes are presented.An inescapable consequence of the synchronization of external autonomous inputs in digital systems is the possibility of failure of digital devices used to capture the external signal. The anomalous behaviour of these devices is referred to as metastability. The most co

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28

Sholander, Peter Edward. "Characterization and minimization of jitter and wander in SDH networks." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/13461.

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29

Zare-Hoseini, Hashem. "Continuous-Time Delta-Sigma Modulators with Immunity to Clock-Jitter." Thesis, University of Westminster, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.500545.

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30

詹益豪. "Jitter Analysis and Implementation of Periodic Jitter Identification." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/94730014210495678058.

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碩士<br>中華大學<br>電機工程學系碩士班<br>91<br>In this thesis, we present a time-domain jitter separation method to estimate the random and deterministic jitter components. And, we structure a periodic jitter model to generate the periodic jitter clock. Then, using accumulated time analysis to determine the presence of periodic jitter and analyze the frequency of periodic jitter.

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31

Seifi, Seyed Mohammad Ehsan. "Sampling Time Jitter." Thesis, 2013. http://hdl.handle.net/10012/7237.

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Electrical systems which use voltage transitions to represent timing information suffer from a degrading phenomenon called timing jitter. Sampling time jitter is the deviation of sampling clock from its ideal position. As transmission rates raise above couple of GHz, deviations become significant comparing to signalling interval, jitter becomes a fundamental performance bottleneck. Especially in band-limited communication systems that imperfect sampling times result in Inter-Symbol Interference (ISI) jitter is a very limiting factor to decode correct transmitted data. In this case, jitter timi

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Buckwalter, James Franklin. "Deterministic Jitter in Broadband Communication." Thesis, 2006. https://thesis.library.caltech.edu/407/1/Buckwalter_Thesis01_06.pdf.

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<p>The past decade has witnessed a drastic change in the design of high-speed serial links. While Silicon fabrication technology has produced smaller, faster transistors, transmission line interconnects between chips and through backplanes have not substantially improved and have a practical bandwidth of around 3GHz. As serial link speeds increase, new techniques must be introduced to overcome the bandwidth limitation and maintain digital signal integrity. This thesis studies timing issues pertaining to bandwidth-limited interconnects. Jitter is defined as the timing uncertainty at a threshold

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Wang, Jian-Ren, and 王健任. "Jitter-based SCTP: Improving SCTP performance by jitter-based congestion control over wired-wireless networks." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/w488gs.

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碩士<br>國立中央大學<br>資訊工程研究所<br>94<br>With the evolution of communication networks, wireless networks gradually become the most adaptive communication networks in next generation internet. Desktops and mobile devices may be equipped with multiple wired and/or wireless network interfaces. Stream Control Transmission Protocol (SCTP) has been proposed for reliable data transport and its multihoming feature makes use of network interfaces effectively to improve performance and reliability. However, like TCP, SCTP suffers unnecessary performance degradation over wired-wireless heterogeneous networks. Th

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Chi-Chang, Liu, and 劉吉昌. "A New Methodology to Reduce Jitter." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/57374350754595925209.

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碩士<br>逢甲大學<br>資訊電機工程碩士在職專班<br>94<br>Signal jitter is an important factor that has no way to ignore many circuit. Solving signal jitter becomes the essential work when facing the mechanism requirement of precision and speed from users. Researches in this field are devoted to the measurement of clock jitter and its influence on circuits, so far. Fewer of them are focused on the analysis and the corresponding effect of data jitter, which can be the unstablization factor of a mechanism, on circuits; even the researches of concerning both of these two kinds of jitters. This research focuses on proc

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35

"Jitter reduction techniques for digital audio." 1997. http://library.cuhk.edu.hk/record=b5889216.

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by Tsang Yick Man, Steven.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.<br>Includes bibliographical references (leaves 94-99).<br>ABSTRACT --- p.i<br>ACKNOWLEDGMENT --- p.ii<br>LIST OF GLOSSARY --- p.iii<br>Chapter 1 --- INTRODUCTION --- p.1<br>Chapter 1.1 --- What is the jitter ？ --- p.3<br>Chapter 2 --- WHY DOES JITTER OCCUR IN DIGITAL AUDIO ？ --- p.4<br>Chapter 2.1 --- Poorly-designed Phase Locked Loop ( PLL ) --- p.4<br>Chapter 2.1.1 --- Digital data problem --- p.7<br>Chapter 2.2 --- Sampling jitter or clock jitter ( Δti) --- p.9<br>Chapter 2.3 --- Waveform distort

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Chen, Jun-Jia, and 陳俊嘉. "PLL with On-Chip Jitter Measurement." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/71915360853316686796.

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Cheng, Nai-Chen, and 鄭乃禎. "On-Chip Low Jitter Clock Generation." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/73032553756572761821.

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碩士<br>國立成功大學<br>電機工程學系專班<br>93<br>Phase locked-loops (PLLs) are widely used to generate well-timed on-chip clocks in high-performance digital systems. Any timing jitter or phase noise significantly degrades the performance of these systems, especially as operating frequency increases. Switching activity in large digital systems introduces power supply or substrate noise which perturb the more sensitive blocks in a PLL, especially the voltage-controlled oscillators (VCOs), 　At system level, this work investigates the effects of PLL design parameters, such as bandwidth and peaking in frequency r

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黃名宏. "Jitter Tolerant Differential Non-linearity Measurement." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/59830491459141580458.

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碩士<br>國立交通大學<br>電機學院碩士在職專班電機與控制組<br>96<br>As the prosperity of technology, circuit becomes more complicated and scale is going to be smaller. Thus, there’re many problems which are used to be treated as bias and can be ignored originally become much difficulty to overcome at present , jitter for example .Differential non-linearity measurement (Linear Ramp histogram method) introduced in IEEE 1057 can’t measure Differential non-linearity precisely within reasonable time frame in the case of turbulent jitter. To have accurate measurement of Differential non-linearity under the influence of jitte

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Thomas, Linson. "Power Integrity Analysis For Jitter Characterization." Thesis, 2016. http://ethesis.nitrkl.ac.in/8271/1/2016_MT_214EC2185_Power.pdf.

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Continuous improvements in the VLSI domain have enabled the integration of billions of transistors on the same die operating at frequencies in the gigahertz range. These advancements have brought upon the era of system-on-chip (SoC). Traditionally, analog ICs has been prone to device noise while digital ICs have typically not been the prime concern being considered as relatively immune to noise. With faster transition times and denser integration, the scenario wherein digital ICs were considered to be immune to noise has changed significantly. Drastic changes in the physical design of an IC an

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CHIANG, HU-CHENG, and 江虎城. "Design of High Resolution, Low Measured Jitter Errorand Variation Resilient On-Chip Jitter Sensor for DDR4-3200." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/m36b79.

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碩士<br>國立中正大學<br>電機工程研究所<br>106<br>As the technology node progresses and the operating frequency of circuit and system increases, variation’s affection becomes more and more critical, and jitter effect is one of the most severe variations. However, jitter effect is difficult to be measured and quantified in most on chip systems. In the past, jitter had to be measured via external equipment, but as the operating frequency rise, the equipment which is able to conduct high frequency jitter measurement are costly, and the probe-caused noise will affect the measurement results. To measure jitter mor

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Lee, Jae Wook. "A BIST circuit for random jitter measurement." Thesis, 2012. http://hdl.handle.net/2152/ETD-UT-2012-05-5513.

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Jitter is a dominant factor contributing to a high bit error rate (BER) in high speed I/O circuitry, and it aggravates the quality of a clock signal from a phase-locked loop (PLL), subsequently impacting a given timing budget. The recent proliferation of systems-on-a-chip (SoCs) with help of technology scaling makes jitter measurement more challenging as the SoCs integrate more I/O circuitry and PLLs within a chip. Jitter has been, however, one of the most difficult parameters to measure accurately when validating the high speed serial I/O circuitry or PLLs, mostly due to its small value. Ext

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Yang, Wang-Ru, and 楊旺儒. "Real Time Process Scheduling with Jitter Control." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/38383162441198813976.

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HSIAO, MING-FU, and 蕭明富. "Minimizing Coupling Jitter in Multiple Clock Networks." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/94422126303274728418.

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博士<br>國立臺灣大學<br>電機工程學研究所<br>91<br>Crosstalk noise is a crucial factor affecting chip performance in deep submicron technologies. Among all possible crosstalk noise sources, clock is the most common aggressor as well as victim. Crosstalk on clock nets can increase coupling jitter, which may degrade significantly the system performance. Besides, in modern chip designs, there is usually more than one clock net, and sometimes even tens of them. It is therefore imperative to design clock topologies to prevent possible coupling jitter among them. In this Dissertation, we address the coupling jitter

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Chiang, Yu-Chen, and 江宇晟. "Jitter Performance Study For Phase-Lock Loop." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/70476321354403064487.

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碩士<br>國立清華大學<br>電機工程學系<br>93<br>In many circuits, PLL must provide an output clock to follow the input clock closely. Examples of applications that use PLL include clock and data recovery, clock synthesis, and synchronization, frequency synthesis and PLL modulator or de-modulator application. As environment clock speed rise up, the jitter performance for PLL is more and more important. The jitter source of PLL comes from many no ideal effect of PLL, such as power supply noise, substrate noise, VCO noise, and charge pump current mismatch. This thesis proposes the prediction method of jitter per

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Zhao, Ann-Shen, and 趙安生. "Built-in Self Test for jitter measurement." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/30296290427134359925.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>93<br>Phase-locked loops (PLLs) are often served as clock generators and/or frequency synthesizers in a system on a chip (SoC). Since it is usually built inside the chip deeply, it is hard to test PLL directly by using automatic test equipments (ATEs). For a clock signal generated by a PLL, jitter is one of the specifications which are hardest to be test. 　At the beginning of this thesis, we survey and investigate several built-in self-test (BIST) schemes used for jitter measurement in recent years. We also summarize pros, cons and challenges in practical impleme

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Yang, Cheng-Han, and 楊承翰. "Area-Efficient One-Period Delay Jitter Measurement." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/55031029915294714988.

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碩士<br>國立彰化師範大學<br>電子工程學系<br>97<br>In this thesis, a true one-period delay circuit is proved to be actually a synchronous mirror delay. An area-efficient all-digital synchronous mirror delay is thus developed as a true one-period delayline for cycle-to-cycle jitter measurement. In our preliminary work we develop an area-efficient SMD. The power dissipation can thus be also reduced. A VDL is designed for the testability of the SMD [11]. In the comparison pervious work, the author in [10] first develop a one period delay circuit. They add some control gates to a long VDL and generate the postpone

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Chen, Jyh Ming, and 陳志銘. "Jitter Analysis in Asynchronous and Synchronous Networks." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/08680229559803567960.

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Chen, Chien Hung, and 陳建宏. "An Auto Jitter Calibration Dealy-Locked Loop." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/28450179770886339855.

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碩士<br>國立臺灣師範大學<br>應用電子科技研究所<br>99<br>With a first order system and the noise would not accumulate in the voltage controlled delay line (VCDL), delay-locked loop has advamtages such as: easy to design, having small aarea and good jitter performance for clock generator.So it is becoming a popular architecture used in memory intergface, LCD, wireless communication system... etc. However, the locking time and the jitter caused by non-ideal effect are important topics for delaylocked loop. In this paper, we proposed an auto jitter calibration delay-locked loop with fast locking feature to overcome

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Liao, Xin-Sheng, and 廖信勝. "Design of Low Jitter Phase-Locked Loop." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/f28e8d.

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碩士<br>國立臺北科技大學<br>電腦與通訊研究所<br>96<br>Each device has been employed in PLL would contribute the unavoidable noise to degrade the jitter performance. In addition, the power/ground and substrate noise injected to PLL which integrated in a chip also aggravates jitter heavily. This thesis proposed some improvements for the essential issue of low jitter. We consequently improve the circuit architecture of each device and described it as following. One of that is to add self-adjusted mechanism into a charge pump to eliminate whose output current mismatch; furthermore, the mechanism is capable to exten

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Brooks, Anna. "The neural correlates of the jitter illusion." Thesis, 2004. https://researchonline.jcu.edu.au/1034/1/01front.pdf.

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The work that follows introduces a new visual illusion. The ‘jitter’ illusion arises in response to single brief presentations of stationary Glass patterns composed of decrement- and increment-defined dot-pairs. Remarkably, the perceptions that arise are of coherent global motion in trajectories that are consistent with the spatial configuration of the Glass patterns; patterns configured according to concentric functions give rise to perceptions of motion in concentric trajectories, those configured according to radial functions give rise to perceptions of motion in radial trajectories, and so

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