Relevant bibliographies by topics / JK flip-flop

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'JK flip-flop'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "JK flip-flop"

1

Andaloussi, Issam, and Moulay Brahim Sedra. "A design of sequential reversible circuits by reversible gates." International Journal of Engineering & Technology 9, no. 2 (April 18, 2020): 397. http://dx.doi.org/10.14419/ijet.v9i2.30451.

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Reversible logic has become increasingly important in the design of low power CMOS circuits, quantum computing and nanotechnology. In this article we work on recent sequential circuits namely RS Flip Flop JK Flop Flip Flop Flop Flip Flop Master Slave Flip Flop using some reversible gates FG (Feyman Gate), FRG (Fredkin Gate), NG (New Gate) , PG (Peres Gate), BJN (New BJN Gate), while modifying them to obtain new circuits keeping their same functionality and increasing their performances.
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Surya Ali, Septian. "Trainer Gerbang Logika Digital Berbasis Arduino Mega 2560." JASEE Journal of Application and Science on Electrical Engineering 1, no. 02 (February 28, 2021): 47–62. http://dx.doi.org/10.31328/jasee.v1i02.13.

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Materi Rangkaian Digital merupakan komponen penting yang perlu di pelajari oleh mahasiswa Teknik Elektro karena di dunia elekronik tidak luput dari yang namanya Rangkaian Digital. Untuk memudahkan hal tersebut maka peneitian ini dengan menggunakan mikrokontrol Arduino Mega 2560 dapat membuat modul praktikum yang simpel dan mudah di pahami. masukan yang dihasilkan adalah dengan menggerakkan posisi toggle switch dan untuk indikator keluaran adalah lampu led, dan pengujian gerbang logika dilakukan dengan beberapa cara yaitu pengujian rangkaian kombinasional gerbang logika AND, OR, NOT, NAND, NOR, XOR, dan XNOR, masing-masing di uji dari 2 input 1 output, 3 input 1 output dan 4 input 1 output. Dan rangkaian sekuensial RS Flip-Flop, D Flip-Flop, T Flip-Flop, JK Flip-Flop, hasil pengujian yang diperoleh, masing-masing rangkaian kombinasional sudah sesuai dengan tabel kebenaran gerbang logika.
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Yao, Mao Qun, Li Bin Zhang, and Han Neng Ye. "BiCMOS Flip-Flop Design Based on NPN-NPN Feedback Driver Circuits." Advanced Materials Research 712-715 (June 2013): 1826–29. http://dx.doi.org/10.4028/www.scientific.net/amr.712-715.1826.

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based on the analyzing the characteristic of BiCMOS circuits and theory of transmission voltage-switches, we proposed a general structure of binary BiCMOS circuit based on NPN-NPN feedback driver circuit. Then we designed binary BiCMOS master-slave JK flip-flop circuit and transmission gate D flip-flop circuit base on the general structure of NPN-NPN feedback driver circuit. With using HSPICE simulation, the results show that the circuits have the correct logical function. The proposed driver circuits can be used in the design of BiCMOS sequential circuits.
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Jin, Fang, Hengchang Rao, Zhi Zhao, Junlei Song, Wenqin Mo, Yajuan Hui, and Kaifeng Dong. "Skyrmion-based JK flip–flop with a wedge-shaped circular track." Japanese Journal of Applied Physics 59, no. 1 (January 1, 2020): 010907. http://dx.doi.org/10.7567/1347-4065/ab6507.

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Lin, Mi, and Ling-ling Sun. "A novel ternary JK flip-flop using the resonant tunneling diode literal circuit." Journal of Zhejiang University SCIENCE C 13, no. 12 (December 2012): 944–50. http://dx.doi.org/10.1631/jzus.c1200214.

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Zhang, Yongqiang, Guangjun Xie, and Hongjun Lv. "Dual-edge triggered JK flip-flop with comprehensive analysis in quantum-dot cellular automata." Journal of Engineering 2018, no. 7 (July 1, 2018): 354–59. http://dx.doi.org/10.1049/joe.2018.0138.

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Angizi, Shaahin, Samira Sayedsalehi, Arman Roohi, Nader Bagherzadeh, and Keivan Navi. "Design and Verification of New n-Bit Quantum-Dot Synchronous Counters Using Majority Function-Based JK Flip-Flops." Journal of Circuits, Systems and Computers 24, no. 10 (October 25, 2015): 1550153. http://dx.doi.org/10.1142/s0218126615501534.

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Quantum-dot Cellular Automata (QCA) is an attractive nanoelectronics paradigm which is widely advocated as a possible replacement of conventional CMOS technology. Designing memory cells is a very interesting field of research in QCA domain. In this paper, we are going to propose novel nanotechnology-compatible designs based on the majority gate structures. In the first step, this objective is accomplished by QCA implementation of two well-organized JK flip-flop designs and in the second step; synchronous counters with different sizes are presented as an application. To evaluate functional correctness of the proposed designs and compare with state-of-the-art, QCADesigner tool is employed.
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Mandal, Sumana, Dhoumendra Mandal, Mrinal Kanti Mandal, and Sisir Kumar Garai. "Design of frequency-encoded data-based optical master-slave-JK flip-flop using polarization switch." Optical Engineering 56, no. 6 (June 14, 2017): 066105. http://dx.doi.org/10.1117/1.oe.56.6.066105.

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Pandey, Shraddha, Sonali Singh, and Subodh Wairya. "Designing an Efficient Approach for JK and T Flip-Flop with Power Dissipation Analysis Using QCA." International Journal of VLSI Design & Communication Systems 7, no. 3 (June 30, 2016): 29–48. http://dx.doi.org/10.5121/vlsic.2016.7303.

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10

Srivastava, Ashok. "N-MOS JK master/slave flip flop design for use in high speed control and counting applications." Microelectronics Reliability 26, no. 2 (January 1986): 265–69. http://dx.doi.org/10.1016/0026-2714(86)90722-5.

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Dissertations / Theses on the topic "JK flip-flop"

1

Kocina, Filip. "Moderní metody modelování a simulace elektronických obvodů." Doctoral thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-412585.

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Disertační práce se zabývá simulací elektronických obvodů. Popisuje metodu kapacitorové substituce (CSM) pro převod elektronických obvodů na elektrické obvody, jež mohou být následně řešeny pomocí numerických metod, zejména Moderní metodou Taylorovy řady (MTSM). Tato metoda se odlišuje automatickým výběrem řádu, půlením kroku v případě potřeby a rozsáhlou oblastí stability podle zvoleného řádu. V rámci disertační práce bylo autorem disertace vytvořeno specializované programové vybavení pro řešení obyčejných diferenciálních rovnic pomocí MTSM, s mnoha vylepšeními v algoritmech (v porovnání s TKSL/386). Tyto algoritmy zahrnují zjednodušování obecných výrazů na polynomy, paralelizaci nezávislou na integrační metodě atp. Tento software běží na linuxovém serveru, který komunikuje pomocí protokolu TCP/IP. Toto vybavení bylo úspěšně použito pro simulaci VLSI obvodů, jejichž řešení pomocí CSM bylo značně rychlejší a spotřebovávalo méně paměti než state-of-the-art SPICE.
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Book chapters on the topic "JK flip-flop"

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Ishrat, Mehak, Birinderjit Singh Kalyan, Amandeep Sharma, and Balwinder Singh. "Design and Optimization of Synchronous Counter Using Majority Gate-Based JK Flip-Flop." In Communications in Computer and Information Science, 84–95. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0111-1_9.

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Mukherjee, Chiradeep, Saradindu Panda, Asish Kumar Mukhopadhyay, and Bansibadan Maji. "JK Flip-Flop Design Using Layered T Logic: A Quantum-Dot Cellular Automata-Based Approach." In Algorithms for Intelligent Systems, 105–12. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-3368-3_10.

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Conference papers on the topic "JK flip-flop"

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Maruthi, K. Naga, R. Manohari Ramchandran, and Shanthi Prince. "Design of all optical JK Flip Flop." In 2016 International Conference on Communication and Signal Processing (ICCSP). IEEE, 2016. http://dx.doi.org/10.1109/iccsp.2016.7754541.

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Dai, Yanyun, and Jizhong Shen. "An explicit-pulsed double-edge triggered JK flip-flop." In Signal Processing (WCSP 2009). IEEE, 2009. http://dx.doi.org/10.1109/wcsp.2009.5371580.

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Lin, Mi, Hai-Peng Zhang, and Wei-Feng Lv. "An improved ternary three-rail JK flip-flop design." In 2016 International Conference on Integrated Circuits and Microsystems (ICICM). IEEE, 2016. http://dx.doi.org/10.1109/icam.2016.7813569.

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Zhao Xianghong, Guo Jiankang, and Song Guanghui. "An improved low-power clock-gating pulse-triggered JK flip-flop." In 2010 International Conference on Information, Networking and Automation (ICINA 2010). IEEE, 2010. http://dx.doi.org/10.1109/icina.2010.5636463.

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Yuejun Zhang and Pengjun Wang. "Design of multi-valued double-edge-triggered JK flip-flop based on neuron MOS transistor." In 2009 IEEE 8th International Conference on ASIC (ASICON). IEEE, 2009. http://dx.doi.org/10.1109/asicon.2009.5351606.

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Dhar, Krishnendu. "Design of a high speed, low power synchronously clocked NOR-based JK flip-flop using modified GDI technique in 45nm technology." In 2014 International Conference on Advances in Computing, Communications and Informatics (ICACCI). IEEE, 2014. http://dx.doi.org/10.1109/icacci.2014.6968212.

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You might also be interested in the extended bibliographies on the topic 'JK flip-flop' for particular source types:
Journal articles
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