Relevant bibliographies by topics / Junction Field-Effect Transistor(JFET)

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Junction Field-Effect Transistor(JFET)'

Author: Grafiati
Published: 4 June 2021
Last updated: 13 February 2022

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Journal articles on the topic "Junction Field-Effect Transistor(JFET)"

1

Marcoux, J., J. Orchard-Webb, and J. F. Currie. "Complementary metal oxide semiconductor-compatible junction field-effect transistor characterization." Canadian Journal of Physics 65, no. 8 (August 1, 1987): 982–86. http://dx.doi.org/10.1139/p87-156.

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We report on the fabrication and electrical characterization of a vertical junction-gate field-effect transistor (JFET) that is compatible with all complementary metal oxide semiconductor (CMOS) technologies. It can be used as a buried load for an enhancement n-channel metal oxide semiconductor field-effect transistor (n-MOSFET), replacing the p-MOSFET within the standard CMOS inverter configuration and resulting in a 40% net area economy in standard cells. To be entirely CMOS process compatible, this JFET device differs from others in the literature in that dopant concentrations in the n substrates (1014) and in the p wells (1015) are substantially lower. For integrated-circuit applications, one seeks to use the JFET with the smallest area to minimize parasitic capacitances and to maximize switching speeds. However, at these concentration levels, the dc current–voltage characteristics depend critically on the lateral dimension of the JFET's square channel. Above 10 μm, the characteristics are pentode-like and similar to those of a classic MOSFET. Below 10 μm, the channel is naturally pinched-off, and for reverse gate bias, the small JFETs are triode-like. There is also a nonreciprocity between the source and the drain when the source-to-drain voltage polarity is changed, which is due to the distance between the channel and the electrode collecting the carriers. When its gate is forward-biased, the small JFETs behave as bipolar transistors. Depending on source-to-drain voltage polarities, I–V characteristics exhibit saturation effects caused by base-widening phenomena at the JFET's drain contact.
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Bargieł, Kamil, Damian Bisewski, and Janusz Zarębski. "Modelling of Dynamic Properties of Silicon Carbide Junction Field-Effect Transistors (JFETs)." Energies 13, no. 1 (January 1, 2020): 187. http://dx.doi.org/10.3390/en13010187.

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The paper deals with the problem of modelling and analyzing the dynamic properties of a Junction Field Effect Transistor (JFET) made of silicon carbide. An examination of the usefulness of the built-in JFET Simulation Program with Integrated Circuit Emphasis (SPICE) model was performed. A modified model of silicon carbide JFET was proposed to increase modelling accuracy. An evaluation of the accuracy of the modified model was performed by comparison of the measured and calculated capacitance–voltage characteristics as well as the switching characteristics of JFETs.
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BLALOCK, BENJAMIN J., SORIN CRISTOLOVEANU, BRIAN M. DUFRENE, F. ALLIBERT, and MOHAMMAD M. MOJARRADI. "THE MULTIPLE-GATE MOS-JFET TRANSISTOR." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 511–20. http://dx.doi.org/10.1142/s0129156402001423.

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A new SOI device, the MOS-JFET, has been developed that combines two different transistors, JFET and MOSFET, superimposed in a single silicon island so that they share the same body. A unique attribute of the MOS-JFET is that it can be viewed as a four gate transistor (two side junction-based gates, the top MOS gate, and the back gate activated by SOI substrate biasing). Each of these four gates can control the conduction characteristics of the transistor. This novel transistor's multiple gate inputs give rise to exciting circuit opportunities for analog, RF, mixed-signal, and digital applications. Measured results of MOS-JFET transistors, fabricated in a conventional partially-depleted SOI technology, demonstrate that the device is fully operational. From the experiments and systematic 2-D simulations, typical regions of operation are identified. These results indicate that optimum performance is reached when the MOS and junction field-effects are combined.
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Ehiagwina, Frederick Ojiemhende, Olufemi Oluseye Kehinde, Lateef Olashile Afolabi, Hassan Jimoh Onawola, and Nurudeen Ajibola Iromini. "Applications, Prospects and Challenges of Silicon Carbide Junction Field Effect Transistor (SIC JFET)." International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems 5, no. 3 (September 27, 2016): 133. http://dx.doi.org/10.11601/ijates.v5i3.168.

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Properties of Silicon Carbide Junction Field Effect Transistor (SiC JFET) such as high switching speed, low forward voltage drop and high temperature operation have attracted the interest of power electronic researchers and technologists, who for many years developed devices based on Silicon (Si). A number of power system Engineers have made efforts to develop more robust equipment including circuits or modules with higher power density. However, it was realized that several available power semiconductor devices were approaching theoretical limits offered by Si material with respect to capability to block high voltage, provide low on-state voltage drop and switch at high frequencies. This paper presents an overview of the current applications of SiC JFET in circuits such as inverters, rectifiers and amplifiers. Other areas of application reviewed include; usage of the SiC JFET in pulse signal circuits and boost converters. Efforts directed toward mitigating the observed increase in electromagnetic interference were also discussed. It also presented some areas for further research, such as having more applications of SiC JFET in harsh, high temperature environment. More work is needed with regards to SiC JFET drivers so as to ensure stable and reliable operation, and reduction in the prices of SiC JFETs through mass production by industries.
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Casady, J. B., D. C. Sheridan, A. Ritenour, V. Bondarenko, and R. Kelley. "High Temperature Performance of Normally-off SiC JFET's Compared to Competing Approaches." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (January 1, 2010): 000152–59. http://dx.doi.org/10.4071/hitec-jcasady-tp23.

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Normally-off Silicon Carbide (SiC) power Junction Field Effect Transistors (JFETs) were compared with competing power transistor technology at temperatures from 25 °C to 150 °C as limited by the packaging. Switching energies were measured from 1200 V, 125 mΩ and 50 mΩ (room temperature) rated SiC power JFETs and compared with 900 V silicon (Si) super-junction Metal Oxide Semiconductors (MOSFETs) and 1200 V Si Insulated Gate Bipolar Transistors (IGBTs). For both comparisons, measured performance for the SiC power JFET was advantageous at all temperatures when switching at 50 kHz, including a total switching energy (ESW) of 97 μJ for the SiC JFET, compared with 158 μJ for the Si super-junction MOSFET, and 550 μJ for the Si IGBT at 25 °C. At 150°C, the ESW was 138 μJ for the SiC power JFET, 413 μJ for the Si super-junction MOSFET, and 1020 μJ for the Si IGBT. Increasing the die size of the 1200 V, normally-off SiC JFET by 2.25 resulted in an measured increase in switching energy of 2.7 and 2.37 at 25 °C and 150 °C, respectively, a quasi-linear relationship. Higher power preview products of the SiC normally-off JFET technology were also examined including a 1200 V, 25 mΩ (room-temperature rating) power JFET characterized up to 250 °C, and a module capable of 1200 V, 120 A DC performance at 25 °C.
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Lee, Hyeyoung, Jin-A. Jeon, Jinyong Kim, Hyunsu Lee, Moo Hyun Lee, Manwoo Lee, Seungcheol Lee, Hwanbae Park, and Sukjune Song. "Measurement of Switching Performance of Pixelated Silicon Sensor Integrated with Field Effect Transistor." Sensors 19, no. 24 (December 17, 2019): 5580. http://dx.doi.org/10.3390/s19245580.

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Silicon shows very high detection efficiency for low-energy photons, and the silicon pixel sensor provides high spatial resolution. Pixelated silicon sensors facilitate the direct detection of low-energy X-ray radiation. In this study, we developed junction field effect transistors (JFETs) that can be integrated into a pixelated silicon sensor to effectively handle many signal readout channels due to the pixelated structure without any change in the sensor resolution; this capability of the integrated system arises from the pixelated structure of the sensor. We focused on optimizing the JFET’s switching function, and simulated JFETs with different fabrication parameters. Furthermore, prototype JFET switches were designed and fabricated on the basis of the simulated results. It is important not only to keep the low leakage currents in the JFET but also reduce the current flow as much as possible by providing a high resistance when the JFET switch is off. We determined the optimal fabrication conditions for the effective switching of the JFETs. In this paper, we present the results of the measurement of the switching capability of the fabricated JFETs for various design variables and fabrication conditions.
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Chaw, Chaw Su Nandar Hlaing, and Thiri Nwe. "Analysis on Band Layer Design and J-V characteristics of Zinc Oxide Based Junction Field Effect Transistor." Journal La Multiapp 1, no. 2 (June 21, 2020): 14–21. http://dx.doi.org/10.37899/journallamultiapp.v1i2.108.

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This paper presents the band gap design and J-V characteristic curve of Zinc Oxide (ZnO) based on Junction Field Effect Transistor (JFET). The physical properties for analysis of semiconductor field effect transistor play a vital role in semiconductor measurements to obtain the high-performance devices. The main objective of this research is to design and analyse the band diagram design of semiconductor materials which are used for high performance junction field effect transistor. In this paper, the fundamental theory of semiconductors, the electrical properties analysis and bandgap design of materials for junction field effect transistor are described. Firstly, the energy bandgaps are performed based on the existing mathematical equations and the required parameters depending on the specified semiconductor material. Secondly, the J-V characteristic curves of semiconductor material are discussed in this paper. In order to achieve the current-voltage characteristic for specific junction field effect transistor, numerical values of each parameter which are included in analysis are defined and then these resultant values are predicted for the performance of junction field effect transistors. The computerized analyses have also mentioned in this paper.
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Perez, S., A. M. Francis, J. Holmes, and T. Vrotsos. "Silicon Carbide Junction Field Effect Transistor Compact Model for Extreme Environment Integrated Circuit Design." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2021, HiTEC (April 1, 2021): 000118–22. http://dx.doi.org/10.4071/2380-4491.2021.hitec.000118.

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Abstract Presented is a temperature and geometry scalable 800°C Silicon Carbide (SiC) Junction Field Effect Transistor (JFET) compact device model designed to simulate the small signal effects of the SiC JFET-R process developed by NASA Glenn Research Center. With the JFET-R process pushing the temperature limits of integrated circuits, a high-fidelity device model capable of predicting the performance over temperature and geometry is required to realize the thermal ruggedness this process provides. A high temperature (HT) packaging system was utilized to characterize a SiC JFET device up to 800°C with a dwell time of 9 hours during a single test. Invaluable device characterization data was obtained and utilized to extend the device model presented to simulate SiC JFET performance continuously over 800°C.
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Kaneko, Mitsuaki, Ulrike Grossner, and Tsunenobu Kimoto. "SiC Vertical-Channel n- and p-JFETs Fully Fabricated by Ion Implantation." Materials Science Forum 963 (July 2019): 841–44. http://dx.doi.org/10.4028/www.scientific.net/msf.963.841.

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Silicon carbide (SiC) n-and p-channel junction field effect transistors (JFETs) with vertical channels were fabricated by direct ion implantation into a high-purity semi-insulating 4H-SiC substrate in order to further develop the path towards complementary JFET integrated circuits for applications in harsh environments. Compared with the conventional structure (lateral channel), the proposed structure is suitable for integration and inherently has a high transconductance owing to the double-gate configuration. The threshold voltage (Vth) can be controlled by mask design, while Vth in the conventional structure is solely determined by the ion implantation conditions. We demonstrate the transistor operation of the vertical-channel n-and p-channel JFETs fully fabricated by ion implantation.
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Casady, Jeff B., David C. Sheridan, Robin L. Kelley, Volodymyr Bondarenko, and Andrew Ritenour. "A Comparison of 1200 V Normally-OFF & Normally-on Vertical Trench SiC Power JFET Devices." Materials Science Forum 679-680 (March 2011): 641–44. http://dx.doi.org/10.4028/www.scientific.net/msf.679-680.641.

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Equivalent sized (4.5 mm2 die area), 1200 V, 4H-SiC, vertical trench Junction Field Effect Transistors (JFETs) were characterized in terms of DC and switching performance. The 100 mΩ Enhancement-Mode (EM) JFET was found to have natural advantages in safe operation being normally-off, whereas the Depletion-Mode (DM) JFET was found to have advantages with ~ twice as high saturation current, less on-resistance (85 mΩ) and no gate current required in the on-state. The JFETs were found to both have radically less (five to ten times) switching energies than corresponding 1200 V Si transistors, with the DM JFET and EM JFET having EON and EOFF of only 115 µJ and 173 µJ, respectively when tested at half-rated voltage (600 V) and 12 A.
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Dissertations / Theses on the topic "Junction Field-Effect Transistor(JFET)"

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Ding, Hao. "FOUR TERMINAL JUNCTION FIELD-EFFECT TRANSISTOR MODEL FOR COMPUTER-AIDED DESIGN." Doctoral diss., University of Central Florida, 2007. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3129.

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A compact model for four-terminal (independent top and bottom gates) junction field-effect transistor (JFET) is presented in this dissertation. The model describes the steady-state characteristics with a unified equation for all bias conditions that provides a high degree of accuracy and continuity of conductance, which are important for predictive analog circuit simulations. It also includes capacitance and leakage equations. A special capacitance drop-off phenomenon at the pinch-off region is studies and modeled. The operations of the junction fieldeffect transistor (JFET) with an oxide top-gate and full oxide isolation are analyzed, and a semi-physical compact model is developed. The effects of the different modes associated with the oxide top-gate on the JFET steady-state characteristics of the transistor are discussed, and a single expression applicable for the description of the JFET dc characteristics for all operation modes is derived. The model has been implemented in Verilog-A and simulated in Cadence framework for comparison to experimental data measured at Texas Instruments.
Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering
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Wake, D. "The development of an indium gallium arsenide junction field effect transistor for use in optical receivers." Thesis, University of Surrey, 1987. http://epubs.surrey.ac.uk/843424/.

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The objective of this work was to design and develop a high performance field effect transistor to be suitable for monolithic integration with a photodetector for use in long wavelength optical communication systems. It was decided that the most promising type of device for this application was a junction field effect transistor (JFET), fabricated using the alloy In.53Ga.47As grown epitaxially onto an InP substrate. The requirements for such a device were that it should have high transconductance, low input capacitance, and low gate leakage current (for high receiver sensitivity), and that it should have a structure which would be easily integrated monolithically with the desired type of photodetector - an In.53Ga.47As PIN-photodiode. Although this alloy semiconductor has favourable electron transport properties, at the start of this work, high performance field effect transistors had not been realised in this material. In particular, the In.53Ga.47AS FETs that had been made at that time were characterised by low transconductance. Using a device design that incorporated many novel and efficacious features, the JFET described in this work gave results which greatly surpassed all previous (and current) published results of similar devices. This device not only showed high performance, but the novel design features also enabled a simple fabrication scheme. Having developed this very high performance discrete device, the feasibility of monolithic integration with a In.53Ga.47As PIN-photodiode was demonstrated. Although the physical size and material requirements of these two devices were very different, novel design features enabled the construction of a monolithic PIN-FET combination, in which the performance of the JFET was not compromised.
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Song, Shiunn Luen Steven 1960. "Characterization and design of the complementary JFET LAMBDA-DIODE SRAM." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276882.

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The LAMBDA-DIODE was invented in integrated-circuit form in 1974. There was a proposal about this device's application in memory circuits at that time. This thesis is to evaluate the circuit performance of the COMPLEMENTARY JFET LAMBDA-DIODE SRAM. It investigates the speed, power consumption and chip area of this circuit compared with the JFET CROSS COUPLED SRAM by using SPICE and breadboard simulation techniques. The results show positive signs of the Λ-DIODE's feasibility for use in VLSI static memory circuits from the chip area aspect if the parasitic capacitance of the JFET device could be minimized to reduce the power delay product.
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Hamieh, Youness. "Caractérisation et modélisation du transistor JFET en SiC à haute température." Phd thesis, INSA de Lyon, 2011. http://tel.archives-ouvertes.fr/tel-00665817.

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Dans le domaine de l'électronique de puissance, les dispositifs en carbure de silicium (SiC) sont bien adaptés pour fonctionner dans des environnements à haute température, haute puissance, haute tension et haute radiation. Le carbure de silicium (SiC) est un matériau semi-conducteur à large bande d'énergie interdite. Ce matériau possède des caractéristiques en température et une tenue aux champs électriques bien supérieure à celles de silicium. Ces caractéristiques permettent des améliorations significatives dans une grande variété d'applications et de systèmes. Parmi les interrupteurs existants, le JFET en SiC est l'interrupteur le plus avancé dans son développement technologique, et il est au stade de la pré-commercialisation. Le travail réalisé au cours de cette thèse consiste à caractériser électriquement des JFET- SiC de SiCED en fonction de la température (25°C-300°C). Des mesures ont été réalisé en statique (courant-tension), en dynamique (capacité-tension) et en commutation sur charge R-L (résistive-inductives) et dans un bras d'onduleur. Un modèle multi-physique du transistor VJFET de SiCED à un canal latéral a été présenté. Le modèle a été développé en langage MAST et validé aussi bien en mode de fonctionnement statique que dynamique en utilisant le simulateur SABER. Ce modèle inclut une représentation asymétrique du canal latéral et les capacités de jonction de la structure. La validation du modèle montre une bonne concordance entre les mesures et la simulation.
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Laariedh, Farah. "Technologie d’intégration monolithique des JFET latéraux." Thesis, Lyon, INSA, 2013. http://www.theses.fr/2013ISAL0031/document.

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Le carbure de silicium (SiC) est un semi-conducteur à large bande d’énergie interdite, remarquable par ses propriétés physiques situées à mi-chemin entre le silicium et le diamant. Ceci suscite actuellement un fort intérêt industriel pour son utilisation dans la fabrication de composants susceptibles de fonctionner dans des conditions extrêmes : forte puissance et haute température. Les travaux de thèse se sont focalisés sur la levée de verrous technologiques pour réaliser des composants latéraux de type JFET (Junction Field Effect Transistor) et les intégrer monolithiquement dans des substrats SiC-4H. L’objectif est de réaliser un bras d’onduleur intégré en SiC avec deux étages commande et puissance. Dans un premier temps, nous avons entamé cette thèse par une caractérisation de deux lots de composants JFET latéraux à canaux N et P réalisés dans le cadre de deux projets ANR précédents cette thèse. De cette étude nous avons extrait plusieurs points positifs, comme celui qui concerne la tenue en tension des JFET de puissance et l’intégration monolithique des JFET basse tension. Mais, nous avons aussi mis en évidence, la nécessité d’optimiser la structure de composants et d’améliorer certaines étapes technologiques, principalement, la définition des canaux par implantation ionique, le contact ohmique et la gravure profonde. Des études approfondies pour réaliser le contact ohmique sur SiC type P et des procédés pour réaliser une gravure profonde dans le SiC ont été développés. Ces études ont permis d’obtenir une faible résistance de contact comparable à l’état de l’art mondial, d’avoir des calibres en courant plus élevés et par conséquent une meilleure modulation. Pour la gravure, un masque dur à base de silicium et nickel (NiSi), nous a permis de mettre en place un procédé original qui permet des gravures profondes du SiC et réaliser les structures intégrés des JFET. L’ensemble de ces améliorations technologiques nous a permis d’obtenir des nouveaux lots de composants JFET P et N intégrés sur la même puce, avec des meilleures performances par rapport aux précédentes réalisations, notamment avec une conduction dans les canaux 10 à 100 fois plus importante. Nous avons également obtenu une modulation du courant Ids en fonction de la tension Vgs sur un nombre très important de JFET en augmentant significativement le rendement par rapport aux lots précédents
Silicon carbide (SiC) a semiconductor is as wide band gap, notable for its physical properties located between silicon and diamond. The inherent properties of silicon carbide (SiC) high thermal conductivity, and high breakdown voltage make it a very promising material for high power, high temperature and high-frequency device applications. The thesis focused on the removal of technological barriers to achieve lateral components JFET (Junction Field Effect Transistor) and monolithically integrated in SiC-4H substrates. The objective is to realize an arm of inverter integrated there SIC with two floors command and power. Initially, we started this thesis by a characterization of two lots of components JFET with channels N and P realized during two previous ANR this thesis. In this study, we extracted several positive points, such, the breakdown voltage of the JFET power and monolithic integration of low voltage JFET. But we have also highlighted the need to optimize the structure of components and improve some technological steps, mainly the definition channels by ion implantation, the ohmic contact and deep etching. Extensive to achieve ohmic contact on SiC P type and methods for performing deep etching in SiC studies have been developed. These studies have resulted in a low resistance comparable to the state of the art world contact, having sizes in higher current and therefore a better modulation. For etching, a hard mask to silicon and nickel (NiSi) has enabled us to develop a novel method that allows deep etching of SiC JFETs achieve integrated structures. All these technological improvements allowed us to get new batches of P and N JFET integrated on the same chip components with better performance compared to previous achievements, especially with conduction channels 10 to 100 times important. We also got a modulation current Ids as a function of the voltage Vgs on a large number of JFET significantly increasing the performance compared to previous batches
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Granier, André. "Etude et réalisation d'un transistor JFET vertical silicium et son évaluation en hyperfréquence." Grenoble 1, 1993. http://www.theses.fr/1993GRE10146.

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Cette etude presente la realisation d'un transistor a effet de champ vertical a jonction (jfet) compatible avec la technologie cmos du centre national d'etudes des telecommunications de meylan. Dans un premier temps, la structure du composant est presentee: elle est derivee de celle du transistor pmos et utilise un caisson de phosphore implante a haute energie en tant que drain et un siliciure de titane autoaligne. Nous decrivons les procedures et les outils de caracterisation mis en jeu. La physique du dispositif est apprehendee. Nous analysons l'observation d'un courant de grille et de substrat induit par l'ionisation par impact dans ce transistor. Un regime particulier de fonctionnement, le regime bipolaire, est decrit. Une analyse statistique des parametres electriques demontre que les dispersions sont liees a celles de la largeur de source. L'effet avantageux de la siliciuration sur les caracteristiques electriques est mis en evidence. A l'aide de la simulation numerique, nous definissons les caracteristiques technologiques de deux types de transistor dans le cadre de la filiere cmos 0,7 m. Ils se distinguent par une dose du caisson retrograde differente. A partir de mesures statiques et dynamiques, nous donnons une evaluation de ces dispositifs. Chacun presente des performances en frequence de coupure d'environ 4 ghz, limitees par la capacite de la jonction grille-drain et de la resistance de drain, et des tensions de claquages superieures a 10 v. Ainsi, nous montrons qu'un jfet vertical peut etre developpe pour des applications de puissance hyperfrequence avec un excellent compromis cout-performance. Enfin une approche du jfet vertical realise sur une couche enterree est etudiee
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Guédon, Florent Dominique. "Power converters with normally-on SiC JFETs." Thesis, University of Cambridge, 2012. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.610394.

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Falahi, Khalil El. "Contribution à la conception de driver en technologie CMOS SOI pour la commande de transistors JFET SiC pour un environnement de haute température." Thesis, Lyon, INSA, 2012. http://www.theses.fr/2012ISAL0056/document.

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Dans le domaine aéronautique, les systèmes électriques remplacement progressivement les systèmes de contrôle mécaniques ou hydrauliques. Les bénéfices immédiats sont la réduction de la masse embarquée et des performances accrues à condition que l’électronique supporte l’absence de système de refroidissement. Si la haute température de fonctionnement n’empêche pas d’atteindre une fiabilité suffisante, il y aura réduction des coûts opérationnels. Des étapes clefs ont été franchies en introduisant des systèmes à commande électriques dans les aéronefs en lieu et place de systèmes conventionnels : freins électriques, inverseur de poussée, vérins électriques de commandes de vol… Toutes ces avancées se sont accélérées ces dernières années grâce entre autre à l’utilisation de nouveaux matériaux semiconducteurs, dit à grand gap (SiC, GaN…), opérant à haute température et palliant ainsi une faiblesse des dispositifs classiques en silicium (Si). Des composants de puissance haute température, diode Schottky ou transistor JFET SiC, sont ainsi disponibles commercialement et peuvent supporter des ambiantes de plus de 220°C. Des modules de puissances (onduleur) à base de transistor JFET SiC ont été réalisés et validés à haute température. Finalement la partie « commande » de ces modules de puissance reste à concevoir pour les environnements sévères pour permettre leur introduction dans le module de puissance. C’est dans ce contexte de faiblesse concernant l’étage de commande rapprochée qu’a été construit le projet FNRAE COTECH, et où s’inscrivent les travaux de cette thèse, Dans un premier temps, un état de l’art sur les drivers et leurs technologies nous a permis de souligner le lien complexe entre électronique et température ainsi que le potentiel de la technologie CMOS sur Silicium sur Isolant (SOI) pour des applications hautes températures. La caractérisation en température de drivers SOI disponibles dans le commerce nous a fourni des données d’entrée sur le comportement de tels dispositifs. Ces caractérisations sont essentielles pour visualiser et interpréter l’effet de la température sur les caractéristiques du dispositif. Ces mesures mettent aussi en avant les limites pratiques des technologies employées. La partie principale de cette thèse concerne la conception et la caractérisation de blocs ou IPs pour le cœur d’un driver haute température de JFET SiC. Elle est articulée autour de deux runs SOI (TFSmart1). Les blocs développés incluent entre autres des étages de sortie et leurs buffers associés et des fonctions de protection. Les drivers ainsi constitués ont été testés sur un intervalle de température allant de -50°C à plus de 250°C sans défaillance constatée. Une fonction originale de protection des JFETs contre les courts-circuits a été démontrée. Cette fonction permet de surmonter la principale limitation de ces transistors normalement passant (Normaly-ON). Finalement, un module de bras d’onduleur a été conçu pour tester ces driver in-situ
In aeronautics, electrical systems progressively replace mechanical and hydraulic control systems. If the electronics can stand the absence of cooling, the immediate advantages will be the reduction of mass, increased performances, admissible reliability and thus reduction of costs. In aircraft, some important steps have already been performed successfully when substituting standard systems by electrical control system such as electrical brakes, thrust reverser, electrical actuators for flight control… Large band gap semiconductors (SiC, GaN…) have eased the operation in high temperature over the last decade and let overcome a weakness of conventional silicon systems (Si). High temperature power components such as Schottky diodes or JFET transistors, are already commercially available for a use up to 220°C, limited by package. Moreover inverters based on SiC JFET transistors have been realized and characterized at high temperature. Finally the control part of these power systems needs to be designed for harsh environment. It is in this context of lack of integrated control part that the FNRAE COTECH project and my doctoral research have been built. Based on a state of the art about drivers, the complex link between electronic and temperature and the potentialities of CMOS Silicon-On-Insulator technology (SOI) for high temperature applications have been underlined. The characterization of commercial SOI drivers gives essential data on these systems and their behavior at high temperature. These measurements also highlight the practical limitations of SOI technologies. The main part of this manuscript concerns the design and characterization of functions or IPs for high temperature JFET SiC driver. Two SOI runs in TFSmart1 have been realized. The developed functions include the driver output stage, associated buffers and protection functions. The drivers have been tested from -50°C up to 250°C without failure under short time-range. Moreover, an original protection function has been demonstrated against the short-circuit of an inverter leg. This function allows overcoming the main limitation of the normally on JFET transistor. Finally, an inverter module has been built for in-situ test of these new drivers
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Sadik, Diane-Perle. "On Reliability of SiC Power Devices in Power Electronics." Doctoral thesis, KTH, Elkraftteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-207763.

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Silicon Carbide (SiC) is a wide-bandgap (WBG) semiconductor materialwhich has several advantages such as higher maximum electric field, lowerON-state resistance, higher switching speeds, and higher maximum allowablejunction operation temperature compared to Silicon (Si). In the 1.2 kV - 1.7kV voltage range, power devices in SiC are foreseen to replace Si Insulatedgatebipolar transistors (IGBTs) for applications targeting high efficiency,high operation temperatures and/or volume reductions. In particular, theSiC Metal-oxide semiconductor field-effect transistor (MOSFET) – which isvoltage controlled and normally-OFF – is the device of choice due to the easeof its implementation in designs using Si IGBTs.In this work the reliability of SiC devices, in particular that of the SiCMOSFET, has been investigated. First, the possibility of paralleling two discreteSiC MOSFETs is investigated and validated through static and dynamictests. Parallel-connection was found to be unproblematic. Secondly, drifts ofthe threshold voltage and forward voltage of the body diode of the SiC MOSFETare investigated through long-term tests. Also these reliability aspectswere found to be unproblematic. Thirdly, the impact of the package on thechip reliability is discussed through a modeling of the parasitic inductancesof a standard module and the impact of those inductances on the gate oxide.The model shows imbalances in stray inductances and parasitic elementsthat are problematic for high-speed switching. A long-term test on the impactof humidity on junction terminations of SiC MOSFETs dies and SiCSchottky dies encapsulated in the same standard package reveals early degradationfor some modules situated outdoors. Then, the short-circuit behaviorof three different types (bipolar junction transistor, junction field-effect transistor,and MOSFET) of 1.2 kV SiC switching devices is investigated throughexperiments and simulations. The necessity to turn OFF the device quicklyduring a fault is supported with a detailed electro-thermal analysis for eachdevice. Design guidelines towards a rugged and fast short-circuit protectionare derived. For each device, a short-circuit protection driver was designed,built and validated experimentally. The possibility of designing diode-lessconverters with SiC MOSFETs is investigated with focus on surge currenttests through the body diode. The discovered fault mechanism is the triggeringof the npn parasitic bipolar transistor. Finally, a life-cycle cost analysis(LCCA) has been performed revealing that the introduction of SiC MOSFETsin already existing IGBT designs is economically interesting. In fact,the initial investment is saved later on due to a higher efficiency. Moreover,the reliability is improved, which is beneficial from a risk-management pointof-view. The total investment over 20 years is approximately 30 % lower fora converter with SiC MOSFETs although the initial converter cost is 30 %higher.
Kiselkarbid (SiC) är ett bredbandgapsmaterial (WBG) som har flera fördelar,såsom högre maximal elektrisk fältstyrka, lägre ON-state resitans, högreswitch-hastighet och högre maximalt tillåten arbetstemperatur jämförtmed kisel (Si). I spänningsområdet 1,2-1,7 kV förutses att effekthalvledarkomponenteri SiC kommer att ersätta Si Insulated-gate bipolar transistorer(IGBT:er) i tillämpningar där hög verkningsgrad, hög arbetstemperatur ellervolymreduktioner eftersträvas. Förstahandsvalet är en SiC Metal-oxidesemiconductor field-effect transistor (MOSFET) som är spänningsstyrd ochnormally-OFF, egenskaper som möjliggör enkel implementering i konstruktionersom använder Si IGBTer.I detta arbete undersöks tillförlitligheten av SiC komponenter, specielltSiC MOSFET:en. Först undersöks möjligheten att parallellkoppla tvådiskretaSiC MOSFET:ar genom statiska och dynamiska prov. Parallellkopplingbefanns vara oproblematisk. Sedan undersöks drift av tröskelspänning ochbody-diodens framspänning genom långtidsprov. Ocksådessa tillförlitlighetsaspekterbefanns vara oproblematiska. Därefter undersöks kapslingens inverkanpåchip:et genom modellering av parasitiska induktanser hos en standardmoduloch inverkan av dessa induktanser pågate-oxiden. Modellen påvisaren obalans mellan de parasitiska induktanserna, något som kan varaproblematiskt för snabb switchning. Ett långtidstest av inverkan från fuktpåkant-termineringar för SiC-MOSFET:ar och SiC-Schottky-dioder i sammastandardmodul avslöjar tidiga tecken pådegradering för vissa moduler somvarit utomhus. Därefter undersöks kortslutningsbeteende för tre typer (bipolärtransistor,junction-field-effect transistor och MOSFET) av 1.2 kV effekthalvledarswitchargenom experiment och simuleringar. Behovet att stänga avkomponenten snabbt stöds av detaljerade elektrotermiska simuleringar för allatre komponenter. Konstruktionsriktlinjer för ett robust och snabbt kortslutningsskyddtas fram. För var och en av komponenterna byggs en drivkrets medkortslutningsskydd som valideras experimentellt. Möjligheten att konstrueradiodlösa omvandlare med SiC MOSFET:ar undersöks med fokus påstötströmmargenom body-dioden. Den upptäckta felmekanismen är ett oönskat tillslagav den parasitiska npn-transistorn. Slutligen utförs en livscykelanalys(LCCA) som avslöjar att introduktionen av SiC MOSFET:ar i existerandeIGBT-konstruktioner är ekonomiskt intressant. Den initiala investeringensparas in senare pågrund av en högre verkningsgrad. Dessutom förbättrastillförlitligheten, vilket är fördelaktigt ur ett riskhanteringsperspektiv. Dentotala investeringen över 20 år är ungefär 30 % lägre för en omvandlare medSiC MOSFET:ar även om initialkostnaden är 30 % högre.

QC 20170524

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Chevalier, Florian. "Conception, fabrication et caractérisation de transistors à effet de champ haute tension en carbure de silicium et de leur diode associée." Phd thesis, INSA de Lyon, 2012. http://tel.archives-ouvertes.fr/tel-01016687.

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Dans le contexte des transports plus électriques, les parties mécaniques tendent à être remplacées par leurs équivalents électriques plus petits. Ainsi, le composant lui-même doit supporter un environnement plus sévère et de lourdes contraintes (haute tension, haute température). Les composants silicium deviennent alors inappropriés. Depuis la commercialisation des premières diodes Schottky en 2001, le carbure de silicium est le matériau reconnu mondialement pour la fabrication de dispositifs haute tension avec une forte intégration. Sa large bande d'énergie interdite et son fort champ électrique critique permettent la conception de transistors à effet de champ avec jonction (JFET) pour les hautes tensions ainsi que les diodes associées. Les structures étudiées dépendent de nombreux paramètres, et doivent ainsi être optimisées. L'influence d'un paramètre ne pouvant être isolée, des méthodes mathématiques ont été appelées pour trouver la valeur optimale. Ceci a conduit à la mise en place d'un critère d'optimisation. Ainsi, les deux grands types de structures de JFET verticaux ont pu être analysés finement. D'une part, la recherche d'une structure atteignant les tensions les plus élevées possible a conduit à l'élaboration d'un procédé de fabrication complexe. D'autre part, un souci de simplification et de stabilisation des procédés de fabrication a permis le développement d'un composant plus simple, mais avec une limite en tension un peu plus modeste.
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Books on the topic "Junction Field-Effect Transistor(JFET)"

1

Soclof, Sidney. Junction field-effect transistors (JFETS): Principles and applications. Boston: ArtechHouse, 1996.

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Blaser, Markus. Monolithically integrated InGaAs/Inp photodiode-junction field-effect transistor receivers for fiber-optic telecommunication. Konstanz: Hartung-Gorre, 1997.

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Amara, Amara, and Rozeau Olivier, eds. Planar double-gate transistor: From technology to circuit. [Dordrecht?]: Springer, 2009.

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Solymar, L., D. Walsh, and R. R. A. Syms. Principles of semiconductor devices. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780198829942.003.0009.

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p–n junctions are examined initially and the potential distribution in the junction region is derived based on Poisson’s equation. Next the operation of the transistor is discussed, both in terms of the physics and of equivalent circuits. Potential distributions in metal–semiconductor junctions are derived and the concept of surface states is introduced. The physics of tunnel junctions is discussed in terms of their band structure. The properties of varactor diodes are described and the possibility of parametric amplification is touched upon. Further devices discussed are field effect transistors, charge-coupled devices, controlled rectifiers, and the Gunn effect. The fabrication of microelectronic circuits is discussed, followed by the more recent but related field of micro-electro-mechanical systems. The discipline of nanoelectronics is introduced including the role of carbon nanotubes. Finally, the effect of the development of semiconductor technology upon society is discussed.
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Book chapters on the topic "Junction Field-Effect Transistor(JFET)"

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Prasad, R. "Transistor Bipolar Junction (BJT) and Field-Effect (FET) Transistor." In Undergraduate Lecture Notes in Physics, 457–581. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-65129-9_6.

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Kelner, G., M. Shur, S. Binari, K. Sleger, and H. Kong. "A High Transconductance β-SiC Buried-Gate Junction Field Effect Transistor." In Springer Proceedings in Physics, 184–90. Berlin, Heidelberg: Springer Berlin Heidelberg, 1989. http://dx.doi.org/10.1007/978-3-642-75048-9_38.

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Dubey, Avashesh, Rakhi Narang, Manoj Saxena, and Mridula Gupta. "Floating Gate Junction-Less Double Gate Radiation Sensitive Field Effect Transistor (RADFET) Dosimeter: A Simulation Study." In Springer Proceedings in Physics, 571–76. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-319-97604-4_89.

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"Junction Field-Effect Transistor." In Complete Guide to Semiconductor Devices, 191–99. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2010. http://dx.doi.org/10.1002/9781118014769.ch23.

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Wilmshurst, T. H. "Junction field effect transistor." In Analog Circuit Techniques with Digital Interfacing, 132–36. Elsevier, 2001. http://dx.doi.org/10.1016/b978-075065094-6/50010-5.

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Conference papers on the topic "Junction Field-Effect Transistor(JFET)"

1

Shili, K., M. Ben Karoui, R. Gharbi, and S. Ferrero. "Structural and electrical characterization of the 4H-SiC based junction field effect transistor (JFET)." In 2013 International Conference On Electrical Engineering and Software Applications (ICEESA). IEEE, 2013. http://dx.doi.org/10.1109/iceesa.2013.6578475.

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Ou, Tzu-Min, Tomoko Borsa, and Bart Van Zeghbroeck. "Graphene junction field-effect transistor." In 2015 73rd Annual Device Research Conference (DRC). IEEE, 2015. http://dx.doi.org/10.1109/drc.2015.7175594.

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Zeisse, C. R., R. Nguyen, T. T. Vu, L. J. Messick, and K. L. Moazed. "An indium phosphide diffused junction field effect transistor." In International Conference on Indium Phosphide and Related Materials. IEEE, 1990. http://dx.doi.org/10.1109/iciprm.1990.203037.

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Jahangir, Ifat, Shafat Jahangir, and Quazi Deen Mohd Khosru. "Transport characteristics of GaInAs nanowire junction field effect transistor." In 2012 IEEE International Conference on Electro/Information Technology (EIT 2012). IEEE, 2012. http://dx.doi.org/10.1109/eit.2012.6220771.

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Baca, A. G., J. C. Zolper, M. E. Sherwin, P. J. Robertson, R. J. Shul, A. J. Howard, D. J. Rieger, and J. F. Klem. "Complementary GaAs junction-gated heterostructure field effect transistor technology." In Proceedings of 1994 IEEE GaAs IC Symposium. IEEE, 1994. http://dx.doi.org/10.1109/gaas.1994.636920.

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Vardhan Reddy, Isukapalli Vishnu, and Suman Lata Tripathi. "Double Gate-Pocket-Junction-less Tunnel Field Effect Transistor." In 2021 Devices for Integrated Circuit (DevIC). IEEE, 2021. http://dx.doi.org/10.1109/devic50843.2021.9455895.

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Benner, O., A. Lysov, C. Gutsche, G. Keller, C. Schmidt, W. Prost, and F. J. Tegude. "Junction field-effect transistor based on GaAs core-shell nanowires." In 2013 25th International Conference on Indium Phosphide and Related Materials (IPRM). IEEE, 2013. http://dx.doi.org/10.1109/iciprm.2013.6562589.

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Tomioka, K., M. Yoshimura, and T. Fukui. "First Demonstration of Tunnel Field-Effect Transistor Using InGaAs/Si Junction." In 2012 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2012. http://dx.doi.org/10.7567/ssdm.2012.e-4-3.

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Jiang, Zhi, Yiqi Zhuang, Cong Li, and Wang Ping. "The hetero material gateand hetero-junction tunnel field-effect transistor with pocket." In 2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT). IEEE, 2014. http://dx.doi.org/10.1109/icsict.2014.7021632.

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Tripathi, Ball Mukund Mani, and Shyama Prasad Das. "Vertical Channel GaN Field Effect Transistor Without Junction for High Power Application." In 2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT). IEEE, 2018. http://dx.doi.org/10.1109/conecct.2018.8482384.

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