Journal articles: 'Junction Field-Effect Transistor(JFET)'

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Marcoux, J., J. Orchard-Webb, and J. F. Currie. "Complementary metal oxide semiconductor-compatible junction field-effect transistor characterization." Canadian Journal of Physics 65, no. 8 (August 1, 1987): 982–86. http://dx.doi.org/10.1139/p87-156.

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We report on the fabrication and electrical characterization of a vertical junction-gate field-effect transistor (JFET) that is compatible with all complementary metal oxide semiconductor (CMOS) technologies. It can be used as a buried load for an enhancement n-channel metal oxide semiconductor field-effect transistor (n-MOSFET), replacing the p-MOSFET within the standard CMOS inverter configuration and resulting in a 40% net area economy in standard cells. To be entirely CMOS process compatible, this JFET device differs from others in the literature in that dopant concentrations in the n substrates (1014) and in the p wells (1015) are substantially lower. For integrated-circuit applications, one seeks to use the JFET with the smallest area to minimize parasitic capacitances and to maximize switching speeds. However, at these concentration levels, the dc current–voltage characteristics depend critically on the lateral dimension of the JFET's square channel. Above 10 μm, the characteristics are pentode-like and similar to those of a classic MOSFET. Below 10 μm, the channel is naturally pinched-off, and for reverse gate bias, the small JFETs are triode-like. There is also a nonreciprocity between the source and the drain when the source-to-drain voltage polarity is changed, which is due to the distance between the channel and the electrode collecting the carriers. When its gate is forward-biased, the small JFETs behave as bipolar transistors. Depending on source-to-drain voltage polarities, I–V characteristics exhibit saturation effects caused by base-widening phenomena at the JFET's drain contact.

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Bargieł, Kamil, Damian Bisewski, and Janusz Zarębski. "Modelling of Dynamic Properties of Silicon Carbide Junction Field-Effect Transistors (JFETs)." Energies 13, no. 1 (January 1, 2020): 187. http://dx.doi.org/10.3390/en13010187.

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The paper deals with the problem of modelling and analyzing the dynamic properties of a Junction Field Effect Transistor (JFET) made of silicon carbide. An examination of the usefulness of the built-in JFET Simulation Program with Integrated Circuit Emphasis (SPICE) model was performed. A modified model of silicon carbide JFET was proposed to increase modelling accuracy. An evaluation of the accuracy of the modified model was performed by comparison of the measured and calculated capacitance–voltage characteristics as well as the switching characteristics of JFETs.

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BLALOCK, BENJAMIN J., SORIN CRISTOLOVEANU, BRIAN M. DUFRENE, F. ALLIBERT, and MOHAMMAD M. MOJARRADI. "THE MULTIPLE-GATE MOS-JFET TRANSISTOR." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 511–20. http://dx.doi.org/10.1142/s0129156402001423.

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A new SOI device, the MOS-JFET, has been developed that combines two different transistors, JFET and MOSFET, superimposed in a single silicon island so that they share the same body. A unique attribute of the MOS-JFET is that it can be viewed as a four gate transistor (two side junction-based gates, the top MOS gate, and the back gate activated by SOI substrate biasing). Each of these four gates can control the conduction characteristics of the transistor. This novel transistor's multiple gate inputs give rise to exciting circuit opportunities for analog, RF, mixed-signal, and digital applications. Measured results of MOS-JFET transistors, fabricated in a conventional partially-depleted SOI technology, demonstrate that the device is fully operational. From the experiments and systematic 2-D simulations, typical regions of operation are identified. These results indicate that optimum performance is reached when the MOS and junction field-effects are combined.

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Ehiagwina, Frederick Ojiemhende, Olufemi Oluseye Kehinde, Lateef Olashile Afolabi, Hassan Jimoh Onawola, and Nurudeen Ajibola Iromini. "Applications, Prospects and Challenges of Silicon Carbide Junction Field Effect Transistor (SIC JFET)." International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems 5, no. 3 (September 27, 2016): 133. http://dx.doi.org/10.11601/ijates.v5i3.168.

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Properties of Silicon Carbide Junction Field Effect Transistor (SiC JFET) such as high switching speed, low forward voltage drop and high temperature operation have attracted the interest of power electronic researchers and technologists, who for many years developed devices based on Silicon (Si). A number of power system Engineers have made efforts to develop more robust equipment including circuits or modules with higher power density. However, it was realized that several available power semiconductor devices were approaching theoretical limits offered by Si material with respect to capability to block high voltage, provide low on-state voltage drop and switch at high frequencies. This paper presents an overview of the current applications of SiC JFET in circuits such as inverters, rectifiers and amplifiers. Other areas of application reviewed include; usage of the SiC JFET in pulse signal circuits and boost converters. Efforts directed toward mitigating the observed increase in electromagnetic interference were also discussed. It also presented some areas for further research, such as having more applications of SiC JFET in harsh, high temperature environment. More work is needed with regards to SiC JFET drivers so as to ensure stable and reliable operation, and reduction in the prices of SiC JFETs through mass production by industries.

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Casady, J. B., D. C. Sheridan, A. Ritenour, V. Bondarenko, and R. Kelley. "High Temperature Performance of Normally-off SiC JFET's Compared to Competing Approaches." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (January 1, 2010): 000152–59. http://dx.doi.org/10.4071/hitec-jcasady-tp23.

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Normally-off Silicon Carbide (SiC) power Junction Field Effect Transistors (JFETs) were compared with competing power transistor technology at temperatures from 25 °C to 150 °C as limited by the packaging. Switching energies were measured from 1200 V, 125 mΩ and 50 mΩ (room temperature) rated SiC power JFETs and compared with 900 V silicon (Si) super-junction Metal Oxide Semiconductors (MOSFETs) and 1200 V Si Insulated Gate Bipolar Transistors (IGBTs). For both comparisons, measured performance for the SiC power JFET was advantageous at all temperatures when switching at 50 kHz, including a total switching energy (ESW) of 97 μJ for the SiC JFET, compared with 158 μJ for the Si super-junction MOSFET, and 550 μJ for the Si IGBT at 25 °C. At 150°C, the ESW was 138 μJ for the SiC power JFET, 413 μJ for the Si super-junction MOSFET, and 1020 μJ for the Si IGBT. Increasing the die size of the 1200 V, normally-off SiC JFET by 2.25 resulted in an measured increase in switching energy of 2.7 and 2.37 at 25 °C and 150 °C, respectively, a quasi-linear relationship. Higher power preview products of the SiC normally-off JFET technology were also examined including a 1200 V, 25 mΩ (room-temperature rating) power JFET characterized up to 250 °C, and a module capable of 1200 V, 120 A DC performance at 25 °C.

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Lee, Hyeyoung, Jin-A. Jeon, Jinyong Kim, Hyunsu Lee, Moo Hyun Lee, Manwoo Lee, Seungcheol Lee, Hwanbae Park, and Sukjune Song. "Measurement of Switching Performance of Pixelated Silicon Sensor Integrated with Field Effect Transistor." Sensors 19, no. 24 (December 17, 2019): 5580. http://dx.doi.org/10.3390/s19245580.

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Silicon shows very high detection efficiency for low-energy photons, and the silicon pixel sensor provides high spatial resolution. Pixelated silicon sensors facilitate the direct detection of low-energy X-ray radiation. In this study, we developed junction field effect transistors (JFETs) that can be integrated into a pixelated silicon sensor to effectively handle many signal readout channels due to the pixelated structure without any change in the sensor resolution; this capability of the integrated system arises from the pixelated structure of the sensor. We focused on optimizing the JFET’s switching function, and simulated JFETs with different fabrication parameters. Furthermore, prototype JFET switches were designed and fabricated on the basis of the simulated results. It is important not only to keep the low leakage currents in the JFET but also reduce the current flow as much as possible by providing a high resistance when the JFET switch is off. We determined the optimal fabrication conditions for the effective switching of the JFETs. In this paper, we present the results of the measurement of the switching capability of the fabricated JFETs for various design variables and fabrication conditions.

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Chaw, Chaw Su Nandar Hlaing, and Thiri Nwe. "Analysis on Band Layer Design and J-V characteristics of Zinc Oxide Based Junction Field Effect Transistor." Journal La Multiapp 1, no. 2 (June 21, 2020): 14–21. http://dx.doi.org/10.37899/journallamultiapp.v1i2.108.

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This paper presents the band gap design and J-V characteristic curve of Zinc Oxide (ZnO) based on Junction Field Effect Transistor (JFET). The physical properties for analysis of semiconductor field effect transistor play a vital role in semiconductor measurements to obtain the high-performance devices. The main objective of this research is to design and analyse the band diagram design of semiconductor materials which are used for high performance junction field effect transistor. In this paper, the fundamental theory of semiconductors, the electrical properties analysis and bandgap design of materials for junction field effect transistor are described. Firstly, the energy bandgaps are performed based on the existing mathematical equations and the required parameters depending on the specified semiconductor material. Secondly, the J-V characteristic curves of semiconductor material are discussed in this paper. In order to achieve the current-voltage characteristic for specific junction field effect transistor, numerical values of each parameter which are included in analysis are defined and then these resultant values are predicted for the performance of junction field effect transistors. The computerized analyses have also mentioned in this paper.

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Perez, S., A. M. Francis, J. Holmes, and T. Vrotsos. "Silicon Carbide Junction Field Effect Transistor Compact Model for Extreme Environment Integrated Circuit Design." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2021, HiTEC (April 1, 2021): 000118–22. http://dx.doi.org/10.4071/2380-4491.2021.hitec.000118.

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Abstract Presented is a temperature and geometry scalable 800°C Silicon Carbide (SiC) Junction Field Effect Transistor (JFET) compact device model designed to simulate the small signal effects of the SiC JFET-R process developed by NASA Glenn Research Center. With the JFET-R process pushing the temperature limits of integrated circuits, a high-fidelity device model capable of predicting the performance over temperature and geometry is required to realize the thermal ruggedness this process provides. A high temperature (HT) packaging system was utilized to characterize a SiC JFET device up to 800°C with a dwell time of 9 hours during a single test. Invaluable device characterization data was obtained and utilized to extend the device model presented to simulate SiC JFET performance continuously over 800°C.

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Kaneko, Mitsuaki, Ulrike Grossner, and Tsunenobu Kimoto. "SiC Vertical-Channel n- and p-JFETs Fully Fabricated by Ion Implantation." Materials Science Forum 963 (July 2019): 841–44. http://dx.doi.org/10.4028/www.scientific.net/msf.963.841.

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Silicon carbide (SiC) n-and p-channel junction field effect transistors (JFETs) with vertical channels were fabricated by direct ion implantation into a high-purity semi-insulating 4H-SiC substrate in order to further develop the path towards complementary JFET integrated circuits for applications in harsh environments. Compared with the conventional structure (lateral channel), the proposed structure is suitable for integration and inherently has a high transconductance owing to the double-gate configuration. The threshold voltage (Vth) can be controlled by mask design, while Vth in the conventional structure is solely determined by the ion implantation conditions. We demonstrate the transistor operation of the vertical-channel n-and p-channel JFETs fully fabricated by ion implantation.

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Casady, Jeff B., David C. Sheridan, Robin L. Kelley, Volodymyr Bondarenko, and Andrew Ritenour. "A Comparison of 1200 V Normally-OFF & Normally-on Vertical Trench SiC Power JFET Devices." Materials Science Forum 679-680 (March 2011): 641–44. http://dx.doi.org/10.4028/www.scientific.net/msf.679-680.641.

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Equivalent sized (4.5 mm2 die area), 1200 V, 4H-SiC, vertical trench Junction Field Effect Transistors (JFETs) were characterized in terms of DC and switching performance. The 100 mΩ Enhancement-Mode (EM) JFET was found to have natural advantages in safe operation being normally-off, whereas the Depletion-Mode (DM) JFET was found to have advantages with ~ twice as high saturation current, less on-resistance (85 mΩ) and no gate current required in the on-state. The JFETs were found to both have radically less (five to ten times) switching energies than corresponding 1200 V Si transistors, with the DM JFET and EM JFET having EON and EOFF of only 115 µJ and 173 µJ, respectively when tested at half-rated voltage (600 V) and 12 A.

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Akiyama, Satoru, Haruka Shimizu, Natsuki Yokoyama, Tomohiro Tamaki, Sadayuki Koido, Yoshikazu Tomizawa, Toyohiko Takahashi, and Takamitsu Kanazawa. "A 69-mΩ 600-V-Class Hybrid JFET." Materials Science Forum 740-742 (January 2013): 925–28. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.925.

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A hybrid silicon-carbide junction-gate field-effect transistor (HJT: hybrid JFET) is proposed. The HJT consists of a silicon-carbide (SiC) normally-on vertical JFET and a low-voltage normally-off silicon metal-oxide-semiconductor field-effect transistor (Si-MOS: silicon MOSFET). These two devices are connected by bonding wire as a cascode circuit [1] and packaged in a TO-3P split-lead-frame package with the same pin arrangement as conventional silicon power devices, which can thus be easily replaced by the proposed HJT. The vertical JFET has a steep-junction deep-trench structure in its channel region. This structure gives a low on-state resistance of under 60 mΩ and breakdown voltage of over 600 V with the die size of 6.25 mm2. Since the deep-trench structure also lowers the cutoff voltage of the JFET, required minimum breakdown voltage of the Si-MOS is reduced and on-state resistance of the Si-MOS is lowered. The HJT demonstrated on-state resistance of 69 mΩ and breakdown voltage of 783 V. These results indicate that the proposed HJT is a strong candidate for low-resistance high-power switching devices.

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Steiner, B., S. B. Bayne, Victor Veliadis, H. C. Ha, D. Urciuoli, N. El Hinnawy, P. Borodulin, and C. Scozzie. "Reliable Operation of SiC Junction-Field-Effect-Transistor Subjected to over 2 Million 600-V Hard Switch Stressing Events." Materials Science Forum 740-742 (January 2013): 921–24. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.921.

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A necessity for the successful commercialization of SiC power devices is their long term reliability under the switching conditions encountered in the field. Normally-ON 1200 V SiC JFETs were stressed in repetitive hard-switching conditions to determine their fault handling capabilities. The switching pulses were generated from an RLC circuit, where energy initially stored in capacitors discharges through the JFET into a resistive load. The hard-switching included one million repetitive pulsed hard-switching events at 25 °C from a drain blocking-voltage of 600-V to an on-state current of 67 A, and an additional one million 600-V/63-A pulsed hard-switching events at 150 °C. The JFET conduction and blocking-voltage characteristics are virtually unchanged after over two million hard switching events proving the devices are reliable for handling high surge-current faults like those encountered in bidirectional circuit breaker applications.°

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Neudeck, Philip G., David J. Spry, Michael J. Krasowski, Norman F. Prokop, Glenn M. Beheim, Liang-Yu Chen, and Carl W. Chang. "Yearlong 500 °C Operational Demonstration of Up-scaled 4H-SiC JFET Integrated Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2018, HiTEC (May 1, 2018): 000071–78. http://dx.doi.org/10.4071/2380-4491-2018-hiten-000071.

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Abstract This work describes recent progress in the design, processing, and testing of significantly up-scaled 500 °C durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for over one year at 500 °C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500 °C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016 [1]. These results advance the technology foundation for realizing long-term durable 500 °C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.

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Neudeck, Philip G., David J. Spry, Michael J. Krasowski, Norman F. Prokop, Glenn M. Beheim, Liang-Yu Chen, and Carl W. Chang. "Year-long 500°C Operational Demonstration of Up-scaled 4H-SiC JFET Integrated Circuits." Journal of Microelectronics and Electronic Packaging 15, no. 4 (October 1, 2018): 163–70. http://dx.doi.org/10.4071/imaps.729648.

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Abstract This work describes recent progress in the design, processing, and testing of significantly up-scaled complex 500°C–durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for more than 1 y at 500°C in an air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500°C–durable circuit complexity from the 24-transistor ring oscillator ICs reported at HiTEC 2016. These results advance the technology foundation for realizing long-term durable 500°C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.

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Malhan, Rajesh Kumar, S. J. Rashid, Mitsuhiro Kataoka, Yuuichi Takeuchi, Naohiro Sugiyama, F. Udrea, G. A. J. Amaratunga, and T. Reimann. "Switching Performance of Epitaxially Grown Normally-Off 4H-SiC JFET." Materials Science Forum 600-603 (September 2008): 1067–70. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.1067.

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Static and dynamic behavior of the epitaxially grown dual gate trench 4H-SiC junction field effect transistor (JFET) is investigated. Typical on-state resistance Ron was 6 – 10mΩcm2 at VGS = 2.5V and the breakdown voltage between the range of 1.5 – 1.8kV was realized at VGS = −5V for normally-off like JFETs. It was found that the turn-on energy delivers the biggest part of the switching losses. The dependence of switching losses from gate resistor is nearly linear, suggesting that changing the gate resistor, a way similar to Si-IGBT technology, can easily control di/dt and dv/dt. Turn-on losses at 200°C are lower compared to those at 25°C, which indicates the influence of the high internal p-type gate layer resistance. Inductive switching numerical analysis suggested the strong influence of channel doping conditions on the turn-on switching performance. The fast switching normally-off JFET devices require heavily doped narrow JFET channel design.

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Hinojosa, Miguel, Stephen Bayne, Victor Veliadis, and Damian Urciuoli. "Avalanche Breakdown Energy in Silicon Carbide Junction Field Effect Transistors." Materials Science Forum 717-720 (May 2012): 1025–28. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1025.

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The energy dissipation capabilities of a 1200 V, 0.1 cm2 JFET operating in blocking mode were investigated. These devices, which are used in bidirectional circuit breaker applications, can conduct a current of 13 A in forward-conduction mode, and typically block a voltage up to 1200 V in blocking mode. In this document, the blocking limits of the device were pushed slightly to the point where avalanche breakdown occurs. A high voltage pulse generator was designed and constructed to drive the JFET into this state and to monitor the dissipated energy. The devices were able to handle up to 18.14 mJ.

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Neudeck, Philip G., Norman F. Prokop, Lawrence C. Greer III, Liang Yu Chen, and Michael J. Krasowski. "Low Earth Orbit Space Environment Testing of Extreme Temperature 6H-SiC JFETs on the International Space Station." Materials Science Forum 679-680 (March 2011): 579–82. http://dx.doi.org/10.4028/www.scientific.net/msf.679-680.579.

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This paper reports long-term electrical results from two 6H-SiC junction field effect transistors (JFETs) presently being tested in Low Earth Orbit (LEO) space environment on the outside of the International Space Station (ISS). The JFETs have demonstrated excellent functionality and stability through 4600 hours of LEO space deployment. Observed changes in measured device characteristics tracked changes in measured temperature, consistent with well-known JFET temperature-dependent device physics.

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Lawson, Kevin, G. Alvarez, S. B. Bayne, Victor Veliadis, H. C. Ha, Damian Urciuoli, and C. Scozzie. "Reliable Operation of 1200-V SiC Vertical Junction-Field-Effect-Transistor Subjected to 16,000-Pulse Hard Switching Stressing." Materials Science Forum 717-720 (May 2012): 1021–24. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1021.

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A necessity for the successful commercialization of SiC power devices is their long term reliability under the switching conditions encountered in application. Normally-ON 1200 V SiC JFETs were stressed in hard-switching conditions to determine their fault handling capabilities. The hard-switching included single shot tests ranging from drain voltages of 100 V to 500 V and repetition rate tests at 1 Hz, 5 Hz, 10 Hz, and 100 Hz with peak currents exceeding 100 A (8 times the rated current at 250 W/cm22). The JFET conduction and blocking-voltage characteristics are unchanged after 4,000 pulsed and numerous single shot hard switching events proving the devices are reliable for handling high surge-current faults.

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Shimizu, Haruka, Yasuo Onose, Tomoyuki Someya, Hidekatsu Onose, and Natsuki Yokoyama. "Normally-Off 4H-SiC Vertical JFET with Large Current Density." Materials Science Forum 600-603 (September 2008): 1059–62. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.1059.

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We developed normally-off 4H-SiC vertical junction field effect transistors (JFETs) with large current density. The effect of forming an abrupt junction between the gate and the channel was simulated, and vertical JFETs were then fabricated with abrupt junctions. As a result, a large rated drain current density (500 A/cm2) and a low specific on-resistance (2.0 mWcm2) were achieved for small devices. The blocking voltage was 600 V. These results were due to a reduction of the threshold voltage by forming the abrupt junction between the gate and the channel.

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Fu, Xiao An, Amita Patil, Philip G. Neudeck, Glenn M. Beheim, Steven Garverick, and Mehran Mehregany. "6H-SiC Lateral JFETs for Analog Integrated Circuits." Materials Science Forum 600-603 (September 2008): 1099–102. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.1099.

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This paper reports fabrication and electrical characterization of 6H-SiC n-channel, depletion-mode, junction-field-effect transistors (JFETs) for use in high-temperature analog integrated circuits for sensing and control in propulsion, power systems, and geothermal exploration. Electrical characteristics of the resulting JFET devices have been measured across the wafer as a function of temperature, from room temperature to 450oC. The results indicate that the JFETs are suitable for high-gain amplifiers in high-temperature sensor signal processing circuits.

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Fu, Xiao An, Amita Patil, Te Hao Lee, Steven Garverick, and Mehran Mehregany. "Fabrication of SiC JFET-Based Monolithic Integrated Circuits." Materials Science Forum 645-648 (April 2010): 1115–18. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.1115.

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We report fabrication of lateral, n-channel, depletion-mode, junction-field-effect-transistor (JFET) monolithic analog integrated circuits (ICs) in 6H-SiC. Ti/TaSi2/Pt forms the contact metalization, Ti/Pt the interconnect metal, and the SiO2/Si3N4/SiO2 interlayer dielectric. The threshold voltage and pinch off current indicate that the actual channel doping and thickness is close to the nominal values specified. The wafer yield for good circuits of a single-stage differential amplifier is 54% out of 46 copies.

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Spry, David J., Philip G. Neudeck, Dorothy Lukco, Liang Yu Chen, Michael J. Krasowski, Norman F. Prokop, Carl W. Chang, and Glenn M. Beheim. "Prolonged 500°C Operation of 100+ Transistor Silicon Carbide Integrated Circuits." Materials Science Forum 924 (June 2018): 949–52. http://dx.doi.org/10.4028/www.scientific.net/msf.924.949.

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This report describes more than 5000 hours of successful 500 °C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 °C. After 100 hours of 500 °C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 °C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460 °C in comparison to what is observed for Earth-atmosphere oven testing at 500 °C.

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Veliadis, Victor, Harold Hearne, W. Chang, Joshua D. Caldwell, Eric J. Stewart, Megan Snook, R. S. Howell, Damian Urciuoli, Aivars J. Lelis, and C. Scozzie. "Recovery of Bipolar-Current Induced Degradations in High-Voltage Implanted-Gate Junction Field Effect Transistors." Materials Science Forum 717-720 (May 2012): 1013–16. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1013.

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Electron-hole recombination-induced stacking faults have been shown to degrade the electrical characteristics of SiC power pin and MPS diodes and DMOSFETs with thick drift epitaxial layers. In this paper, we investigate the effects of bipolar injection induced stacking faults on the electrical characteristics of p+ ion-implanted high-voltage vertical-channel JFETs with 100-μm drift epilayers. The JFETs were stressed at a fixed gate-drain bipolar current density of 100 A/cm2 for five hours, which led to degradation of the forward gate-drain p-n junction and on-state conduction. The degradation was fully reversed by annealing at 350 °C for 96 hours. Forward and reverse gate-source, transfer, reverse gate-drain, and blocking voltage JFET characteristics exhibit no degradation with bipolar stress. Non-degraded characteristics remain unaffected by annealing events. Consequently, should minority carrier injection occur in JFETs operating at elevated temperatures no stacking fault induced degradations are expected. This eliminates the need for specialty substrates with suppressed densities of basal plane dislocations in the fabrication of high-voltage SiC JFETs for high temperature applications.

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Akiyama, Satoru, Kaoru Katoh, Haruka Shimizu, Ayumu Hatanaka, Takashi Ogawa, Natsuki Yokoyama, and Katsumi Ishikawa. "Gate-Drive Voltage Design for 600-V Vertical-Trench Normally-Off SiC JFETs toward 94% Efficiency Server Power Supply." Materials Science Forum 778-780 (February 2014): 875–78. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.875.

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A gate-drive voltage for a normally-off silicon-carbide vertical-trench junction-gate field-effect transistor (JFET) was designed for a server power supply with 94% efficiency. Since the on-state resistance of the JFET is strongly depends on the gate voltage and a large gate-leakage current between the gate electrode and source flows by applying an excessively high-gate voltage, we therefore must set an adequate turn-on gate-drive voltage to suppress the increase in power loss. The optimum gate-drive voltage design was estimated to be 2.1 V, resulting in a high efficiency of 94% even with a gate-drive voltage variation of ±0.3 V.

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Neudeck, Philip G., David J. Spry, Michael J. Krasowski, Liangyu Chen, Lawrence C. Greer, Carl W. Chang, Dorothy Lukco, Glenn M. Beheim, and Norman F. Prokop. "Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2021, HiTEC (April 1, 2021): 000064–68. http://dx.doi.org/10.4071/2380-4491.2021.hitec.000064.

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Abstract At HiTEC 2018, NASA Glenn Research Center reported the first demonstration of yearlong 500 °C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021 submission updates on-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11 and near 3000 transistors/chip for Gen. 12 are made possible by reductions in minimum layout feature sizes (including resistor width shrinkage from 6 μm to 2 μm) coupled with enlarged die size (from 3 × 3 mm to 5 × 5 mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM) and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequent Gen. 12 fabrication run currently in progress.

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Neudeck, Philip G., David J. Spry, and Liang-Yu Chen. "First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (January 1, 2016): 000263–71. http://dx.doi.org/10.4071/2016-hitec-263.

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Abstract A separate submission to this conference reports that 4H-SiC Junction Field Effect Transistor (JFET) digital and analog Integrated Circuits (ICs) with two levels of metal interconnect have reproducibly demonstrated electrical operation at 500 °C in excess of 1000 hours. While this progress expands the complexity and durability envelope of high temperature ICs, one important area for further technology maturation is the development of reasonably accurate and accessible computer-aided modeling and simulation tools for circuit design of these ICs. Towards this end, we report on development and verification of 25 °C to 500 °C SPICE simulation models of first-order accuracy for this extreme-temperature durable 4H-SiC JFET IC technology. For maximum availability, the JFET IC modeling is implemented using the baseline-version SPICE NMOS LEVEL 1 model that is common to other variations of SPICE software and importantly includes the body-bias effect. The first-order accuracy of these device models is verified by direct comparison with measured experimental device characteristics.

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Spry, David J., Philip G. Neudeck, Liang Yu Chen, Glenn M. Beheim, Robert S. Okojie, Carl W. Chang, Roger D. Meredith, Terry L. Ferrier, and Laura J. Evans. "Fabrication and Testing of 6H-SiC JFETs for Prolonged 500 °C Operation in Air Ambient." Materials Science Forum 600-603 (September 2008): 1079–82. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.1079.

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This paper reports on the fabrication and testing of 6H-SiC junction field effect transistors (JFETs) and a simple differential amplifier integrated circuit that have demonstrated 2000 hours of electrical operation at 500 °C without degradation. The high-temperature ohmic contacts, dielectric passivation, and packaging technology that enabled such 500 °C durability are briefly described. Key JFET parameters of threshold voltage, on-state resistance, transconductance, and on-state current, as well as the gain of the differential amplifier integrated circuit, exhibited less than 7% change over the first 2000 hours of 500 °C operational testing.

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Flicker, Jack, David Hughart, Robert Kaplar, Stanley Atcitty, and Matthew Marinella. "Performance and Reliability Characterization of 1200 V Silicon Carbide Power MOSFETs and JFETs at High Temperatures." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000228–34. http://dx.doi.org/10.4071/hitec-wp16.

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1200 V Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) and Junction Field Effect Transistors (JFETs) have been characterized at high operational temperatures. For packaged JFETs obtained from a collaborating manufacturer, the threshold shift (ΔVT) was measured under both static and dynamic voltage stress and, in all cases, was less than 2 mV, which is within the measurement margin of error. Temperatures up to 250°C and stress times as long as 200 hours were evaluated. As a comparison, commercially available SiC MOSFETs demonstrated shifts of up to 300 mV after 30 minutes of static gate stress at 175°C. In addition, results from unpackaged JFET die at temperatures up to 525°C show ΔVT values of less than 10 mV for all stress conditions. Although VT remained unchanged for the duration of the test for both static and dynamic stress conditions, under dynamic stress conditions the JFET packaged parts demonstrated a linear increase in sub-threshold leakage current of around 15.6 nA per hour; in contrast, the MOSFET devices showed an exponential increase in sub-threshold leakage under dynamic stress. The increase in sub-threshold leakage current could be recovered temporarily, but long-term behavior was consistent with cumulative damage.

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Speer, Kevin M., Kiran Chatty, Volodymyr Bondarenko, David C. Sheridan, Kevin Matocha, and Jeff B. Casady. "Demonstration of SiC Vertical Trench JFET Reliability." Materials Science Forum 717-720 (May 2012): 1017–20. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1017.

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This paper demonstrates the reliability of SiC vertical trench junction field-effect transistors (VJFET). Measurements are shown which prove that the device’s intrinsic gate-source pn junction is immune to degradation associated with recombination-enhanced dislocation glide. And after subjecting VJFETs to 1,000 hours of high-temperature bias stress, no measured parameter deviated from datasheet specifications. These results reflect the maturity and reliability of SemiSouth’s SiC VJFET technology, as well as tight process control over device parameters that are critical to circuit design and long-term system operation.

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Neudeck, Philip G., David J. Spry, Liang Yu Chen, Dorothy Lukco, Carl W. Chang, and Glenn M. Beheim. "Experimentally Observed Electrical Durability of 4H-SiC JFET ICs Operating from 500 °C to 700 °C." Materials Science Forum 897 (May 2017): 567–70. http://dx.doi.org/10.4028/www.scientific.net/msf.897.567.

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Prolonged 500 °C to 700 °C electrical testing data from 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) are combined with post-testing microscopic studies in order to gain more comprehensive understanding of the durability limits of the present version of NASA Glenn's extreme temperature microelectronics technology. The results of this study support the hypothesis that T ≥ 500 °C durability-limiting IC failure initiates with thermal stress-related crack formation where dielectric passivation layers overcoat micron-scale vertical features including patterned metal traces.

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Chen, Gang, Xiao Feng Song, Song Bai, Li Li, Yun Li, Zheng Chen, and Wen Wang. "5A 1300V Trenched and Implanted 4H-SiC Vertical JFET." Applied Mechanics and Materials 229-231 (November 2012): 824–27. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.824.

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A silicon carbide (SiC) vertical channel junction field effect transistor (VJFET) was fabricated based on in-house SiC epitaxial wafer with lift-off trenched and implanted method. Its blocking voltage exceeds 1300V at gate bias VG = -6V and forward drain current is in excess of 5A at gate bias VG = 3V and drain bias VD = 3V. The SiC VJFET device’s current density is 240A/cm2 at VG= 3V and VD = 3V, with related specific on-resistance 8.9mΩ•cm2. Further analysis reveals that the on-resistance depends greatly on ohmic contact resistance and the bonding spun gold. The specific on-resistance can be further reduced by improving the doping concentration of SiC channel epilayer and the device’s ohmic contact.

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Tamaki, Tomohiro, Shinya Ishida, Yoshikazu Tomizawa, Hiroyuki Nakamura, Yasuhiro Shirai, Satoru Akiyama, Haruka Shimizu, and Natsuki Yokoyama. "On-State and Switching Performance Comparison of A 600 V-Class Hybrid SiC JFET and Si Superjunction MOSFETs." Materials Science Forum 740-742 (January 2013): 950–53. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.950.

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We compare the on-state and switching performance of a 600 V-class Hybrid SiC junction field effect transistor (HJT) and Si superjunction MOSFETs (SJ-MOSs), both of which are packaged in TO-3P full-mold package, as a function of operating frequency. The maximum load current is limited by the package power dissipation rating determined by the maximum junction temperature. Since the HJT is composed of a SiC JFET and a low voltage Si MOSFET, the allowable maximum junction temperature of the HJT is the same as that of SJ-MOSFETs, namely 150 °C. The experimental results show that the maximum operating current of the HJT is comparable to that of SJ-MOSs, but the EMI noise of the HJT is much suppressed due to lower dV/dt.

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Zhang, L., L. F. Lester, A. G. Baca, R. J. Shul, P. C. Chang, C. G. Willison, U. K. Mishra, S. P. Denbaars, and J. C. Zolper. "Fabrication and Characterization of GaN Junctionfield Effect Transistors." MRS Internet Journal of Nitride Semiconductor Research 5, S1 (2000): 376–83. http://dx.doi.org/10.1557/s1092578300004531.

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Junction field effect transistors (JFET) were fabricated on a GaN epitaxial structure grown by metal organic chemical vapor deposition. The DC and microwave characteristics, as well as the high temperature performance of the devices were studied. These devices exhibited excellent pinch-off and a breakdown voltage that agreed with theoretical predictions. An extrinsic transconductance (gm) of 48 mS/mm was obtained with a maximum drain current (ID) of 270 mA/mm. The microwave measurement showed an fT of 6 GHz and an fmax of 12 GHz. Both the ID and the gm were found to decrease with increasing temperature, possibly due to lower electron mobility at elevated temperatures. These JFETs exhibited a significant current reduction after a high drain bias was applied, which was attributed to a partially depleted channel caused by trapped electrons in the semi-insulating GaN buffer layer.

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Spry, David J., Philip G. Neudeck, Liang Yu Chen, Laura J. Evans, Dorothy Lukco, Carl W. Chang, and Glenn M. Beheim. "Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect." Materials Science Forum 858 (May 2016): 1112–16. http://dx.doi.org/10.4028/www.scientific.net/msf.858.1112.

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The fabrication and prolonged 500 °C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 °C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 °C operating time. Evidence is presented for four distinct issues that significantly impacted 500 °C IC operational yield and lifetime for this wafer.

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Spry, David J., Philip G. Neudeck, Liang Yu Chen, Dorothy Lukco, Carl W. Chang, Glenn M. Beheim, Michael J. Krasowski, and Norman F. Prokop. "Processing and Prolonged 500 °C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect." Materials Science Forum 858 (May 2016): 908–12. http://dx.doi.org/10.4028/www.scientific.net/msf.858.908.

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Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC’s with two levels of metal interconnect capable of prolonged operation at 500 °C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 °C. A 3-stage oscillator functioned for over 3000 hours at 500 °C in air ambient. Improved reproducibility remains to be accomplished.

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Elwakil, A. S., and A. M. Soliman. "Two Modified for Chaos Negative Impedance Converter Op Amp Oscillators with Symmetrical and Antisymmetrical Nonlinearities." International Journal of Bifurcation and Chaos 08, no. 06 (June 1998): 1335–46. http://dx.doi.org/10.1142/s0218127498001030.

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Two sinusoidal oscillator circuits, that employ an operational amplifier (op amp) as a current negative impedance converter (CNIC), are modified for chaos using a nonlinear resistor of anti-symmetrical current-voltage characteristics formed by a junction field effect transistor (JFET) operating in the triode region. The internal op amp dominant pole is found to contribute significantly to the chaotic nature of one circuit while the other circuit develops different chaotic attractors when cubic and fifth power odd symmetrical nonlinearities are used. Mathematical models of the two generators are presented. Experimental laboratory results, circuit simulations and numerical simulations of the mathematical models well agree and are included.

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Li, Shuxia, N. Garry Tarr, and Winnie N. Ye. "JFET Integration Using a Foundry SOI Photonics Platform." Applied Sciences 9, no. 19 (September 21, 2019): 3964. http://dx.doi.org/10.3390/app9193964.

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We explore the monolithic integration of conventional electronics with SOI photonics using the commercial silicon photonics foundry technology offered by A*STAR’s Institute of Microelectronics (IME). This process offers optical waveguide modulators and photodetectors, but was not intended to support transistors. We present the implementation of junction field effect transistors (JFETs) integrated with optical waveguides and photodetectors. A simple SPICE model is developed for the JFETs based on the available ion implant parameters, and the geometry feature size allowed by the technology’s layout rules. We have demonstrated the monolithic integration of photonics and electronics circuits. This work could be useful for application in waveguide sensors and optical telecommunications.

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Spry, David J., Philip G. Neudeck, Liang-Yu Chen, Dorothy Lukco, Carl W. Chang, Glenn M. Beheim, Michael J. Krasowski, and Norman F. Prokop. "Processing and Characterization of Thousand-Hour 500 °C Durable 4H-SiC JFET Integrated Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (January 1, 2016): 000249–56. http://dx.doi.org/10.4071/2016-hitec-249.

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Abstract This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 °C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over ~ 1-μm scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 °C operational testing. These results advance the technology foundation for realizing long-term durable 500 °C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

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Neudeck, Philip G., David J. Spry, Liang Yu Chen, Carl W. Chang, Glenn M. Beheim, Robert S. Okojie, Laura J. Evans, et al. "Prolonged 500 °C Operation of 6H-SiC JFET Integrated Circuitry." Materials Science Forum 615-617 (March 2009): 929–32. http://dx.doi.org/10.4028/www.scientific.net/msf.615-617.929.

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This paper updates the long-term 500 °C electrical testing results from 6H-SiC junction field effect transistors (JFETs) and small integrated circuits that were introduced at ICSCRM-2007. Two packaged JFETs have now been operated in excess of 7000 hours at 500 °C with less than 10% degradation in linear I-V characteristics. Several simple digital and analog demonstration integrated circuits successfully operated for 2000-6500 hours at 500 °C before failure.

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Sugiyama, Naohiro, Yuuichi Takeuchi, Mitsuhiro Kataoka, Adolf Schöner, and Rajesh Kumar Malhan. "Growth Mechanism and 2D Aluminum Dopant Distribution of Embedded Trench 4H-SiC Region." Materials Science Forum 600-603 (September 2008): 171–74. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.171.

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The migration enhanced embedded epitaxy (ME3) mechanism and 2D dopant distribution of the embedded trench region is investigated with the aim to realize the all-epitaxial, normally-off junction field effect transistor (JFET). We found that the embedded growth consists of two main components. First one is the direct supply without gas scattering and the other one is the surface migration supply via the trench opening edge, which dominate the ME3 process. An inhomogeneous 2D distribution of Aluminum (Al) concentration was revealed for the first time in the 4H-SiC embedded trench regions by the combined analysis of secondary ion mass spectrometry (SIMS) and scanning spreading resistance microscopy (SSRM) results. The maximum variation of Al concentration in the trench is estimated to be about 4-times, which suggests that the Al concentration is highest for the (0001) plane and lowest for the trench corner (1-10x) plane. Al concentration in the (1-100) plane, which determines the JFET p-gate doping level is 1.5-times lower than (0001) plane for trench region fabricated on Si-face wafers.

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Kelley, Robin L., T. Brignac, Michael S. Mazzola, and Jeff B. Casady. "Inherently Safe Resonant Reset Forward Converter Using a Bias-Enhanced SiC JFET." Materials Science Forum 527-529 (October 2006): 1211–14. http://dx.doi.org/10.4028/www.scientific.net/msf.527-529.1211.

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The power junction field effect transistor (JFET) is the second most mature SiC device, after the SiC Schottky diode, and is commonly associated with normally on functionality; but this feature is often viewed problematically for off-line dc-to-dc converter applications. Two inherently safe, single-switch dc-dc converter designs have been developed that put into practice pure SiC JFET devices (i.e., without cascoded devices) that possess enhancement-mode functionality and bias-enhanced blocking. These ‘Quasi-Off’ devices are designed to block half of the rated blocking voltage at zero gate bias and achieve full rated blocking voltage with a modest negative bias, typically between 0 and -5 V. Inherent safety is provided by utilizing the enhancement mode functionality of these devices as well as appropriate gate driver design. Bias enhanced blocking matches the dynamic stress encountered by modern high-frequency power supply topologies to the ratings of the device while recognizing that the larger dynamic stress is typically encountered only when the power supply (and especially the gate driver) is functioning properly.

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Bertilsson, Kent, and Chris I. Harris. "Comparison of Bipolar and Unipolar SiC Switching Devices for Very High Power Applications." Materials Science Forum 556-557 (September 2007): 975–78. http://dx.doi.org/10.4028/www.scientific.net/msf.556-557.975.

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Both unipolar and injection SiC devices can be used for high voltage switching applications; it is not determined, however, for which applications one approach is preferred over the other. In this paper, simulation studies are used to compare the suitability of unipolar devices, in this case a JFET (Junction Field Effect Transistor) against an equivalent FCD (Field Controlled Diode) configuration up to very high voltages. The calculations are performed in a finite element approach, with commercial drift-diffusion software. Numerous drift layers have been simulated in a Monte-Carlo approach to ensure that the optimal design of the drift layers for different breakdown is used. In a static case, purely conductive losses in the drift layer in both unipolar and injection configuration are compared. Additionally the total losses are studied and compared in switched applications for different switching frequencies and current levels.

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Li, Yu Zhu, Petre Alexandrov, Jian Hui Zhang, Larry X. Li, and Jian Hui Zhao. "10 kV, 87 mΩcm² Normally-Off 4H-SiC Vertical Junction Field-Effect Transistors." Materials Science Forum 527-529 (October 2006): 1187–90. http://dx.doi.org/10.4028/www.scientific.net/msf.527-529.1187.

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SiC JFET, compared with SiC MOSFET, is attractive for high power, high temperature applications because it is free of gate oxide reliability issues. Trenched-and-Implanted VJFET (TIVJFET) does not require epi-regrowth and is capable of high current density. In this work we demonstrate two trenched-and-implanted normally-off 4H-SiC vertical junction field-effect transistors (TI-VJFET), based on 120μm, 4.9×1014cm-3 and 100μm, 6×1014cm-3 drift layers. The corresponding devices showed blocking voltage (VB) of 11.1kV and specific on-resistance (RSP_ON) of 124m7cm2, and VB of 10kV and RSP_ON of 87m7cm2. A record-high value for VB 2/RSP_ON of 1149MW/cm2 was achieved for normally-off SiC FETs.

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Koyama, Akihiro, Yuji Kiuchi, Tomonori Mizushima, Kensuke Takenaka, Shinichiro Matsunaga, Mitsuru Sometani, Koji Nakayama, et al. "20 kV-Class Ultra-High Voltage 4H-SiC n-IE-IGBTs." Materials Science Forum 1004 (July 2020): 899–904. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.899.

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We demonstrate 20 kV-class 4H-SiC n-channel implantation and epitaxial (IE)-IGBTs having both low on-state voltage and high blocking characteristics. We fabricated n-IE-IGBTs on a (0001) silicon face with free-standing epitaxial layers. Effective carrier lifetime increased significantly from 0.9 μs to 9.6 μs by a lifetime enhancement process. We used the IE structure to suppress an increase of the surface p+-well concentration, reduce implantation damage at the p+-well, and reduce junction field effect transistor (JFET) region resistance by ion implantation as a counter doping. The n-IE-IGBT at 100 A/cm2 on-state voltage and specific differential on-resistance was 8.2 V and 36.9 mΩcm2, respectively, at room temperature with a 30 V gate voltage. The blocking voltage was 26.8 kV at 45.7 μA.

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Spry, David J., Philip G. Neudeck, and Carl W. Chang. "Experimental Study on Mitigation of Lifetime-Limiting Dielectric Cracking in Extreme Temperature 4H-SiC JFET Integrated Circuits." Materials Science Forum 1004 (July 2020): 1148–55. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.1148.

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While NASA Glenn Research Center’s “Generation 10” 4H-SiC Junction Field Effect Transistor (JFET) integrated circuits (ICs) have uniquely demonstrated 500 °C electrical operation for durations of over a year, this experimental work has also revealed that physical cracking of chip dielectric passivation layers ultimately limits extreme-environment operating lifetime [1-3]. The prevention of such dielectric passivation cracks should therefore improve IC high temperature durability and yield, leading to more beneficial technology adoption into aerospace, automotive, and energy systems. This report describes Generation 10.2, 11.1, and 11.2 die tested under unbiased and unpackaged accelerated age testing at 500 °C, 600 °C, 720 °C, and 800 °C in air-atmosphere ovens for 100-and 200-hour duration. Additional samples were separately subjected to 10 thermal cycles between the same high temperatures (with 10-hour high-temperature soak each cycle) and 50 °C. It is shown that having two stoichiometric Si3N4 layers in the interconnect dielectric stack substantially decreases the amount of dielectric cracking observed following these oven tests.

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Wang, Lina, Junyi Yang, Haobo Ma, Zeyuan Wang, Kabir Olanrewaju, and Kamel Kerrouche. "Analysis and Suppression of Unwanted Turn-On and Parasitic Oscillation in SiC JFET-Based Bi-Directional Switches." Electronics 7, no. 8 (July 24, 2018): 126. http://dx.doi.org/10.3390/electronics7080126.

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Silicon Carbide (SiC)-based Bi-Directional Switches (BDS) have great potential in the construction of several power electronic circuits including multi-level converters, solid-state breakers, matrix converters, HERIC (high efficient and reliable inverter concept) photovoltaic grid-connected inverters and so on. In this paper, two issues with the application of SiC-based BDSs, namely, unwanted turn-on and parasitic oscillation, are deeply investigated. To eliminate unwanted turn-on, it is proposed to add a capacitor (CX) paralleled at the signal input port of the driver IC (integrated circuit) and the capacitance range of CX is also analytically derived to guide the selection of CX. To mitigate parasitic oscillation, a combinational method, which combines a snubber capacitor (CJ) paralleled with the JFET (Junction Field Effect Transistor) and a ferrite ring connected in series with the power line, is proposed. It is verified that the use of CJ mainly improves the turn-off transient and the use of a ferrite ring damps the current oscillation during the turn-on transient significantly. The effects of the proposed methods have been demonstrated by theoretical analysis and verified by experimental results.

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Cha, Kyuhyun, Jongwoon Yoon, and Kwangsoo Kim. "3.3-kV 4H-SiC Split-Gate DMOSFET with Floating p+ Polysilicon for High-Frequency Applications." Electronics 10, no. 6 (March 11, 2021): 659. http://dx.doi.org/10.3390/electronics10060659.

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A split-gate metal–oxide–semiconductor field-effect transistor (SG-DMOSFET) is a well-known structure used for reducing the gate–drain capacitance (CGD) to improve switching characteristics. However, SG-DMOSFETs have problems such as the degradation of static characteristics and a high gate-oxide electric field. To solve these problems, we developed a SG-DMOSFET with floating p+ polysilicon (FPS-DMOSFET) and compared it with a conventional planar DMOSFET (C-DMOSFET) and a SG-DMOSFET through Technology Computer-Aided Design (TCAD) simulations. In the FPS-DMOSFET, floating p+ polysilicon (FPS) is inserted between the active gates to disperse the high drain voltage in the off state and form an accumulation layer over the entire junction field effect transistor (JFET) region, similar to a C-DMOSFET, in the on state. Therefore, the FPS-DMOSFET can minimize the degradation of static characteristics such as the breakdown voltage (BV) and specific on resistance (RON,SP) in the split-gate structure. Consequently, the FPS-DMOSFET can shorten the active gate length and achieve a gate-to-drain capacitance (CGD) that is less than those of the C-DMOSFET and SG-DMOSFET by 48% and 41%, respectively. Moreover, the high-frequency figure of merit (HF-FOM = RON,SP × CGD) of the FPS-DMOSFET is lower than those of the C-DMOSFET and SG-DMOSFET by 61% and 49%, respectively. In addition, the FPS-DMOSFET shows an EMOX of 2.1 MV/cm, which guarantees a gate oxide reliability limit of 3 MV/cm. Therefore, the proposed FPS-DMOSFET is the most appropriate device to be used in high-voltage and high-frequency electronic applications.

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Liu, Haitao, Kai Wei, Zhengzhou Li, Wengang Huang, Yi Xu, and Wei Cui. "A Novel, Hybrid-Integrated, High-Precision, Vacuum Microelectronic Accelerometer with Nano-Field Emission Tips." Micromachines 9, no. 10 (September 20, 2018): 481. http://dx.doi.org/10.3390/mi9100481.

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In this paper, a novel, hybrid-integrated, high-precision, vacuum microelectronic accelerometer is put forward, based on the theory of field emission; the accelerometer consists of a sensitive structure and an ASIC interface (application-specific integrated circuit). The sensitive structure has a cathode cone tip array, a folded beam, an emitter electrode, and a feedback electrode. The sensor is fabricated on a double-sided polished (1 0 0) N-type silicon wafer; the tip array of the cathode is shaped by wet etching with HNA (HNO3, HF, and CH3COOH) and metalized by TiW/Au thin film. The structure of the sensor is finally released by the ICP (inductively coupled plasma) process. The ASIC interface was designed and fabricated based on the P-JFET (Positive-Junction Field Effect Transistor) high-voltage bipolar process. The accelerometer was tested through a static field rollover test, and the test results show that the hybrid-integrated vacuum microelectronic accelerometer has good performance, with a sensitivity of 3.081 V/g, the non-linearity is 0.84% in the measuring range of −1 g~1 g, the average noise spectrum density value is 36.7 μV/ Hz in the frequency range of 0–200 Hz, the resolution of the vacuum microelectronic accelerometer can reach 1.1 × 10−5 g, and the zero stability reaches 0.18 mg in 24 h.

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Choi, Y. C., Ho Young Cha, Lester F. Eastman, and Michael G. Spencer. "Design Considerations of a New 4H-SiC Enhancement-Mode Lateral Channel Vertical JFET for Low-Loss Switching Operation." Materials Science Forum 527-529 (October 2006): 1199–202. http://dx.doi.org/10.4028/www.scientific.net/msf.527-529.1199.

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A new silicon carbide (SiC) enhancement-mode lateral channel vertical junction fieldeffect transistor (LC-VJFET), namely “source inserted double-gate structure (SID-gate) with a supplementary highly doped region (SHDR)”, was proposed for achieving extremely low power losses in high power switching applications. The proposed architecture was based on the combination of an additional source electrode inserted between two adjacent surface gate electrodes and a unique SHDR in the vertical channel region. Two-dimensional numerical simulations for the static and resistive switching characteristics were performed to analyze and optimize the SiC LCVJFET structures for this purpose. Based on the simulation results, the excellent performance of the proposed structure was compared with optimized conventional structures with regard to total power losses. Finally, the proposed structure showed about a 20 % reduction in on-state loss (Pon) compared to the conventional structures, due to the effective suppression of the JFET effect. Furthermore, the switching loss (Psw) of the proposed structure was found to be much lower than the results of the conventional structures, about a 75 % ~ 95 % reduction, by significantly reducing both input capacitance (Ciss) and reverse transfer capacitance (Crss) of the device.

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Achtenberg, Krzysztof, Janusz Mikołajczyk, Carmine Ciofi, Graziella Scandurra, and Zbigniew Bielecki. "Low-Noise Programmable Voltage Source." Electronics 9, no. 8 (August 2, 2020): 1245. http://dx.doi.org/10.3390/electronics9081245.

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Abstract:

This paper presents the design and testing of a low-noise programmable voltage source. Such a piece of instrumentation is often required as part of the measurement setup needed to test electronic devices without introducing noise from the power supply (such as photodetectors, resistors or transistors). Although its construction is based on known configurations, here the discussion is focused on the characterization and the minimization of the output noise, especially at very low frequencies. The design relies on a digital-to-analog converter, proper lowpass filters, and a low-noise Junction Field-Effect Transistors (JFET) based voltage follower. Because of the very low level of output noise, in some cases we had to resort to cross-correlation in order to reduce the background noise of the amplifiers used for the characterization of the programmable source. Indeed, when two paralleled IF9030 JFETs are used in the voltage follower, the output noise can be as low as 3 nV/√Hz, 0.6 nV/√Hz and 0.4 nV/√Hz at 1 Hz, 10 Hz and 100 Hz, respectively. The output voltage drift was also characterized and a stability of ±25 µV over 3 h was obtained. In order to better appreciate the performance of the low-noise voltage source that we have designed, its noise performances were compared with those of a set-up based on one of the best low-noise solid-state voltage regulators available on the market. Actual measurements of the current noise in a type-II superlattice photodetector are reported in which the programmable source was used to provide the voltage bias to the device.

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Journal articles on the topic 'Junction Field-Effect Transistor(JFET)'

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