Relevant bibliographies by topics / Kogge-Stone

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Kogge-Stone'

Author: Grafiati
Published: 4 June 2021
Last updated: 18 February 2022

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Journal articles on the topic "Kogge-Stone"

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Yagain, Deepa, Vijaya Krishna A, and Akansha Baliga. "Design of High-Speed Adders for Efficient Digital Design Blocks." ISRN Electronics 2012 (September 26, 2012): 1–9. http://dx.doi.org/10.5402/2012/253742.

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The core of every microprocessor and digital signal processor is its data path. The heart of data-path and addressing units in turn are arithmetic units which include adders. Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well suited for VLSI implementations. This paper involves the design and comparison of high-speed, parallel-prefix adders such as Kogge-Stone, Brent-Kung, Sklansky, and Kogge-Stone Ling adders. It is found that Kogge-Stone Ling adder performs much efficiently when compared to the other adders. Here, Kogge-Stone Ling adders and ripple adders are incorporated as a part of a lattice filter in order to prove their functionalities. It is seen that the operating frequency of lattice filter increases if parallel prefix Kogge-Stone Ling adder is used instead of ripple adders since the combinational delay of Kogge-Stone Ling adder is less. Further, design and comparison of different tree adder structures are performed using both CMOS logic and transmission gate logic. Using these adders, unsigned and signed comparators are designed as an application example and compared with their performance parameters such as area, delay, and power consumed. The design and simulations are done using 65 nm CMOS design library.
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BKondalkar, Mangesh, Arunkumar P Chavan, and P. Narashimaraja. "Improved Fault Tolerant Sparse KOGGE Stone ADDER." International Journal of Computer Applications 75, no. 10 (August 23, 2013): 36–41. http://dx.doi.org/10.5120/13150-0582.

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Nusullapalli, Rambabu, and Vaishnavi N. "DESIGN OF FFT ARCHITECTURE USING KOGGE STONE ADDER." International Journal of Advances in Signal and Image Sciences 4, no. 2 (December 28, 2018): 8. http://dx.doi.org/10.29284/ijasis.4.2.2018.8-15.

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A., Abinaya, and Maheswari M. "Implementation of Kogge Stone Adder for Signal Processing Applications." IJARCCE 8, no. 5 (May 30, 2019): 141–46. http://dx.doi.org/10.17148/ijarcce.2019.8528.

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Shapiro, Alexander E., Francois Atallah, Kyugseok Kim, Jihoon Jeong, Jeff Fischer, and Eby G. Friedman. "Adaptive power gating of 32-bit Kogge Stone adder." Integration 53 (March 2016): 80–87. http://dx.doi.org/10.1016/j.vlsi.2015.12.001.

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Naga Babu, Ch, P. Naga Siva Sai, Ch Priyanka, K. Hari Kishore, M. Bindu Bhargavi, and K. Karthik. "Comparative Analysis of High Speed Carry Skip Adders." International Journal of Engineering & Technology 7, no. 2.24 (April 25, 2018): 121. http://dx.doi.org/10.14419/ijet.v7i2.24.12015.

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In this paper we compared a high speed carry skip adders by considering parameters such as area, LUT’S, delay, power. When compared to conventional CSKA and other adders. Here in this project in first stage CSKA designed by using multiplexer as skip logic so by using this speed gets increased by skipping of carry. so here area gets increased so to reduce area another hybrid variable latency carry skip adder(Brent-kung adder) is designed .here power utilization also gets decreased, speed gets increased, but some delay is produced here to overcome that we followed a another method called Kogge-Stone adder here so it reduces the critical path delay. In Kogge-stone adder power is highly consumed due to more no of wiring connections so another adder was designed to reduce power consumption which is Sklansky adder which reduces power Consumption. This is done in Xilinx ISE 14.7 and power was analyzed using Xilinx power analyzer.
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Sindhuja, K. Aishwarya. "Implementation of Time Efficient VLSI Design using Kogge Stone Adder." International Journal for Research in Applied Science and Engineering Technology 8, no. 9 (September 30, 2020): 56–59. http://dx.doi.org/10.22214/ijraset.2020.31307.

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Mei Xiang, Lee, Muhammad Mun’im Ahmad Zabidi, Ainy Haziyah Awab, and Ab Al-Hadi Ab Rahman. "VLSI Implmentation of a Fast Kogge-Stone Parallel-Prefix Adder." Journal of Physics: Conference Series 1049 (July 2018): 012077. http://dx.doi.org/10.1088/1742-6596/1049/1/012077.

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Bhattacharjee, Debjyoti, Anne Siemon, Eike Linn, Stephan Menzel, and Anupam Chattopadhyay. "Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays." ACM Journal on Emerging Technologies in Computing Systems 14, no. 2 (July 27, 2018): 1–14. http://dx.doi.org/10.1145/3183352.

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Hoe, David H. K., L. P. Deepthi Bollepalli, and Chris D. Martinez. "FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders." VLSI Design 2013 (November 7, 2013): 1–10. http://dx.doi.org/10.1155/2013/382682.

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This paper examines fault tolerant adder designs implemented on FPGAs which are inspired by the methods of modular redundancy, roving, and gradual degradation. A parallel-prefix adder based upon the Kogge-Stone configuration is compared with the simple ripple carry adder (RCA) design. The Kogge-Stone design utilizes a sparse carry tree complemented by several smaller RCAs. Additional RCAs are inserted into the design to allow fault tolerance to be achieved using the established methods of roving and gradual degradation. A triple modular redundant ripple carry adder (TMR-RCA) is used as a point of reference. Simulation and experimental measurements on a Xilinx Spartan 3E FPGA platform are carried out. The TMR-RCA is found to have the best delay performance and most efficient resource utilization for an FPGA fault-tolerant implementation due to the simplicity of the approach and the use of the fast-carry chain. However, the superior performance of the carry-tree adder over an RCA in a VLSI implementation makes this proposed approach attractive for ASIC designs.
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Dissertations / Theses on the topic "Kogge-Stone"

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Åslund, Anders. "Power Estimation of High Speed Bit-Parallel Adders." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2390.

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Fast addition is essential in many DSP algorithms. Various structures have been introduced to speed up the time critical carry propagation. For high throughput applications, however, it may be necessary to introduce pipelining. In this report the power consumption of four different adder structures, with varying word length and different number of pipeline cuts, is compared.

Out of the four adder structures compared, the Kogge-Stone parallel prefix adder proves to be the best choice most of the time. The Brent-Kung parallel prefix adder is also a good choice, but the maximal throughput does not reach as high as the maximal throughput of the Kogge-Stone parallel prefix adder.

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Book chapters on the topic "Kogge-Stone"

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Lokesh Chowdary, M., A. Mallaiah, and A. Jaya Lakshmi. "Design of Wallace Tree Multiplier Using Sparse Kogge-Stone and Brent–Kung Adders." In Lecture Notes in Networks and Systems, 195–203. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8204-7_20.

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Frustaci, Fabio, and Marco Lanuzza. "A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder." In Lecture Notes in Computer Science, 357–66. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-11802-9_40.

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Raghav, Himadri Singh, Sachin Maheshwari, and B. Prasad Singh. "Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology." In Communications in Computer and Information Science, 100–107. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-42024-5_13.

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Conference papers on the topic "Kogge-Stone"

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Anjana, R., B. Abishna, M. S. Harshitha, E. Abhishek, V. Ravichandra, and M. S. Suma. "Implementation of vedic multiplier using Kogge-stone adder." In 2014 International Conference on Embedded Systems (ICES). IEEE, 2014. http://dx.doi.org/10.1109/embeddedsys.2014.6953044.

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Mukhopadhyay, Dhiman, and Arindam Chatterjee. "ATPG for 2D/3D wider Kogge-Stone Adder circuit." In 2016 International Conference on Computer, Electrical & Communication Engineering (ICCECE). IEEE, 2016. http://dx.doi.org/10.1109/iccece.2016.8009537.

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Raju, Aradhanan, and Sudhir Kumar Sa. "Design and performance analysis of multipliers using Kogge Stone Adder." In 2017 3rd International Conference on Applied and Theoretical Computing and Communication Technology (iCATccT). IEEE, 2017. http://dx.doi.org/10.1109/icatcct.2017.8389113.

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Moudallal, Zahi, Ibrahim Issa, Mohammad Mansour, Ali Chehab, and Ayman Kayssi. "A low-power methodology for configurable wide kogge-stone adders." In 2011 International Conference on Energy Aware Computing (ICEAC 2011). IEEE, 2011. http://dx.doi.org/10.1109/iceac.2011.6403621.

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Shrivastava, Shubhi, and Paresh Rawat. "High speed and delay efficient convolution by using Kogge Stone device." In 2017 International Conference on Computer Communication and Informatics (ICCCI). IEEE, 2017. http://dx.doi.org/10.1109/iccci.2017.8117789.

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Chen, Yancang, Minlei Zhang, Pei Wei, Sai Sui, Yaxin Zhao, and Lunguo Xie. "Implementation of a Parallel Prefix Adder Based on Kogge-Stone Tree." In 2016 International Conference on Communications, Information Management and Network Security. Paris, France: Atlantis Press, 2016. http://dx.doi.org/10.2991/cimns-16.2016.58.

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Daphni, S., and K. S. Vijula Grace. "Design an Area Efficient Kogge Stone Adder using Pass Transistor Logic." In 2021 Third International Conference on Intelligent Communication Technologies and Virtual Mobile Networks (ICICV). IEEE, 2021. http://dx.doi.org/10.1109/icicv50876.2021.9388489.

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Penchalaiah, U., and Siva Kumar VG. "Design of High-Speed and Energy-Efficient Parallel Prefix Kogge Stone Adder." In 2018 IEEE International Conference on System, Computation, Automation and Networking (ICSCAN). IEEE, 2018. http://dx.doi.org/10.1109/icscan.2018.8541143.

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Ghosh, Swaroop, Patrick Ndai, and Kaushik Roy. "A novel low overhead fault tolerant Kogge-Stone adder using adaptive clocking." In the conference. New York, New York, USA: ACM Press, 2008. http://dx.doi.org/10.1145/1403375.1403462.

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Kai, Chang Chin, Suhaila Isaak, and Yusmeeraz Yusof. "16-bit Fault Tolerant Sparse Kogge Stone Adder using 0.18μm CMOS Technology." In 2020 IEEE International Conference on Semiconductor Electronics (ICSE). IEEE, 2020. http://dx.doi.org/10.1109/icse49846.2020.9166865.

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