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Journal articles on the topic 'Kogge Stone Adder'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

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1

Yagain, Deepa, Vijaya Krishna A, and Akansha Baliga. "Design of High-Speed Adders for Efficient Digital Design Blocks." ISRN Electronics 2012 (September 26, 2012): 1–9. http://dx.doi.org/10.5402/2012/253742.

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The core of every microprocessor and digital signal processor is its data path. The heart of data-path and addressing units in turn are arithmetic units which include adders. Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well suited for VLSI implementations. This paper involves the design and comparison of high-speed, parallel-prefix adders such as Kogge-Stone, Brent-Kung, Sklansky, and Kogge-Stone Ling adders. It is found that Kogge-Stone Ling adder performs much efficiently when compared to the other adders. Here, Kogge-Stone Ling adders and

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2

Aritra, Mitra, Bakshi Amit, Sharma Bhavesh, and Didwania Nilesh. "Design of a High Speed Adder." International Journal of Scientific & Engineering Research 6, no. 4 (2015): 918–21. https://doi.org/10.5281/zenodo.33243.

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In this paper we have compared different addition algorithms such as Ripple Carry Adder, Carry Save Adder, Carry Select Adder, Carry Look Ahead Adder & Kogge Stone Adder for different performance parameters i.e. Area Utilization, Speed of operation and Power Consumption. A high speed Adder is then designed by merging Kogge Stone & Carry Select Algorithms. The circuits have been designed using Verilog HDL & Synthesize using TSMC 180 nm standard cell. The performance parameters are obtained with the help of Cadence Encounter RTL Compiler.

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3

Kumar V G, Kiran, and Shantharama Rai C,. "Low Power High Speed Arithmetic Circuits." International Journal of Recent Technology and Engineering (IJRTE) 8, no. 2 (2019): 807–13. http://dx.doi.org/10.35940/ijrte.a1064.078219.

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In the Design of arithmetic circuits reducing area, high speed and power are the major areas in VLSI system design. In this paper parallel prefix adders like Kogge-stone adder, Breunt-Kung adder, Ladner-Fischer adder is designed .Radix-4 Booth multiplier is designed by using Kogge-Stone adder. 16 bit Vedic multiplier is done by using Urdhwa Triyambaka sutra .8bit Vedic division is implemented by using Crumbs method so as to reduce the area, LUT tables and increase the speed as well as to reduce the Power dissipiation. The design is synthesized using Xilinx ISE 14.1 design suite.

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4

Anagani, Vamsidhar, Kasi Geethanjali, Anusha Gorantla, and Annamreddy Devi. "An improved approximate parallel prefix adder for high performance computing applications: a comparative analysis." International Journal of Informatics and Communication Technology (IJ-ICT) 14, no. 2 (2025): 382. https://doi.org/10.11591/ijict.v14i2.pp382-392.

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Binary adders are fundamental in digital circuit designs, including digital signal processors and microprocessor data path units. Consequently, significant research has focused on improving adders’ power-delay efficiency. The carry tree adder (CTA) is alternatively referred to as the parallel prefix adder (PPA), is among the fastest adders, achieving superior performance in very large scale integrated (VLSI) implementations through efficient concurrent carry generation and propagation. This study introduces approximate PPAs (AxPPAs) by applying approximations in prefix operators (POs). Four ty

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5

S., Nithin, and Ramesh K.B. "Design of High Speed Carry Select Adder Using Kogge-Stone and Carry-Lookahead Adders." Recent Trends in Analog Design and Digital Devices 7, no. 3 (2024): 23–33. https://doi.org/10.5281/zenodo.13709580.

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<em>The adder is acknowledged as the fundamental component in various arithmetic and logical operations. In efforts to enhance operational efficiency, the Carry Select Adder (CSLA) has been devised. By integrating multiple high-speed adder logics within a conventional CSLA framework, operational speed is further enhanced. This study presents the design of a hybrid CSLA that amalgamates the advantages of both Kogge Stone Adder and Look Ahead Adder (CLA) methodologies to achieve superior performance. Kogge Stone Adder, distinguished for its rapid carry generation, is incorporated to bolster spee

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6

Naga Babu, Ch, P. Naga Siva Sai, Ch Priyanka, K. Hari Kishore, M. Bindu Bhargavi, and K. Karthik. "Comparative Analysis of High Speed Carry Skip Adders." International Journal of Engineering & Technology 7, no. 2.24 (2018): 121. http://dx.doi.org/10.14419/ijet.v7i2.24.12015.

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In this paper we compared a high speed carry skip adders by considering parameters such as area, LUT’S, delay, power. When compared to conventional CSKA and other adders. Here in this project in first stage CSKA designed by using multiplexer as skip logic so by using this speed gets increased by skipping of carry. so here area gets increased so to reduce area another hybrid variable latency carry skip adder(Brent-kung adder) is designed .here power utilization also gets decreased, speed gets increased, but some delay is produced here to overcome that we followed a another method called Kogge-S

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7

BKondalkar, Mangesh, Arunkumar P Chavan, and P. Narashimaraja. "Improved Fault Tolerant Sparse KOGGE Stone ADDER." International Journal of Computer Applications 75, no. 10 (2013): 36–41. http://dx.doi.org/10.5120/13150-0582.

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8

Swetha, Potharla, and R. Rajkumar. "A Novel Design of a 4 Bit Reversible ALU using Kogge Stone Adder." International Journal of Trend in Scientific Research and Development 1, no. 6 (2017): 1296–301. https://doi.org/10.31142/ijtsrd5758.

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Reversible circuits are one promising direction withapplications in the field of low power design or quantumcomputation. However, no real design flow for this new kind ofcircuits exists so far. Significant contributions have been madein the literature towards the design of reversible logic gatestructures and arithmetic units, however, there are not manyefforts directed towards the design of reversible ALUs. In thispaper, a novel programmable reversible Kogge Stone adder ispresented and verified, and its implementation in the design ofa reversible Arithmetic Logic Unit is demonstrated. Then,rev

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9

Mahammad, Masood Ahmad, Appala Raju Uppala, Suggala Ram Prasad, and Anusha Marouthu. "Performance analysis of parallel prefix adders developed with field programmable gate array technology." International Journal of Reconfigurable and Embedded Systems (IJRES) 14, no. 1 (2025): 109. https://doi.org/10.11591/ijres.v14.i1.pp109-116.

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In many digital systems like high-performance computing and digital signal processing, parallel prefix adders are vital. Field programmable gate array (FPGA) technology is a well-known platform for developing parallel prefix adders. FPGA performance depends on bit size of the adder, the adder structure chosen, and the implementation specifications. An examination of the performance and area of parallel prefix adders developed using FPGA technology is presented in this research work. We look into how different design factors, such as the adder structure and the number of input bits, affect the

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10

Mahammad, Masood Ahmad, Appala Raju Uppala, Ram Prasad Suggala, and Anusha Marouthu. "Performance analysis of parallel prefix adders developed with field programmable gate array technology." International Journal of Reconfigurable and Embedded Systems (IJRES) 14, no. 1 (2025): 109–16. https://doi.org/10.11591/ijres.v14.i1.pp109-116.

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In many digital systems like high-performance computing and digital signal processing, parallel prefix adders are vital. Field programmable gate array (FPGA) technology is a well-known platform for developing parallel prefix adders. FPGA performance depends on bit size of the adder, the adder structure chosen, and the implementation specifications. An examination of the performance and area of parallel prefix adders developed using FPGA technology is presented in this research work. We look into how different design factors, such as the adder structure and the number of input bits, affect the

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11

S., Lakshmipriya. "A Review on Implementation of Parallel Prefix Adders using FPGA'S." International Journal of Trend in Scientific Research and Development 2, no. 1 (2019): 1304–6. https://doi.org/10.31142/ijtsrd7165.

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The paper mainly used in the implementation of parallel prefix adders using FPGA'S. The carry tree adders constitute spanning tree adder, sparse Kogge Stone and Kogge Stone adder. It also presents a representation of the carry skip adder. The best resolution of the VLSI system is obtained by the Prefix adders. Thus the implementation of the block diagram is difficult so the FPGA technology is used instead. They produce the high efficiency of the layout using the FPGA analysis. Better delay and performance of the RCA design in the 128 bits in the use of the fast chain array. Xilinx Spartan

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12

Eppili, Jaya, Sri B. Sai, Kumar P. Akshay, Kumar O. Hem, D. Sunil, and R. Rajesh. "VLSI implementation of Kogge-Stone Adder for low-power applications." i-manager's Journal on Digital Signal Processing 11, no. 1 (2023): 9. http://dx.doi.org/10.26634/jdp.11.1.19372.

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The adder is a vital part of the Central Processing Unit (CPU) that can perform computational operations. It is used in digital components, mainly in the design of integrated circuits. Recent decades have seen a sharp rise in demand for mobile electronics, which has increased the need for highly efficient Very Large-Scale Integration (VLSI) structures. All operations must be computed using low-power, space-efficient designs that run faster. The Kogge-Stone adder (KSA) is an extension of the carry look-ahead adder which is used for performing fast addition in high-performance computing systems.

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13

Swami G, Narayan, Bhuvana D T, Keerthana M R, Ankita B, and Manoja E. "Optimization of Delay and Area for Approximate Radix-8 Booth Multiplier." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–6. https://doi.org/10.55041/ijsrem39405.

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This paper investigates the optimization of Radix-8 Booth Multipliers, which are essential for efficient arithmetic operations in modern digital systems, particularly in applications such as digital signal processing, telecommunications, and image processing where rapid and accurate calculations are crucial. The study aims to enhance performance by focusing on reducing both delay and area while ensuring that acceptable accuracy levels are maintained for error-tolerant applications. To achieve these optimization goals, we compare three methodologies: the Carry Save Adder (CSA), the Kogge Stone

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14

Nusullapalli, Rambabu, and Vaishnavi N. "DESIGN OF FFT ARCHITECTURE USING KOGGE STONE ADDER." International Journal of Advances in Signal and Image Sciences 4, no. 2 (2018): 8. http://dx.doi.org/10.29284/ijasis.4.2.2018.8-15.

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15

Priyanka, Sharma* K. Srinivasarao. "DESIGN AND IMPLEMENTATION OF CARRY SELECT ADDER USING KOGGE-STONE TECHNIQUE." International Journal OF Engineering Sciences & Management Research 3, no. 6 (2016): 62–69. https://doi.org/10.5281/zenodo.55861.

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In VLSI System design digital adder with optimum power is one of the important area of research. For many data processing purpose CSA perform fast air thematic function. So, it is clear that there is need to reduce the power consumption in CSA. This paper discusses about to reduce the power dissipation in CSA for many applications. For reduction purpose we use one of the most important approaches, which are Kogge –stone configuration. The proposed design with Kogge-stone adder CSA has reduced power dissipation compared with CMOS technology CSA. The simulation performed using SPICE circui

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16

A., Akilandeswari, Grace Vimala Annie, and D.Sungeetha. "A Low Power Shift Add Multiplier for Lifting Based Dwt using Kogge Stone Adder." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 4 (2020): 1080–86. https://doi.org/10.35940/ijeat.C6211.029320.

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The most common technique used for image processing applications is ‘The wavelet transformation’. The Discrete Wavelet Transform (DWT) keeps the time as well as frequency information depend on a multi resolution analysis structure, where the other classical transforms like Fast Fourier Transform (FFT), Discrete Cosine Transform (DCT) will not do that. Because of this feature, the quality of the repaired image is improved when comparing to the other transforms. To implement the DWT on a real time codec, a fast device needs to be targeted. While comparing with the other implementatio

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17

A., Abinaya, and Maheswari M. "Implementation of Kogge Stone Adder for Signal Processing Applications." IJARCCE 8, no. 5 (2019): 141–46. http://dx.doi.org/10.17148/ijarcce.2019.8528.

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18

Shapiro, Alexander E., Francois Atallah, Kyugseok Kim, Jihoon Jeong, Jeff Fischer, and Eby G. Friedman. "Adaptive power gating of 32-bit Kogge Stone adder." Integration 53 (March 2016): 80–87. http://dx.doi.org/10.1016/j.vlsi.2015.12.001.

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19

Hoe, David H. K., L. P. Deepthi Bollepalli, and Chris D. Martinez. "FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders." VLSI Design 2013 (November 7, 2013): 1–10. http://dx.doi.org/10.1155/2013/382682.

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This paper examines fault tolerant adder designs implemented on FPGAs which are inspired by the methods of modular redundancy, roving, and gradual degradation. A parallel-prefix adder based upon the Kogge-Stone configuration is compared with the simple ripple carry adder (RCA) design. The Kogge-Stone design utilizes a sparse carry tree complemented by several smaller RCAs. Additional RCAs are inserted into the design to allow fault tolerance to be achieved using the established methods of roving and gradual degradation. A triple modular redundant ripple carry adder (TMR-RCA) is used as a point

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20

Sivadurgarao, Parasa, Naga Venkata Tejaswini Paruchuri, Huzaifa Mohammad, Vardhini Vagu, Geethika Pakalapati, and Taraka Rama Shanmukh Sai Segu. "Design and validation of low power, high performance parallel prefix adders." i-manager’s Journal on Electronics Engineering 15, no. 3 (2025): 48. https://doi.org/10.26634/jele.15.3.21813.

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In the realm of designing digital systems through Very Large Scale Integration (VLSI), the digital adder takes center stage. However, low-power VLSI adder designs grapple with the Propagation Delay issue, leading to increased latency. This paper explores the viability of Parallel Prefix Adders (PPA) in addressing these challenges for low-power VLSI designs, emphasizing minimal propagation latency. The paper delves into the design and analysis of select PPA models, comparing their performance in terms of area, delay, and power. Utilizing Xilinx Vivado 2019.1, this study evaluates four prominent

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21

Neeraja, P. K., and Narayanadass Ramadass. "A Modified Fused Floating Point Three Term Adder." International Journal of Engineering and Advanced Technology (IJEAT) 10, no. 1 (2020): 415–19. https://doi.org/10.35940/ijeat.A1908.1010120.

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This paper is about a modified architecture for a fused floating point three term adder. The important feature of a fused floating-point three-term adder is its ability to do multiple additions in same block to get better performance as well as accuracy compared to a conventional discrete floating point adder. The parallel prefix adder is one amongst the fastest adders and out of which the han-carlson adder represents a blend of the kogge-stone adders and brent-kung adder. In this work, han carlson adder is used to enhance the performance of the three term adder along with various optimization

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22

A, Vishnupriya, and Sudarmani R. "Efficient Serial Multiplier Design using Ripple Counters,Kogge-Stone Adder and Full Adder." International Journal of Computer Applications 67, no. 6 (2013): 33–38. http://dx.doi.org/10.5120/11401-6717.

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23

S., Sandeep, and Kiran V. "SYNTHESIS AND FPGA VALIDATION OF PARALLEL PREFIX ADDERS." International Journal of Advanced Research 10, no. 10 (2022): 708–17. http://dx.doi.org/10.21474/ijar01/15539.

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In this work, the design implementation, functionality testing, design synthesis and bitstream generation of various n-bit adder architecture of RCA, CLA, CSkA and KSA. And addresses various forms of adders which include Ripple-carry (RCA), Carry-lookahead (CLA), Carry-skip (CSkA), and Kogge-stone (KSA) adders. Certain design restrictions for digital VLSI circuits, such speed and area, can be satisfied using these adders. All the mentioned adder are designed using Verilog HDL, implemented the same on Xilinx Vivado 2018.2, functionality test is carried out by writing testbench, bitstream genera

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24

Sindhuja, K. Aishwarya. "Implementation of Time Efficient VLSI Design using Kogge Stone Adder." International Journal for Research in Applied Science and Engineering Technology 8, no. 9 (2020): 56–59. http://dx.doi.org/10.22214/ijraset.2020.31307.

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25

Mei Xiang, Lee, Muhammad Mun’im Ahmad Zabidi, Ainy Haziyah Awab, and Ab Al-Hadi Ab Rahman. "VLSI Implmentation of a Fast Kogge-Stone Parallel-Prefix Adder." Journal of Physics: Conference Series 1049 (July 2018): 012077. http://dx.doi.org/10.1088/1742-6596/1049/1/012077.

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26

Bhattacharjee, Debjyoti, Anne Siemon, Eike Linn, Stephan Menzel, and Anupam Chattopadhyay. "Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays." ACM Journal on Emerging Technologies in Computing Systems 14, no. 2 (2018): 1–14. http://dx.doi.org/10.1145/3183352.

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27

Deepak, Kumar Athur, Narayanan Bhuvanesh, Gopalakrishnan Amshuman, Palanisamy Sasipriya, and Angeline Augustine Anita. "Design of novel high speed parallel prefix adder." Design of novel high speed parallel prefix adder 29, no. 3 (2023): 1345–54. https://doi.org/10.11591/ijeecs.v29.i3.pp1345-1354.

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Adders are crucial logical building blocks found almost in all the modern electronic system designs. In the adder architecture design, the fundamental issue is the propagation latency in the carry chain. As the length of the input operands increases, the length of the carry chain along with it. Parallel prefix adders, which address the problem of carry propagation in adders, are the most efficient adder topologies for hardware implementation. However, delay reduction still could be achieved for very high speed applications. Hence, in this paper design of 16bit novel parallel prefix adder is pr

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28

Akilandeswari, A., Annie Grace Vimala, and D. Sungeetha. "A Low Power Shift Add Multiplier for Lifting Based Dwt using Kogge Stone Adder." International Journal of Engineering and Advanced Technology 9, no. 4 (2020): 1080–86. http://dx.doi.org/10.35940/ijeat.c6211.029320.

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The most common technique used for image processing applications is ‘The wavelet transformation’. The Discrete Wavelet Transform (DWT) keeps the time as well as frequency information depend on a multi resolution analysis structure, where the other classical transforms like Fast Fourier Transform (FFT), Discrete Cosine Transform (DCT) will not do that. Because of this feature, the quality of the repaired image is improved when comparing to the other transforms. To implement the DWT on a real time codec, a fast device needs to be targeted. While comparing with the other implementation such as PC

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29

Potharla, Swetha, and Rajkumar R. "A Novel Design of a 4 Bit Reversible ALU using Kogge-Stone Adder." International Journal of Trend in Scientific Research and Development Volume-1, Issue-6 (2017): 1296–301. http://dx.doi.org/10.31142/ijtsrd5758.

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30

Kumar Athur, Deepak, Bhuvanesh Narayanan, Amshuman Gopalakrishnan, Sasipriya Palanisamy, and Anita Angeline Augustine. "Design of novel high speed parallel prefix adder." Indonesian Journal of Electrical Engineering and Computer Science 29, no. 3 (2023): 1345. http://dx.doi.org/10.11591/ijeecs.v29.i3.pp1345-1354.

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Adders are crucial logical building blocks found almost in all the modern electronic system designs. In the adder architecture design, the fundamental issue is the propagation latency in the carry chain. As the length of the input operands increases, the length of the carry chain along with it. Parallel prefix adders, which address the problem of carry propagation in adders, are the most efficient adder topologies for hardware implementation. However, delay reduction still could be achieved for very high speed applications. Hence, in this paper design of 16bit novel parallel prefix adder is pr

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31

Kowsalya, P., M. Malathi, and Palaniappan Ramanathan. "Low Power Parallel Prefix Adder." Applied Mechanics and Materials 573 (June 2014): 194–200. http://dx.doi.org/10.4028/www.scientific.net/amm.573.194.

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Addition is a fundamental operation of all Arithmetic and Logic Units (ALU).The speed of addition operation decides the computational frequency of ALU. In order to improve the performance of the binary adder, the parallel prefix adder are preferred. There are various parallel prefix adders available. This work focuses on designing 8-bit prefix adders such as Brent Kung ,Kogge Stone and Sklansky adders using GDI technique. The performance of these GDI based prefix adders are compared with that of CMOS based prefix adder. GDI based prefix adders out performs CMOS based prefix adders in terms of

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32

N., Sridevi, and M. Meenakshi. "Efficient reconfigurable architecture for moving object detection with motion compensation." Indonesian Journal of Electrical Engineering and Computer Science 23, no. 2 (2021): 802. http://dx.doi.org/10.11591/ijeecs.v23.i2.pp802-810.

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The detection and tracking of object in large data surveillance requires a proper motion estimation and compensation techniques which are generally used to detect accurate movement from video stream. In this paper, a novel hardware level architecture involving motion detection, estimation, and compensation is proposed for real-time implementation. The motion vectors are obtained using 16×16 sub-blocks with a novel parallel D flip flop architecture in this work to arrive at an optimised architecture. The sum of absolute difference (SAD) is then calculated by optimized absolute difference and ad

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N., Sridevi, and M. Meenakshi. "Efficient reconfigurable architecture for moving object detection with motion compensation." Indonesian Journal of Electrical Engineering and Computer Science 23, no. 2 (2021): 802–10. https://doi.org/10.11591/ijeecs.v23.i2.pp802-810.

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The detection and tracking of object in large data surveillance requires a proper motion estimation and compensation techniques which are generally used to detect accurate movement from video stream. In this paper, a novel hardware level architecture involving motion detection, estimation, and compensation is proposed for real-time implementation. The motion vectors are obtained using 16×16 sub-blocks with a novel parallel D flip flop architecture in this work to arrive at an optimised architecture. The sum of absolute difference (SAD) is then calculated by optimized absolute difference

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34

Researcher. "LOW POWER HIGH SPEED HANS CARLSON ADDER USING SPST." International Journal of Applied Electronics (IJAE) 5, no. 2 (2024): 1–10. https://doi.org/10.5281/zenodo.13381981.

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The concept of SPST is to segregate the arithmetic units into Most significant Part (MSP) & Least significant Part (LSP), where MSP doesn’t affect most of computation results. Efficient adders are beneficial in the arithmetic circuit design. Ripple carry adder was found to have lowest gate count but maximum delay. To address the area and delay, a high speed low power Han Carlson adder adopting SPST is proposed in this part of process. Hans Carlson adder’s is coalescence of two designs comprising Kogge-stone and the Brent-Kung construction. The Xilinx- Vivado tool was used to si

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35

Hussain, Md Zakir, and Kazi Nikhat Parvin. "Performance Analysis of High Speed and Area Efficient Finite Impulse Response Filters." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 12, no. 01 (2020): 8–12. http://dx.doi.org/10.18090/samriddhi.v12i01.2.

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This study represents the designing and implementation of a bandpass finite impulse response (FIR) filter of order 31 using windowing techniques. The frequency parameters used are of a typical GSM receiver,19 which is one of the applications of software-defined radio (SDR). To minimize filter area, various multiplication techniques like a canonical signed digit, Vedic multiplier, booth multiplier, and modified booth multiplier are used. Adders like ripple carry adder, carry save adder, carry look ahead adder, and Kogge-Stone adder are used to add the product from the multiplier unit. A compari

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36

Dr.Tammisetti, Ashok, Dileepkumar Kunchala, Suresh Kumar Kornipati, Amareswari Pradyumna Mediga, Praveen Kumar Mallikeswarapu, and Avinash Kuvvarapu. "Design and analysis of GDI based kogge stone adder for low power applications." International Journal for Modern Trends in Science and Technology 11, no. 04 (2025): 131–37. https://doi.org/10.5281/zenodo.15121134.

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In modern VLSI design, the demand for highspeed and energy-efficient arithmetic circuits isever-growing, particularly in low-power computing applications. The KoggeStone Adder(KSA) is widely recognized for its parallel-prefix architecture, offering reduced delaycompared to conventional adders. However, traditional KSA implementations suffer fromhigh power consumption and increased transistor count. To address this, we propose aGDI-based Kogge-Stone Adder, leveraging the Gate Diffusion Input (GDI) technique tooptimize power efficiency while maintaining computational accuracy. The proposed desig

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Thakur, Garima, Harsh Sohal, and Shruti Jain. "High Speed RADIX-2 Butterfly Structure Using Novel Wallace Multiplier." International Journal of Engineering & Technology 7, no. 3.4 (2018): 213. http://dx.doi.org/10.14419/ijet.v7i3.4.16777.

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In Signal Processing applications the arithmetic units mainly consists of adders and multipliers. These arithmetic units are used in to enhance the performance of Fast Fourier Transform (FFT) Butterfly structure implementation. This paper discusses the addition and multiplication algorithms for parameters like speed, area and power. The best suited among all adders are Kogge Stone Adder (KSA) while among multipliers are Wallace multiplier(WM) which is used for the implementation of the FFT structure. Verilog coding is used for implementation of circuit and the tool used is Xilinx ISE 14.1 Desi

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Singaravelan, Hema, and Dr Kiran V. "32-bit Kogge-Stone based Hybrid Adder Implemented using Standard Cells of Different Logic Families." Journal of University of Shanghai for Science and Technology 23, no. 09 (2021): 196–204. http://dx.doi.org/10.51201/jusst/21/09539.

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Adders performs a critical role in all computational operations, thereby optimizing them with respect to design constraints for a system is essential. In this paper, standard cells of different logic families, namely- CMOS, Pseudo NMOS, and MGDI, are designed in Cadence Design Suite Virtuoso 6.1.7 in 180nm technology and characterized using Liberate 15.1.3. The standard cell libraries thus created are then applied to 32-bit KSA (Kogge-Stone Adder) and KSA based proposed hybrid adder that are implemented in Verilog, functionally verified on Xilinx Vivado 2020.2 and synthesized on Cadence Genus

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Abbas, Abdulkareem Dawah. "Review of high-speed phase accumulator for direct digital frequency synthesizer." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 4 (2020): 4008. http://dx.doi.org/10.11591/ijece.v10i4.pp4008-4014.

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A review of high-speed pipelined phase accumulator (PA) is proposed in this paper. The detail explanation of ideas, methods and techniques used in previous researches to improve the PA throughput designs were surveyed. The Brent–Kung (BK) adder was modified in this paper to be applied in pipelined PA architecture. A comparison of different adder circuits, includes a modified BK, ripple carry adder (RCA), Kogge-Stone adder (KS) and other prefix adders were applied to architect the PA based on Pipeline technique. The presented pipelined PA design circuit with multiple frequency control word (FCW

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Abdulkareem, Dawah Abbas. "Review of high-speed phase accumulator for direct digital frequency synthesizer." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 4 (2020): 4008–14. https://doi.org/10.11591/ijece.v10i4.pp4008-4014.

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A review of high-speed pipelined phase accumulator (PA) is proposed in this paper. The detail explanation of ideas, methods and techniques used in previous researches to improve the PA throughput designs were surveyed. The Brent-Kung (BK) adder was modified in this paper to be applied in pipelined PA architecture. A comparison of different adder circuits, includes a modified BK, ripple carry adder (RCA), Kogge-Stone adder (KS) and other prefix adders were applied to architect the PA based on Pipeline technique. The presented pipelined PA design circuit with multiple frequency control word (FCW

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Sanduri, Akshitha, P. Navitha Mrs., and D. Mamatha Mrs. "Fast Modular Multiplication using Parallel Prefix Adder." International Journal of Trend in Scientific Research and Development 2, no. 5 (2018): 1770–74. https://doi.org/10.31142/ijtsrd18170.

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Public key cryptography applications involve use of large integer arithmetic operations which are compute intensive in term of power, delay and area. Modular multiplication, which is frequently, used most resource hungry block. Generally, last stage of modular multiplication is implemented by using carry propagate adder whose long carry chain takes more time. In this paper, modulo multiplication architectures using Carry Save and Kogge Stone parallel prefix adder are presented to reduce this problem. Proposed implementations are faster as compared to conventional carry save adder and carry pro

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Govindaraj, Prabakaran, Shanmugasundaram Nallasamy, Mohankumar Mylsamy, and Sathiyapriya Krishnamoorthy. "DESIGN AND ANALYSIS OF NOVEL PARALLEL PREFIX ADDERS FOR VLSI CIRCUITS." Suranaree Journal of Science and Technology 31, no. 1 (2024): 010276(1–8). http://dx.doi.org/10.55766/sujst-2024-01-e0379.

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Arithmetic Logic Unit is the brain of all processors, is composed of an Adder circuit. The main component of multiplier circuits is the adder, which performs subtraction (by 2’s complement arithmetic). Since the most fundamental operation in mathematics is addition, and the adder is the most essential part of the processor, the study of VLSI arithmetic has required many digital VLSI researchers. When designing digital systems employing the VLSI approach, the digital adder plays a major role. Low power VLSI based adder designs perform poorly because of the propagation delay issue. With the aid

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Manogna, Manchiryala, and M. Shiva Kumar. "Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits using Quantam-Dot Celluar Automata (QCA) Technique." International Journal for Research in Applied Science and Engineering Technology 11, no. 10 (2023): 704–19. http://dx.doi.org/10.22214/ijraset.2023.56082.

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Abstract: In this paper, we propose an approximate multiplier that is Approximate computing (AC) offers benefits by reducing the requirement for accuracy, thereby reducing delay. The majority logic (ML) gate functions as the fundamental logic block of many emerging nanotechnologies. These adders are designed to prevent the propagation of inexact carry-out signals to higher order computing parts to enhance accuracy. We implemented the proposed multiplier by using a unique partial product reduction (PPR) circuitry, which was based on the parallel approximate 6:3 compressor. The implemented by qu

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Yadav, Jatin, Anupam Kumar, Shaik Shareef, Sandeep Bansal, and Navjot Rathour. "Comparative Analysis of Vedic Multiplier using Various Adder Architectures." Journal of Physics: Conference Series 2327, no. 1 (2022): 012022. http://dx.doi.org/10.1088/1742-6596/2327/1/012022.

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Abstract The performance of a microprocessor depends on the efficient multiplier as it is one of the most principal component in various digital circuits. This paper reviews optimization techniques for high speed Vedic multiplier design which is based on Urdhva Tiryakbhyam Sutra of Ancient Indian Vedic Mathematics. This particular sutra is the most efficient one as it gives minimum delay for all types of complex multiplication. Adder being the most important component in a multiplier design, using the efficient adder will enhance the performance of Vedic multiplier. During the comparison, diff

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Dhilipkumar, P., and G. Mohanbabu. "Energy Conservation of Adiabatic ECRL-Based Kogge-Stone Adder Circuits for FFT Applications." Intelligent Automation & Soft Computing 32, no. 3 (2022): 1445–58. http://dx.doi.org/10.32604/iasc.2022.021663.

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Ozer, M., M. Eren Çelik, Y. Tukel, and A. Bozbey. "Design of RSFQ wave pipelined Kogge–Stone Adder and developing custom compound gates." Cryogenics 63 (September 2014): 174–79. http://dx.doi.org/10.1016/j.cryogenics.2014.05.007.

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N., Vidhya. "An Efficient Implementation of N-Bit Kogge Stone Adder for High Speed and Low Power ALU." Journal of Advanced Research in Dynamical and Control Systems 12, SP4 (2020): 690–96. http://dx.doi.org/10.5373/jardcs/v12sp4/20201535.

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Yang, Xinghua, Yue Xing, Fei Qiao, and Huazhong Yang. "Multistage Latency Adders Architecture Employing Approximate Computing." Journal of Circuits, Systems and Computers 26, no. 03 (2016): 1750039. http://dx.doi.org/10.1142/s0218126617500396.

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This paper proposed an energy efficient adder employing multistage latency and approximate computing technology. The delay of the adder decreases after the critical path of the adder is divided into multiple short stages with series of predictors, then the approximate computing technology is exploited to make a tradeoff between output quality and energy efficiency. The proposed design is applied into discrete cosine transformation (DCT) in image processing and support vector machine (SVM) algorithm in machine learning to verify its availability, the simulation results demonstrate that the prop

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B R, Mr Chethan, T. S. Samarth, Praveen T R, Vishwas V S, and Mruthyunjaya S D. "Floating Point Multiplier using High Performance Adders and Multipliers." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–7. https://doi.org/10.55041/ijsrem39447.

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This paper presents a high-performance floating- point multiplier designed using advanced adder and multiplier architectures to enhance computational efficiency and speed for FPGA-based applications. The design employs Carry Bypass Adder (CBA) and Kogge-Stone Adder (KSA) to optimize partial product accumulation, along with Wallace Tree and Systolic Multiplier architectures for efficient parallel multiplication. Implemented in compliance with the IEEE 754 single-precision floating-point standard, the proposed multiplier is synthesized and simulated using the Vivado design suite. Comprehensive a

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Khushboo, Bais* Zoonubiya Ali. "DESIGN OF A HIGH-SPEED WALLACE TREE MULTIPLIER." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 6 (2016): 476–80. https://doi.org/10.5281/zenodo.55546.

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Multiplication is one of the most common arithmetic operations employed in digital systems, but multipliers are the most time, area, and power consuming circuits. Improvement in any of these parameters can be advantageous for improving the efficiency of the circuit. The ever increasing need for development of efficient and high speed multipliers has motivated several researchers to go a step ahead and present some novel approach. This paper presents an approach towards the reduction of delay in the Wallace tree multipliers by using 4:2 compressors along with full-adders and half-adders, in the

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