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Journal articles on the topic 'Kogge-Stone'

Author: Grafiati

Published: 4 June 2021

Last updated: 18 February 2022

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1

Yagain, Deepa, Vijaya Krishna A, and Akansha Baliga. "Design of High-Speed Adders for Efficient Digital Design Blocks." ISRN Electronics 2012 (September 26, 2012): 1–9. http://dx.doi.org/10.5402/2012/253742.

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The core of every microprocessor and digital signal processor is its data path. The heart of data-path and addressing units in turn are arithmetic units which include adders. Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well suited for VLSI implementations. This paper involves the design and comparison of high-speed, parallel-prefix adders such as Kogge-Stone, Brent-Kung, Sklansky, and Kogge-Stone Ling adders. It is found that Kogge-Stone Ling adder performs much efficiently when compared to the other adders. Here, Kogge-Stone Ling adders and ripple adders are incorporated as a part of a lattice filter in order to prove their functionalities. It is seen that the operating frequency of lattice filter increases if parallel prefix Kogge-Stone Ling adder is used instead of ripple adders since the combinational delay of Kogge-Stone Ling adder is less. Further, design and comparison of different tree adder structures are performed using both CMOS logic and transmission gate logic. Using these adders, unsigned and signed comparators are designed as an application example and compared with their performance parameters such as area, delay, and power consumed. The design and simulations are done using 65 nm CMOS design library.

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2

BKondalkar, Mangesh, Arunkumar P Chavan, and P. Narashimaraja. "Improved Fault Tolerant Sparse KOGGE Stone ADDER." International Journal of Computer Applications 75, no. 10 (August 23, 2013): 36–41. http://dx.doi.org/10.5120/13150-0582.

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3

Nusullapalli, Rambabu, and Vaishnavi N. "DESIGN OF FFT ARCHITECTURE USING KOGGE STONE ADDER." International Journal of Advances in Signal and Image Sciences 4, no. 2 (December 28, 2018): 8. http://dx.doi.org/10.29284/ijasis.4.2.2018.8-15.

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4

A., Abinaya, and Maheswari M. "Implementation of Kogge Stone Adder for Signal Processing Applications." IJARCCE 8, no. 5 (May 30, 2019): 141–46. http://dx.doi.org/10.17148/ijarcce.2019.8528.

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5

Shapiro, Alexander E., Francois Atallah, Kyugseok Kim, Jihoon Jeong, Jeff Fischer, and Eby G. Friedman. "Adaptive power gating of 32-bit Kogge Stone adder." Integration 53 (March 2016): 80–87. http://dx.doi.org/10.1016/j.vlsi.2015.12.001.

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6

Naga Babu, Ch, P. Naga Siva Sai, Ch Priyanka, K. Hari Kishore, M. Bindu Bhargavi, and K. Karthik. "Comparative Analysis of High Speed Carry Skip Adders." International Journal of Engineering & Technology 7, no. 2.24 (April 25, 2018): 121. http://dx.doi.org/10.14419/ijet.v7i2.24.12015.

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In this paper we compared a high speed carry skip adders by considering parameters such as area, LUT’S, delay, power. When compared to conventional CSKA and other adders. Here in this project in first stage CSKA designed by using multiplexer as skip logic so by using this speed gets increased by skipping of carry. so here area gets increased so to reduce area another hybrid variable latency carry skip adder(Brent-kung adder) is designed .here power utilization also gets decreased, speed gets increased, but some delay is produced here to overcome that we followed a another method called Kogge-Stone adder here so it reduces the critical path delay. In Kogge-stone adder power is highly consumed due to more no of wiring connections so another adder was designed to reduce power consumption which is Sklansky adder which reduces power Consumption. This is done in Xilinx ISE 14.7 and power was analyzed using Xilinx power analyzer.

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7

Sindhuja, K. Aishwarya. "Implementation of Time Efficient VLSI Design using Kogge Stone Adder." International Journal for Research in Applied Science and Engineering Technology 8, no. 9 (September 30, 2020): 56–59. http://dx.doi.org/10.22214/ijraset.2020.31307.

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8

Mei Xiang, Lee, Muhammad Mun’im Ahmad Zabidi, Ainy Haziyah Awab, and Ab Al-Hadi Ab Rahman. "VLSI Implmentation of a Fast Kogge-Stone Parallel-Prefix Adder." Journal of Physics: Conference Series 1049 (July 2018): 012077. http://dx.doi.org/10.1088/1742-6596/1049/1/012077.

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9

Bhattacharjee, Debjyoti, Anne Siemon, Eike Linn, Stephan Menzel, and Anupam Chattopadhyay. "Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays." ACM Journal on Emerging Technologies in Computing Systems 14, no. 2 (July 27, 2018): 1–14. http://dx.doi.org/10.1145/3183352.

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10

Hoe, David H. K., L. P. Deepthi Bollepalli, and Chris D. Martinez. "FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders." VLSI Design 2013 (November 7, 2013): 1–10. http://dx.doi.org/10.1155/2013/382682.

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This paper examines fault tolerant adder designs implemented on FPGAs which are inspired by the methods of modular redundancy, roving, and gradual degradation. A parallel-prefix adder based upon the Kogge-Stone configuration is compared with the simple ripple carry adder (RCA) design. The Kogge-Stone design utilizes a sparse carry tree complemented by several smaller RCAs. Additional RCAs are inserted into the design to allow fault tolerance to be achieved using the established methods of roving and gradual degradation. A triple modular redundant ripple carry adder (TMR-RCA) is used as a point of reference. Simulation and experimental measurements on a Xilinx Spartan 3E FPGA platform are carried out. The TMR-RCA is found to have the best delay performance and most efficient resource utilization for an FPGA fault-tolerant implementation due to the simplicity of the approach and the use of the fast-carry chain. However, the superior performance of the carry-tree adder over an RCA in a VLSI implementation makes this proposed approach attractive for ASIC designs.

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11

Potharla, Swetha, and Rajkumar R. "A Novel Design of a 4 Bit Reversible ALU using Kogge-Stone Adder." International Journal of Trend in Scientific Research and Development Volume-1, Issue-6 (October 31, 2017): 1296–301. http://dx.doi.org/10.31142/ijtsrd5758.

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12

Dubey, Rajnish, and Jitendra Jain. "An Efficient Processing by using Kogge-Stone High Speed Addition Technique." International Journal of Computer Applications 131, no. 1 (December 17, 2015): 21–23. http://dx.doi.org/10.5120/ijca2015907211.

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13

N., Sridevi, and M. Meenakshi. "Efficient reconfigurable architecture for moving object detection with motion compensation." Indonesian Journal of Electrical Engineering and Computer Science 23, no. 2 (August 1, 2021): 802. http://dx.doi.org/10.11591/ijeecs.v23.i2.pp802-810.

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The detection and tracking of object in large data surveillance requires a proper motion estimation and compensation techniques which are generally used to detect accurate movement from video stream. In this paper, a novel hardware level architecture involving motion detection, estimation, and compensation is proposed for real-time implementation. The motion vectors are obtained using 16×16 sub-blocks with a novel parallel D flip flop architecture in this work to arrive at an optimised architecture. The sum of absolute difference (SAD) is then calculated by optimized absolute difference and adder blocks designed using kogge-stone adder which helps in improving the speed of the architecture. The controller block is designed by finite state machine model used for synchronization of all the operations. Further, the comparator and compensation blocks are optimized by using basic logical elements and the Kogge-stone adder. Finally, the proposed architecture is implemented on Zynq Z7-10 field-programmable gate array (FPGA) and simulated using System Generator tool for real time traffic signal. The hardware and software parameters are compared with the existing techniques which shows that the proposed architecture is efficient than existing methods of design.

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14

A, Vishnupriya, and Sudarmani R. "Efficient Serial Multiplier Design using Ripple Counters,Kogge-Stone Adder and Full Adder." International Journal of Computer Applications 67, no. 6 (April 18, 2013): 33–38. http://dx.doi.org/10.5120/11401-6717.

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15

sudharani, Somarajupalli, and M. Sumalatha. "Delay Efficient Kogge Stone Approach for Implementing Shift Registers By Using Pulsed Latches." International Journal of Engineering Trends and Technology 43, no. 2 (January 25, 2017): 109–15. http://dx.doi.org/10.14445/22315381/ijett-v43p219.

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16

Ozer, M., M. Eren Çelik, Y. Tukel, and A. Bozbey. "Design of RSFQ wave pipelined Kogge–Stone Adder and developing custom compound gates." Cryogenics 63 (September 2014): 174–79. http://dx.doi.org/10.1016/j.cryogenics.2014.05.007.

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17

N., Vidhya. "An Efficient Implementation of N-Bit Kogge Stone Adder for High Speed and Low Power ALU." Journal of Advanced Research in Dynamical and Control Systems 12, SP4 (March 31, 2020): 690–96. http://dx.doi.org/10.5373/jardcs/v12sp4/20201535.

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18

Dhanabal, R., and V. N. Ramakrishnan. "Design of Montgomery Multiplier for High Speed Pairing Computation with Modified Compressor for Floating-point Unit." Journal of Computational and Theoretical Nanoscience 17, no. 5 (May 1, 2020): 2336–41. http://dx.doi.org/10.1166/jctn.2020.8892.

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Pairings are adorable and captive cryptographic primitives for endowing different unique and effective information security schemes. Cryptosystem is generally attained using repeated modular multiplication for integers in large volume. To gear the security providing process high speed Montgomery multiplication modular VLSI architectures and algorithms and adapt addition by carry save method to prevent the carry propagation for every addition operation in add-shift loop. The suggested architecture consumes less energy and through put is high. In extension the compressor is modified with modified Kogge-stone adder to prominently increase the speed of the circuit.

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19

Thakur, Garima, Harsh Sohal, and Shruti Jain. "High Speed RADIX-2 Butterfly Structure Using Novel Wallace Multiplier." International Journal of Engineering & Technology 7, no. 3.4 (June 25, 2018): 213. http://dx.doi.org/10.14419/ijet.v7i3.4.16777.

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In Signal Processing applications the arithmetic units mainly consists of adders and multipliers. These arithmetic units are used in to enhance the performance of Fast Fourier Transform (FFT) Butterfly structure implementation. This paper discusses the addition and multiplication algorithms for parameters like speed, area and power. The best suited among all adders are Kogge Stone Adder (KSA) while among multipliers are Wallace multiplier(WM) which is used for the implementation of the FFT structure. Verilog coding is used for implementation of circuit and the tool used is Xilinx ISE 14.1 Design suite.

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20

Singaravelan, Hema, and Dr Kiran V. "32-bit Kogge-Stone based Hybrid Adder Implemented using Standard Cells of Different Logic Families." Journal of University of Shanghai for Science and Technology 23, no. 09 (September 7, 2021): 196–204. http://dx.doi.org/10.51201/jusst/21/09539.

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Adders performs a critical role in all computational operations, thereby optimizing them with respect to design constraints for a system is essential. In this paper, standard cells of different logic families, namely- CMOS, Pseudo NMOS, and MGDI, are designed in Cadence Design Suite Virtuoso 6.1.7 in 180nm technology and characterized using Liberate 15.1.3. The standard cell libraries thus created are then applied to 32-bit KSA (Kogge-Stone Adder) and KSA based proposed hybrid adder that are implemented in Verilog, functionally verified on Xilinx Vivado 2020.2 and synthesized on Cadence Genus 15.22. Pseudo NMOS logic shows 14.03% area savings and MGDI offers 54.43% power saving based on area per cell over the traditional CMOS technology. It is also seen that the proposed adder offers a decrease in power and delay by 32.13% and 13.75% over KSA, respectively, in CMOS logic. Further discussions are made and suitable applications for all designs are also discussed.

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21

Hussain, Md Zakir, and Kazi Nikhat Parvin. "Performance Analysis of High Speed and Area Efficient Finite Impulse Response Filters." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 12, no. 01 (June 30, 2020): 8–12. http://dx.doi.org/10.18090/samriddhi.v12i01.2.

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This study represents the designing and implementation of a bandpass finite impulse response (FIR) filter of order 31 using windowing techniques. The frequency parameters used are of a typical GSM receiver,19 which is one of the applications of software-defined radio (SDR). To minimize filter area, various multiplication techniques like a canonical signed digit, Vedic multiplier, booth multiplier, and modified booth multiplier are used. Adders like ripple carry adder, carry save adder, carry look ahead adder, and Kogge-Stone adder are used to add the product from the multiplier unit. A comparison between three different windows has been made. The FIR is designed in MATLAB using a windowing technique. Then it is synthesized on Xilinx 14.7, Virtex 6 XC6VLX760, whose results are included in this paper.

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22

Wang, Ren Ping. "Full-Custom Design and Implementation of High-Performance Multiplier." Advanced Materials Research 631-632 (January 2013): 1445–51. http://dx.doi.org/10.4028/www.scientific.net/amr.631-632.1445.

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I proposed a method of using full-custom design 32 × 32 multiplier to enhance performance, reduce the power consumption and the area of layout. I use improved Wallace tree structure for partial product compression, truncated beyond the 64 part of the plot and the look-ahead logarithmic adder using Radix-4 Kogge-Stone tree algorithm raise the multiplier performance. In the design of Booth2 encoding circuit and compression circuit, I use a transmission gate logic design with higher speed and smaller area. I also use Euler path method and heuristic Euler path method to reduce the layout area. The design use SMIC 0.18μm 1P4M CMOS process, with a layout area of 0.1684mm2. In a large number of test patterns, simulation results show that the computation time of a 32 × 32 multiplication is less than 3.107ns.

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23

Kowsalya, P., M. Malathi, and Palaniappan Ramanathan. "Low Power Parallel Prefix Adder." Applied Mechanics and Materials 573 (June 2014): 194–200. http://dx.doi.org/10.4028/www.scientific.net/amm.573.194.

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Addition is a fundamental operation of all Arithmetic and Logic Units (ALU).The speed of addition operation decides the computational frequency of ALU. In order to improve the performance of the binary adder, the parallel prefix adder are preferred. There are various parallel prefix adders available. This work focuses on designing 8-bit prefix adders such as Brent Kung ,Kogge Stone and Sklansky adders using GDI technique. The performance of these GDI based prefix adders are compared with that of CMOS based prefix adder. GDI based prefix adders out performs CMOS based prefix adders in terms of power delay product (PDP). The design is implemented and simulated by DSCH2 and MICROWIND tool .The simulation result reveal about 31%,40% and 50 % of power saving is attained and the number of transistors also reduced.

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24

John, Vimukth, Shylu Sam, S. Radha, P. Sam Paul, and Joel Samuel. "Design of a power-efficient Kogge–Stone adder by exploring new OR gate in 45nm CMOS process." Circuit World 46, no. 4 (March 23, 2020): 257–69. http://dx.doi.org/10.1108/cw-12-2018-0104.

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Purpose The purpose of this work is to reduce the power consumption of KSA and to improve the PDP for data path applications. In digital Very Large – Scale Integration systems, the addition of two numbers is one of the essential functions. This arithmetic function is used in the modern digital signal processors and microprocessors. The operating speed of these processors depends on the computation of the arithmetic function. The speed computation block for most of the datapath elements was adders. In this paper, the Kogge–Stone adder (KSA) is designed using XOR, AND and proposed OR gates. The proposed OR gate has less power consumption due to the less number of transistors. In arithmetic logic circuit power, delay and power delay products (PDP) are considered as the important parameters. The delays reported for the proposed OR gate are less when compared with the conventional Complementary Metal Oxide Semiconductor (CMOS) OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. To analyze the performance of KSA, extensive Cadence Virtuoso simulations are used. From the simulation results based on 45 nm CMOS process, it was observed that the proposed design has obtained 688.3 nW of power consumption, 0.81 ns of delay and 0.55 fJ of PDP at 1.1 V. Design/methodology/approach In this paper, a new circuit for OR gate is proposed. The KSA is designed using XOR, AND and proposed OR gates. Findings The proposed OR gate has less power consumption due to the less number of transistors. The delays reported for the proposed OR gate are less when compared with the conventional CMOS OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. Originality/value In arithmetic logic circuit power, delay and PDP are considered as the important parameters. In this paper, a new circuit for OR gate is proposed. The power consumption of the designed KSA using the proposed OR gate is very less when compared with the conventional KSA. Simulation results show that the performance of the proposed KSA are improved and suitable for high speed applications.

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25

Abbas, Abdulkareem Dawah. "Review of high-speed phase accumulator for direct digital frequency synthesizer." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 4 (August 1, 2020): 4008. http://dx.doi.org/10.11591/ijece.v10i4.pp4008-4014.

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A review of high-speed pipelined phase accumulator (PA) is proposed in this paper. The detail explanation of ideas, methods and techniques used in previous researches to improve the PA throughput designs were surveyed. The Brent–Kung (BK) adder was modified in this paper to be applied in pipelined PA architecture. A comparison of different adder circuits, includes a modified BK, ripple carry adder (RCA), Kogge-Stone adder (KS) and other prefix adders were applied to architect the PA based on Pipeline technique. The presented pipelined PA design circuit with multiple frequency control word (FCW) and different adders were coded Verilog hardware description language (HDL) code, compiled and verified with field programmable gate array (FPGA) kit platform. The comparison result shows that the modified BK adder has fast performances. The shifted clocking technique is utilized in the proposed pipelined PA circuit to reduce the unwanted repetitive D-flip flop (DFF) registers (coming from the pipeline technique), while preserving the high speed.

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26

Alkurwy, Salah, Sawal H. Ali, Md Shabiul Islam, and Faizul Idros. "An area efficient memory-less ROM design architecture for direct digital frequency synthesizer." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (February 1, 2021): 257. http://dx.doi.org/10.11591/ijece.v11i1.pp257-264.

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This paper introduces a new technique of designing a read-only memory (ROM) circuit, namely; memory-less ROM as a novel approach to designing the ROM lookup table (LUT) circuit for use in a direct digital frequency synthesizer (DDFS). The proposed DDFS design uses the pipelined phase accumulator (PA) based on the kogge-stone (KS) adder. Verilog HDL programming is encoded on the architecture circuit of pipelined PA and contrasted with other PA based on various adders. The obtained results define the KS adder as having good capabilities for improving the throughput. In addition to the quarter symmetry technique, the built memory-less ROM to obtain the quarter sine amplitude waveform is proposed and implemented in the DDFS system. The implementation of the proposed technique replaces the necessary ROM registers (384 D flip-flops) and multiplexers with simple logic gate circuits instead of traditional ROMs. This technique would reduce the area size and cell count by 56% and 32.6% respectively.

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27

Vinutha, C. Ruth, M. Bharathi, and D. Divya. "A Survey on Brent-Kung, Han-Carlson and Kogge-Stone Parallel Prefix Adders for Their Area, Speed and Power Consumption." i-manager's Journal on Circuits and Systems 3, no. 4 (November 15, 2015): 37–41. http://dx.doi.org/10.26634/jcir.3.4.5929.

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28

Yang, Xinghua, Yue Xing, Fei Qiao, and Huazhong Yang. "Multistage Latency Adders Architecture Employing Approximate Computing." Journal of Circuits, Systems and Computers 26, no. 03 (November 21, 2016): 1750039. http://dx.doi.org/10.1142/s0218126617500396.

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This paper proposed an energy efficient adder employing multistage latency and approximate computing technology. The delay of the adder decreases after the critical path of the adder is divided into multiple short stages with series of predictors, then the approximate computing technology is exploited to make a tradeoff between output quality and energy efficiency. The proposed design is applied into discrete cosine transformation (DCT) in image processing and support vector machine (SVM) algorithm in machine learning to verify its availability, the simulation results demonstrate that the proposed approximate adder provides 25.6% power-delay-product (PDP) reduction and 2 orders of magnitude reduction in output error than the recent counterpart designs. Compared with the conventional accurate ripple carry adder (RCA) and Kogge stone adde (KSA), the proposed design presents 66.5% to 37.6% PDP reduction, at the cost of negligible output quality reduction, which are qualified as peak signal-to-noise ratio (PSNR) for DCT (decreases from 33.88dB to 33.84dB) and classification accuracy for SVM (decreases from 80.46% to 79.19%).

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29

Reddy Hemantha, G., S. Varadarajan, and M. N. Giriprasad. "DA Based Systematic Approach Using Speculative Addition for High Speed DSP Applications." International Journal of Engineering & Technology 7, no. 2.24 (April 25, 2018): 197. http://dx.doi.org/10.14419/ijet.v7i2.24.12030.

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In recent years Parallel-prefix topologies has been emerged to offer a high-speed solution for many DSP applications. Here in this paper carrier approximation is introduced to incorporate speculation in Han Carlson prefix method. And overall latency is considerably reduced using single Brent-Kung addition as a pre and post processing unit. In order to improve the reliability error detection network is combined with the approximated adder and it is assert the error correction unit whenever speculation fails during carries propagation from LSB segment to MSB unit. The proposed speculative adder based on Han-Carlson parallel-prefix topology attains better latency reduction than variable latency Kogge-Stone topology. Finally, multiplier-accumulation unit (MAC) is designed using serial shift-based accumulation where the proposed speculative adder is used for partial product addition iteratively. The performance merits and latency reduction of proposed adder unit is proved through FPGA hardware synthesis. Obtained results show that proposed MAC unit outperforms both previously proposed speculative architectures and all other high-speed multiplication methods.

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30

Et. al., Barma Venkata RamaLakshmi. "Implementation and Comparison of Radix-8 Booth Multiplier by using 32-bit Parallel prefix adders for High Speed Arithmetic Applications." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (April 10, 2021): 5673–83. http://dx.doi.org/10.17762/turcomat.v12i3.2242.

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This paper presents the implementation and design of Radix-8 booth Multiplier using 32-bit parallel prefix adders. High performance processors have a high demand in the industrial market. For achieving high performance and to enhance the computational speed multiplier plays a key role in performance of digital system. But the major drawback is it consumes more power , area and delay. To enhance the performance and decrease the area consumption and delay there are many algorithms and techniques. In this paper we designed a radix-8 Booth Multiplier using two parallel prefix adders and compared them for best optimized multiplier. The number of parital products generation can be reduced by n/3 by using radix-8 in the multiplier encoding. To further reduce the additions we have used booth recoding mechanism .We have implemented the design using Kogge stone adder and Brent kung adder. We observed that by using parallel prefix adders reduces the delay further more which results in significant increase in speed of the digital systems. The simulation results are carried out on XILINX VIVADO software.

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31

"Low Power High Speed Arithmetic Circuits." International Journal of Recent Technology and Engineering 8, no. 2 (July 30, 2019): 807–13. http://dx.doi.org/10.35940/ijrte.b1064.078219.

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In the Design of arithmetic circuits reducing area, high speed and power are the major areas in VLSI system design. In this paper parallel prefix adders like Kogge-stone adder, Breunt-Kung adder, Ladner-Fischer adder is designed .Radix-4 Booth multiplier is designed by using Kogge-Stone adder. 16 bit Vedic multiplier is done by using Urdhwa Triyambaka sutra .8bit Vedic division is implemented by using Crumbs method so as to reduce the area, LUT tables and increase the speed as well as to reduce the Power dissipiation. The design is synthesized using Xilinx ISE 14.1 design suite.

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32

KIRAN, RENUKUNTLA, and SUNITHA NAMPALLY. "ANALYZING THE PERFORMANCE OF CARRY TREE ADDERS BASED ON FPGA’S." International Journal of Electronics Signals and Systems, October 2013, 121–25. http://dx.doi.org/10.47893/ijess.2013.1152.

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In this paper carry tree adders are known to have the best performance in VLSI designs. However, this performance advantage does not translate directly into FPGA implementations due to constraints on logic block configurations and routing overhead. This paper investigates three types of carry-tree adders (the Kogge-Stone, sparse Kogge-Stone, and spanning tree adder) and compares them to the simple Ripple Carry Adder (RCA) and Carry Skip Adder (CSA). These designs of varied bit-widths were implemented on a Xilinx Spartan 3E FPGA and delay measurements were made with a high-performance logic analyzer. Due to the presence of a fast carry-chain, the RCA designs exhibit better delay performance up to 128 bits. The carry-tree adders are expected to have a speed advantage over the RCA as bit widths approach 256.

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33

"IMPLEMENTATION OF REVERSIBLE CIRCUITBASED KOGGE STONE PREFIX MODULO ADDER." Journal of critical reviews 7, no. 14 (September 2, 2020). http://dx.doi.org/10.31838/jcr.07.14.242.

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34

"Enhancement and Usage of Different Sorts of Efficient Parallel Prefix Adders." International Journal of Innovative Technology and Exploring Engineering 9, no. 2 (December 10, 2019): 3964–68. http://dx.doi.org/10.35940/ijitee.b7220.129219.

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Portray Mighty exploit adders (aside unfamiliar pretence as invite apparatus or against introduce adders) are track to crack the stroke in VLSI designs. In provincial case, this ordinance statement does howl decrypt right away into FPGA implementations befitting to chains on assertion arena configurations and routing overhead. This version preparation investigates span forms of Stand-machinery adders (Spanning tree adder and Brent-kung adder, the Kogge-Stone) and associates them to the uncomplicated a Carry Skip Adder (CSA) Ripple Carry Adder(RCA). The deception parameters steady for the comparative division of the presented adders are: the amid of logic gates, crawl run in plagiarized at the drop of a hat clog modeling in Xilinx curtailment. As a expectation, this instant affectation of alternate adders, Kogge-Stone adder and ready-made PPA effort akin to crisis slow.

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35

"DESIGN AND IMPLEMENTATION OF ARRAY MULTIPLIER USING KOGGE STONE ADDER." Journal of Xidian University 15, no. 6 (June 12, 2021). http://dx.doi.org/10.37896/jxu15.6/021.

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36

"A Low Power Shift Add Multiplier for Lifting Based Dwt using Kogge Stone Adder." International Journal of Engineering and Advanced Technology 9, no. 4 (April 30, 2020): 1080–86. http://dx.doi.org/10.35940/ijeat.c6211.049320.

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The most common technique used for image processing applications is ‘The wavelet transformation’. The Discrete Wavelet Transform (DWT) keeps the time as well as frequency information depend on a multi resolution analysis structure, where the other classical transforms like Fast Fourier Transform (FFT), Discrete Cosine Transform (DCT) will not do that. Because of this feature, the quality of the repaired image is improved when comparing to the other transforms. To implement the DWT on a real time codec, a fast device needs to be targeted. While comparing with the other implementation such as PCs, ARM processors, DSPs etc, Field Programmable Gate Array (FPGA) implementation of DWT had better processing speed and costs were vey less. A Fast Architecture based DWT using Kogge Stone Adder is proposed in this paper where the coefficients of lifting scheme are calculated by using Shift adder and Kogge Stone Adder where other techniques used multiplier. The most important intention of the suggested technique is to use minimum calculation and limited memory. The simulation of the suggested design is dole out on the Xilinx 14.1 style tool and also the performance is evaluated and compared with the present architectures.

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"Braun’s Multiplier Implementation using Ripple Carry Adder, Kogge-Stone Adder and 14-transistor novel ADDER." International Journal of Recent Trends in Engineering and Research, January 30, 2018, 483–89. http://dx.doi.org/10.23883/ijrter.conf.20171225.073.tdhy5.

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"AREA AND DELAY OPTIMIZATION OF KOGGE STONE ADDER USING APPROXIMATE 15-4 COMPRESSOR." Journal of critical reviews 7, no. 05 (September 2, 2020). http://dx.doi.org/10.31838/jcr.07.05.236.

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Michael Preetam Raj, P., Bhaskaruni Sandeep, D. Sai Mallik Reddy, P. Ramanjaneyulu, and Sakhamuri Sai Pravallika. "Design of Prefix Adder Amalgamation Reversible Logic Gates using 16 Bit Kogge Stone Adder." Indian Journal of Science and Technology 9, no. 13 (April 22, 2016). http://dx.doi.org/10.17485/ijst/2016/v9i13/87911.

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"Design and Implementation of Kogge Stone adder using CMOS and GDI Design: VLSI Based." International Journal of Engineering and Advanced Technology 8, no. 6S3 (November 22, 2019): 2181–82. http://dx.doi.org/10.35940/ijeat.f1422.0986s319.

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Adders is a significant part in different math legitimate activity. Parallel Prefix Adder was developed as the most basic and effective circuit for double expansion. The Particular structure and execution are alluring for VLSI usage. In these papers, I can depict the structure and execution of the Kogge Stone Parallel Prefix Adders and actualized utilizing diverse plan procedure. CMOS (Complementary Metal Oxide Semiconductor) and GDI (Gate Diffusion Input) are the distinctive structure system utilized. . The plan and reenactment of rationale entryways is performed on CADENCE Design Suit 6.1.6 utilizing virtuoso and ADE Environment at GPDK 180nm innovation. The execution estimation considered for the presentation of the KSA is delay, number of door check/Transistor Count (territory) and power. Recreation reads are accomplished for 4-piece, 8-piece and 16-piece input information

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J, Muralidharan, Senthisivakumar M, and Prakash A. "Performance Comparison of Adder Topologies with Parallel Processing Adder Circuit." Innovations in Information and Communication Technology Series, December 30, 2020, 209–11. http://dx.doi.org/10.46532/978-81-950008-1-4_046.

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In today’s modern era IC architecture design adders are become obligatory block. The growth in digitalization scenario to produce compact design products parameters like power, delay and area should be minimized. In most of the complex design of digital circuits, adder is an elementary factor. If the performance of digital adders is enriched, it would lead to quickening the binary operations in involved in the complex circuits. The constraints in the operation delay of an adder are due to carry propagation in the circuit. The adder topologies involved in this work includes Carry Save Adder, Carry Select Adder, Ripple Carry Adder and Kogge Stone Adder

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"Design of 32 Tap Finite Impulse Response Filter using Vedic Multiplier and KoggeStone Adder." International Journal of Recent Technology and Engineering 8, no. 2 (July 30, 2019): 6138–41. http://dx.doi.org/10.35940/ijrte.b3731.078219.

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32 tap FIR Filter is designed utilizing Vedic multiplier and Kogge stone adder. Effective performance is important for FIR Filter design due to increasing complexity. Two basic opertaions of FIR Filter are multiplication and addition. So, for multiplication, vedic multiplier is used and addition is performed by KS adder which is faster than other adders like Ripple carry adder, Look ahead carry adder, Carry select adder etc. K S adder is used to overcome problem of carry propagation. The objective is to minimize the propagation delay i.e increasing the speed of filter. Synthesis & simulation is done by Xilinx ISE 14.7 software tool using VHDL.

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J, Muralidharan, Senthisivakumar M, and Prakash A. "Performance Comparison of Adder Topologies with Parallel Processing Adder Circuit." Innovations in Information and Communication Technology Series, December 30, 2020, 209–11. http://dx.doi.org/10.46532/978-81-950008-1-4_046.

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In today’s modern era IC architecture design adders are become obligatory block. The growth in digitalization scenario to produce compact design products parameters like power, delay and area should be minimized. In most of the complex design of digital circuits, adder is an elementary factor. If the performance of digital adders is enriched, it would lead to quickening the binary operations in involved in the complex circuits. The constraints in the operation delay of an adder are due to carry propagation in the circuit. The adder topologies involved in this work includes Carry Save Adder, Carry Select Adder, Ripple Carry Adder and Kogge Stone Adder

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"FPGA Implementation of Area Efficient CMOS Multiplier using Fast Kogge Stone Look Ahead Logarithmic Adder." International Journal of Recent Technology and Engineering 8, no. 4 (November 30, 2019): 8445–49. http://dx.doi.org/10.35940/ijrte.d9714.118419.

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Though Multipliers play a major role in all digital processing systems, still there is a research challenge related with area, delay, power, speed and accuracy parameters. Basically multipliers contains more number of adders (i.e.,) multiplication is done by repetitive additions. Highest care should be taken on adders. Partial Products (PP) part is middle process between multiplier, multiplicand and final addition. Next one about the methodology that Serial/parallel, Pipeline/parallel, Floating/decimal, Array, Binary/BCD, Fixed/Variable, Gate Level/Transistor Level. All the predecessors are having more controversy parameters. The forthcoming research concentrated on parallel, pipelining, decimal, binary and transistor level.

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"A Modified Fused Floating Point Three Term Adder." Regular 10, no. 1 (October 30, 2020): 415–19. http://dx.doi.org/10.35940/ijeat.a1908.1010120.

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This paper is about a modified architecture for a fused floating point three term adder. The important feature of a fused floating-point three-term adder is its ability to do multiple additions in same block to get better performance as well as accuracy compared to a conventional discrete floating point adder. The parallel prefix adder is one amongst the fastest adders and out of which the han-carlson adder represents a blend of the kogge-stone adders and brent-kung adder. In this work, han carlson adder is used to enhance the performance of the three term adder along with various optimization techniques. The adder is implemented using Verilog language in Xilinx ISE Design suite 14.2 and all Simulations are carried out in Isim simulator. Synthesis is done using Cadencetool

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"Low Power Sub Threshold QDI Kogge Stone Adder using Sense Amplifier Lector based Half Buffer Cell Templates." International Journal of Innovative Technology and Exploring Engineering 8, no. 11S2 (October 26, 2019): 173–79. http://dx.doi.org/10.35940/ijitee.k1028.09811s219.

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Nowadays power consumption has the highest priority in designing high-performance electronics systems. The main purpose of this paper is to present a 16-bitKogge-Stone Adder where the low control operation is attained by the decrease of exchanging action. In this paper, we propose a method called Sense amplifier Lector based Half-Buffer (SALHB) by exemplifying Sense Amplifier Half Buffer (SAHB) with LECTOR algorithm to lessen leakage current in circuit structure. A 16-piece Kogge Stone Adder (KSA) is structured and actualized utilizing an asynchronous Quasi-Delay-Insensitive cell configuration approach known as the SALHB algorithm. Generally, SAHB is an asynchronous QDI configuration approach which applies 4-phase signaling protocol and sub-edge operation to obtain low control dissipation and rapid of operation. Additionally, LECTOR algorithm is applied to SAHB configuration approach through which leakage current can be decreased further to a great degree. A portion of the asynchronous QDI cell templates are Pre-charged Half-buffer(PCHB) and Autonomous signal validity Half-buffer(ASVHB), as both the templates, use completion detector circuits which lead to high power dissipation and large area overhead. SAHB design surpasses these drawbacks. But, SAHB has more leakage current. Hence, SALHB method was proposed to overcome the problem of high leakage current. In this paper, the performance of KSA is analyzed in terms of power, delay, energy, rise time, fall time, settle time, duty cyle, throughput and slew rate.

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"Performance Evaluation of New Adder Designed for Electronic Circuits." International Journal of Recent Technology and Engineering 8, no. 3 (September 30, 2019): 5039–43. http://dx.doi.org/10.35940/ijrte.c5681.098319.

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Arithmetic and Logic Unit (ALU) is the important module in any digital system utilized in the current world applications. Adder plays major role in the construction of any ALU. Multipliers can also be designed with the help of continuous addition. The efficient design of adders is very much needed for the efficient ALU design. Parallel prefix adder has been chosen in this research because of its fastest computation and efficiency. Kogge Stone, Sklansky, Ladner Fischer, Brunt Kung, Han-Carlson and Knowles are the adders discussed in this research. Further, the combinations of any two adders have also been tested for the best efficiency in terms of power consumption and delay utilisation. From the many combinations, it is found that the proposed combination of Bruntkung and SKlansky (BSK) adder performs excellent with the power consumption of 25011.22 nW and delay of 1243 pS.

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"Design and Analysis of 32-bit Reverse Converter based on low power Parallel Prefix Adder." International Journal of Engineering and Advanced Technology 9, no. 1 (October 30, 2019): 3028–31. http://dx.doi.org/10.35940/ijeat.a1207.109119.

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The Residue Number System (RNS) based reverse converter can play as main role in Parallel arithmetic operations of Digital Signal Processing (DSP) applications and VLSI technologies. Normally, by the use of carry adders, the reverse conversion design gives high delay and high power consumption. Due to resolve of above problem, the design of reverse converter is proposed by the use of familiar high speed (less propagation delay) Parallel Prefix - Kogge Stone Adder (PP- KSA). This paper describes the design of 32-bit Reverse converter with regular PP-KSA and proposed MUX (Multiplex) logic of PP-KSA with Hybrid Modular Parallel Prefix structure (HMPE) separately. In addition to that, the performance of that designs are analysed based on area, delay and power independently. The Performance results of proposed MUX logic of PP-KSA Reverse converter design yields low power than the other design which uses the regular PP-KSA. The simulation and synthesis effects can be done in Xilinx ISE 14.2i tool.

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"Implementation of Low Power High Speed Adder’s using GDI Logic." International Journal of Innovative Technology and Exploring Engineering 8, no. 11 (September 10, 2019): 1291–98. http://dx.doi.org/10.35940/ijitee.j9547.0981119.

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Addition is a vital arithmetic operation and is the base of other arithmetic operations such as multiplication, subtraction and division. Adder is a digital circuit that does addition of binary numbers. The 1-bit full adder is the basic block of an arithmetic unit. In VLSI, there are many efficient techniques to design digital circuits. Some of the techniques are Pass Transistor logic (PTL), Complementary metal oxide semiconductor (CMOS) and Transmitter gate (TG). There are several adder designs implemented to reduce the power. However, each design undergoes from precise disadvantage. The adder design with good driving capability requires more power and the design with more delay which consumes less power. In this paper 8-bit Carry Increment Adder (CIA), Carry Bypass Adder (CBA), Carry Skip Adder (CSKA), Carry Look Ahead Adder (CLA), Kogge Stone Adder (KSA), Han Carlson Adder (HCA), and Brent Kung Adder (BKA) are implemented using Gate Diffusion Input (GDI) logic. These designs are simulated and implemented using Tanner tool. The result shows that CBA, CLA, and KSA designs using GDI logic are more efficient compared to CMOS logic in view of power consumption, delay, and area (transistors count) respectively

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"Design and Implementation of Hybrid FIR Filters using Vedic Multiplier and Fast Adders." International Journal of Recent Technology and Engineering 8, no. 4 (November 30, 2019): 11849–53. http://dx.doi.org/10.35940/ijrte.d9569.118419.

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FIR (Finite Impulse Response) filters play a significant role in the field of Digital Signal Processing (DSP) to eliminate noise suppression in Electro Cardio Graph (ECG), Imaging devices and the signal stored in analog media. So filter evaluation is accomplished to reduce the noise level. The Filter passes only the desired frequency to pass thereby reducing distortion in the processed signal during measurement. The FIR filter comprises of basic units like adders, multipliers and the delay element for its operations.FIR and IIR are the two types of digital filters chosen based on the range of inputs, complexity and size requirement. Multipliers and adders play a vital role in deterring the performance of FIR filter. In this work, we design and analyze different multiplier and adder for high-performance Fir filter implementation. The Vedic Mathematics is the methods containing 16 Sutras to aid fast mental calculations. In this work, we propose modified Anurupye Vedic multiplier methods with Kogge Stone fast adder for implementation in the direct form FIR filter. This approach provides 1.5% decrease in delay and 10.2% reduced in power, hence increasing speed marginally than previous methods. Along with low power consumption in Very High-Speed Hardware Description Language (VHDL), all the adders and the multiplier topologies are Synthesized using (Xilinx Spartan – 6 FPGA) Trainer Kit and the proposed 8 – Tap FIR filter is executed using this Board

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