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Journal articles on the topic 'Layout Versus Schematic (LVS)'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

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1

Pujari, Swasti. "A Practical Approach to Layout versus Schematic (LVS)." International Journal for Research in Applied Science and Engineering Technology 7, no. 9 (2019): 663–70. http://dx.doi.org/10.22214/ijraset.2019.9089.

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2

M, G. Srinivasa. "Performance Analysis of 6T, 8T and 10T SRAM Cell in 45nm Technology." International Journal of Engineering and Advanced Technology (IJEAT) 13, no. 5 (2024): 12–16. https://doi.org/10.35940/ijeat.E4447.13050624.

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<strong>Abstract:</strong> The rise of portable battery-powered devices has emphasized the significance of low power IC design. Embedded SRAM units have become indispensable elements within contemporary SOCs due to their substantial footprint. In research circles, SRAM is highly regarded as a semiconductor memory type, highlighting its crucial role in the VLSI sector. In this paper, 6T, 8T and 10T SRAM cells design is estimated for power consumption and delay. This proposed work presents the schematic, simulation of analysis of 6T, 8T and 10T SRAM cells at 45 nm technology. The Cadence Virtuos

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3

M G Srinivasa and Bhavana M S. "Performance Analysis of 6T, 8T and 10T SRAM Cell in 45nm Technology." International Journal of Engineering and Advanced Technology 13, no. 5 (2024): 12–16. http://dx.doi.org/10.35940/ijeat.e4447.13050624.

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The rise of portable battery-powered devices has emphasized the significance of low power IC design. Embedded SRAM units have become indispensable elements within contemporary SOCs due to their substantial footprint. In research circles, SRAM is highly regarded as a semiconductor memory type, highlighting its crucial role in the VLSI sector. In this paper, 6T, 8T and 10T SRAM cells design is estimated for power consumption and delay. This proposed work presents the schematic, simulation of analysis of 6T, 8T and 10T SRAM cells at 45 nm technology. The Cadence Virtuoso software is utilized for

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4

Rajapriyadharshini, B., V. Renisha, S. Shivani, Kumar S. Bharath, and P. Latha. "Analog / Full Custom IC Design of Wilson Current Mirror." International Journal of Microsystems and IoT 2, no. 12 (2024): 1440–46. https://doi.org/10.5281/zenodo.15455573.

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This paper presents the design and implementation of an analog integrated circuit (IC) based on the Wilson current mirror topology. The design process was carried out using the Cadence Virtuoso tool suite. The initial phase involved creating the schematic in the Schematic Editor and generating a corresponding symbol to represent the circuit. A test bench was subsequently constructed using this symbol to enable simulation and performance evaluation. Input and output waveforms were obtained and analyzed to validate the functionality of the design. Additionally, the layout was generated and modif

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5

Gaddipati, Kavya. "Balancing Performance and Area in High-Speed Analog Layout Design: Systematic Approaches to DRC/LVS Optimization." European Journal of Computer Science and Information Technology 13, no. 21 (2025): 37–47. https://doi.org/10.37745/ejcsit.2013/vol13n213747.

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This article explores systematic approaches to navigating the critical balance between performance and area in high-speed analog layout design. It shows methodologies for efficient debugging of Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations, which represent fundamental verification steps in the analog design workflow. The article presents structured techniques for prioritizing and resolving verification issues, including hierarchical debugging approaches and automation tools for repetitive checks. Additionally, it gives area optimization strategies such as shared diffu

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6

Белявцев, А. В., А. В. Русанов, and Т. С. Шайкина. "RC OSCILLATOR FOR A DOMESTIC TECHNOLOGICAL PROCESS." ВЕСТНИК ВОРОНЕЖСКОГО ГОСУДАРСТВЕННОГО ТЕХНИЧЕСКОГО УНИВЕРСИТЕТА 20, no. 1 (2024): 45–50. http://dx.doi.org/10.36622/1729-6501.2024.20.1.007.

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предложен сложно-функциональный (СФ/IP) блок RC-генератора, построенный на МОП-транзисторах. Генератор является блоком тактирования для большого числа электронных устройств, не требовательных к стабильности частоты, но чувствительных к размеру. Данный блок предназначен для применения в составе интегральных схем стабилизаторов напряжения. Приведено описание электрической схемы генератора, его основные электрические характеристики и результаты моделирования (зависимости частоты генератора и его тока потребления от температуры и напряжения питания схемы, получены значения нестабильности частоты и

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7

Kim, Wonjong, and Hyunchul Shin. "Hierarchy Restructuring for Hierarchical LVS Comparison." VLSI Design 10, no. 1 (1999): 117–25. http://dx.doi.org/10.1155/1999/50892.

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A new hierarchical layout vs. schematic (LVS) comparison system for layout verification has been developed. The schematic hierarchy is restructured to remove ambiguities for consistent hierarchical matching. Then the circuit hierarchy is reconstructed from the layout netlist by using a modified SubGemini algorithm recursively in bottom-up fashion. For efficiency, simple gates are found by using a fast rule-based pattern matching algorithm during preprocessing. Experimental results show that our hierarchical netlist comparison technique is effective and efficient in CPU time and in memory usage

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8

Белявцев, А. В., А. В. Русанов та Д. О. Лялин. "СФ‑БЛОКИ ПРИЕМНИКА И ПЕРЕДАТЧИКА LVDS ДЛЯ ТЕХНОЛОГИЧЕСКОГО ПРОЦЕССА 180 НМ". ВЕСТНИК ВОРОНЕЖСКОГО ГОСУДАРСТВЕННОГО ТЕХНИЧЕСКОГО УНИВЕРСИТЕТА 21, № 1 (2025): 107–13. https://doi.org/10.36622/1729-6501.2025.21.1.016.

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представлены два сложно-функциональных (СФ/IP) блока для интегральных схем: приемник и передатчик низковольтной дифференциальной передачи сигналов (Low voltage differntial signal - LVDS). Раздел статьи, посвященный передатчику LVDS, содержит подробное описание структурной схемы СФ‑блока и электрических схем его составных частей, результаты моделирования, временные диаграммы работы и основные электрические параметры устройства. Отдельное внимание уделено особенностям схемотехнических решений, использованных при проектировании. Раздел, посвященный СФ‑блоку приемника LVDS, содержит краткое описан

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Susa, Hidekana, Kenji Mori, Mitsutoshi Sugawara, and Akira Matsuzawa. "SWA: SoftWare for Analog Design Automation." Chips 3, no. 4 (2024): 379–94. http://dx.doi.org/10.3390/chips3040019.

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We have developed SWA: SoftWare for Analog design automation. Its commands can describe analog and mixed-signal (AMS) layouts and schematics to replace the graphic editor with a program reflecting the knowledge of design experts. Also, it is able to utilize variables to parameterize schematics and layouts to fulfill design needs. We programmed a 10b 1 GS/s DAC using SWA with 8.3 K lines of code, which is about 1/10 compared with conventional programs. The programmed DAC is configurable with multiple voltages and multiple resolutions from 4 to 12 bits. The DAC schematic and layout generation wi

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10

Русанов, А. В., Л. В. Сопина, and А. В. Бунина. "BANDGAP REFERENCE VOLTAGE SOURCE FOR A DOMESTIC TECHNOLOGICAL PROCESS." ВЕСТНИК ВОРОНЕЖСКОГО ГОСУДАРСТВЕННОГО ТЕХНИЧЕСКОГО УНИВЕРСИТЕТА 19, no. 4 (2023): 71–76. http://dx.doi.org/10.36622/vstu.2023.19.4.009.

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предложены два сложнофункциональных (СФ/IP) блока операционных усилителей (ОУ), построенных на n-канальной и р-канальной дифференциальных парах. ОУ являются универсальными блоками, на основе которых можно построить множество различных электронных узлов. В настоящее время ОУ получили широкое применение как в виде отдельных чипов, так и в виде IP-блоков в составе более сложных интегральных схем. Разработанные IP-блоки ОУ предназначены для применения в интегральных схемах линейных стабилизаторов напряжения в качестве усилителей ошибки. В стабилизаторах напряжения усилитель ошибки выполняет ключев

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11

Gnilenko, A. B. "LAYOUT DESIGN OF A SYNAPTIC INPUT WITH DIGITALLY CONTROLLED WEIGHT COEFFICIENTS FOR A HARDWARE IMPLEMENTATION OF AN ARTIFICIAL SPIKING NEURON." System technologies 1, no. 144 (2023): 76–82. http://dx.doi.org/10.34185/1562-9945-1-144-2023-10.

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The layout design of a synaptic input with digitally controlled synaptic weight coefficients is presented as a building component of a spiking neuron hardware implementation. The de-sign is based on Leaky Integrate-and-Fire model of an artificial spiking neuron. The com-pact-sized layout is obtained using EDA tool with all necessary physical verifications ful-filled at every design stage. Layout versus schematic check and the simulation of signal waveforms at ports are performed based on the extracted netlist to validate the design.

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12

Zargari, Amir Hosein Afandizadeh, Marzieh AshrafiAmiri, Minjun Seo, Sai Manoj Pudukotai Dinakarrao, Mohammed E. Fouda, and Fadi Kurdahi. "CAPTIVE: Constrained Adversarial Perturbations to Thwart IC Reverse Engineering." Information 14, no. 12 (2023): 656. http://dx.doi.org/10.3390/info14120656.

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Reverse engineering (RE) in Integrated Circuits (IC) is a process in which one will attempt to extract the internals of an IC, extract the circuit structure, and determine the gate-level information of an IC. In general, the RE process can be done for validation as well as Intellectual Property (IP) stealing intentions. In addition, RE also facilitates different illicit activities such as the insertion of hardware Trojan, pirating, or counterfeiting a design, or developing an attack. In this work, we propose an approach to introduce cognitive perturbations, with the aid of adversarial machine

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13

Ramadan, Tarek. "SYSTEM-LEVEL, POST-LAYOUT ELECTRICAL ANALYSIS FOR HIGH-DENSITY ADVANCED PACKAGING." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (2019): 000856–77. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_wp1_015.

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INTRODUCTION High-density advanced packaging (HDAP) continues to be the promising “More” in the “More than Moore” approach for improved form factor, functionality, and integration of multiple dies built using different technology nodes. HDAP offerings from outsourced assembly and test (OSAT) companies and foundries are continuously increasing. However, the full commercial productization of such offerings will require the assurance of both an acceptable yield and correct (as intended) functionality. This assurance, like that for integrated circuits (ICs), will come from the availability of prov

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14

Martins, Ricardo. "Closing the Gap Between Electrical and Physical Design Steps with an Analog IC Placement Optimizer Enhanced with Machine-Learning-Based Post-Layout Performance Regressors." Electronics 13, no. 22 (2024): 4360. http://dx.doi.org/10.3390/electronics13224360.

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The design of integrated circuits in the analog spectrum is intricate due to the signals’ continuous nature. Additionally, it is strongly affected by the physical implementation of their devices and interconnections on the layout, a design task that has stubbornly defied all automation attempts. In this paper, one limitative factor is identified that must be addressed to finally push automation tools into the analog integrated circuit design flow: accurate assessment of post-layout performance degradation. For this purpose, a performance-driven placement generator highly integrated with off-th

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15

A. A, Sujata, and Lalitha Y. S. "Design and Performance Analysis of 4-bit Nano-processor Design for Low Area, Low Power and Minimum Delay Using 32nm FinFET Technology." WSEAS TRANSACTIONS ON ELECTRONICS 12 (January 20, 2021): 1–8. http://dx.doi.org/10.37394/232017.2021.12.1.

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The recent technologies in VLSI Chips have grown in terms of scaling of transistor and device parameters but still, there is challenging task for controlling current between the source and drain terminals. For effective control of device current, the FinFET transistors have come into VLSI chip, through which current can be controlled effectively. This paper is to address the issues present in CMOS technology and majorly concentrated on the proposed 4-bit Nano processor using FinFET 32nm technology by using the Cadence Virtuoso software tool. In the proposed Nano processor, the first part is to

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16

Anil Kumar, D. "FinFET based Design and Performance Analysis of Nano-processor for Low Area, Low Power and Minimum Delay using 32nm." International Journal of Circuits, Systems and Signal Processing 15 (July 22, 2021): 690–99. http://dx.doi.org/10.46300/9106.2021.15.77.

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The recent technologies in VLSI chips has grown in terms of scaling of transistor and device parameters but still there is a challenging task for controlling of current between source and drain terminals. For effective control of device current, the FinFET transistors have come into VLSI chip manufacturing, through which current can be effectively controlled. This section addresses the issues present in CMOS technology and majorly concentrated on proposed 4-bit Nano processor using FinFET 32nm technology by using Cadence Virtuoso software tool. In the proposed Nanoprocessor design, the first p

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17

Venkatesh, G. K., S. Bhargavi, Basavaraj V. Hiremath, and C. Anil Kumar. "Design and Performance Analysis of Low Power and High Throughput of Analog Data Compression and Decompression using ANN in 32nm FinFET Technology." International Journal of Circuits, Systems and Signal Processing 15 (July 28, 2021): 730–44. http://dx.doi.org/10.46300/9106.2021.15.81.

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The development and fabrication of integrated circuits for the applicational areas of VLSI such as processing of the signal, medicine tomography, telecommunication turn out to be a novel technology for the upcoming innovations. The fabrication of IC’s is attributable to the methodology in the technology of VLSI and when compared to artificial Neural Network, the genetic performance of these productions is approximately the same and are typically employed for diagnosing the syndrome, compression as well as the decompression of signal used in the medical domain. Techniques such as HMM, DCT, as w

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18

Parikh, Raj, and Khushi Sandip Parikh. "Mathematical Foundations of AI-Based Secure Physical Design Verification." Indian Journal of VLSI Design 5, no. 1 (2025): 1–7. https://doi.org/10.54105/ijvlsid.a1230.05010325.

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Concerns about hardware security are raised by the increasing dependence on third-party Semiconductor Intellectual Property in system-on-chip design, especially during physical design verification. Traditional rule-based verification methods, such as Design Rule Checking (DRC) and Layout vs. Schematic (LVS) checking, together with side-channel analysis indicated apparent deficiencies in dealing with new forms of threat. The impossibility of distinguishing dependable from malicious insertions in ICs makes it hard to prevent such dangers as hardware Trojans (HTs); side-channel vulnerabilities re

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19

Khushi, Sandip Parikh. "Mathematical Foundations of AI-Based Secure Physical Design Verification." Indian Journal of VLSI Design (IJVLSID) 5, no. 1 (2025): 1–7. https://doi.org/10.54105/ijvlsid.A1230.05010325.

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<strong>Abstract:</strong> Concerns about hardware security are raised by the increasing dependence on third-party Semiconductor Intellectual Property in system-on-chip design, especially during physical design verification. Traditional rule-based verification methods, such as Design Rule Checking (DRC) and Layout vs. Schematic (LVS) checking, together with side-channel analysis indicated apparent deficiencies in dealing with new forms of threat. The impossibility of distinguishing dependable from malicious insertions in ICs makes it hard to prevent such dangers as hardware Trojans (HTs); side

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20

Moukalled, F., and I. Lakkis. "Computer-Aided Analysis of Gas Turbine Cycles." International Journal of Mechanical Engineering Education 22, no. 3 (1994): 209–27. http://dx.doi.org/10.1177/030641909402200306.

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This paper describes a microcomputer-based, interactive, and menu-driven software package designed to help mechanical engineering students to understand gas turbines and to allow them to conduct more analysis of gas turbine cycles than they would normally be able to do by hand-calculation. The program deals with gas turbine cycle analysis so the acronym GTCA is used. GTCA is written in the Pascal computer language and runs on IBM PC, or compatible, computers. Improvements to the basic Brayton cycle, including three compressor and turbine stages, reheater, heat exchanger, intercooler, and preco

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21

Chiolino, N., A. M. Francis, J. Holmes, M. Barlow, and C. Perkowski. "470 Celsius Packaging System for Silicon Carbide Electronics." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2021, HiTEC (2021): 000083–88. http://dx.doi.org/10.4071/2380-4491.2021.hitec.000083.

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Abstract High temperature Silicon Carbide (SiC) integrated circuit (IC) processes have enabled devices that operate at &gt;450°C for more than a year. These results have established the need for more advanced and practical packaging strategies. Off the shelf state of the art packages cannot withstand the same high temperatures as the semiconductor can for long periods of time. Packaging SiC die to survive temperatures &gt;450°C, while also maintaining a reasonable packaging strategy that is agile, rapid, and modular, presents new challenges. Presented is a technique for packaging SiC d

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22

Rajapriyadharshini, B., V. Renisha, S. Shivani, Kumar S. Bharath, and P. Latha. "Analog / Full Custom IC Design of Wilson Current Mirror." 2, no. 12 (2024): 1440–46. https://doi.org/10.5281/zenodo.15455538.

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This paper presents the design and implementation of an analog integrated circuit (IC) based on the Wilson current mirror topology. The design process was carried out using the Cadence Virtuoso tool suite. The initial phase involved creating the schematic in the Schematic Editor and generating a corresponding symbol to represent the circuit. A test bench was subsequently constructed using this symbol to enable simulation and performance evaluation. Input and output waveforms were obtained and analyzed to validate the functionality of the design. Additionally, the layout was generated and modif

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23

Kaushik, Roohie, Jasdeep Kaur, and Anushree Anushree. "Design of folded cascode op amp and its application – bandgap reference circuit." Circuit World ahead-of-print, ahead-of-print (2021). http://dx.doi.org/10.1108/cw-10-2019-0137.

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Purpose Reference voltage or current generators are an important requirement for an analog or digital circuit design. Bandgap reference circuits (BGR) are most common way of generating the reference voltage. This paper aims to provide a detailed insight of design of a folded cascode operational amplifier (FC op amp) and a BGR circuit. The complete study flow from design to layout of the circuits on 180 nm semiconductor laboratory (SCL) process leading to bonding diagram for possible tape-out is discussed. This study work has been supported by MeitY, Govt. of India, through Special Manpower Dev

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24

Roberts, Rebecca, and Coenrad Fourie. "Layout-versus-schematic verification for superconductive integrated circuits." IEEE Transactions on Applied Superconductivity, 2014, 1. http://dx.doi.org/10.1109/tasc.2014.2373035.

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25

R., Abdul Wahab, Mohd Fuad Tengku Aziz R., Othman N., et al. "Physical Verification Flow on Multiple Foundries." August 2, 2015. https://doi.org/10.5281/zenodo.1108911.

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This paper will discuss how we optimize our physical verification flow in our IC Design Department having various rule decks from multiple foundries. Our ultimate goal is to achieve faster time to tape-out and avoid schedule delay. Currently the physical verification runtimes and memory usage have drastically increased with the increasing number of design rules, design complexity, and the size of the chips to be verified. To manage design violations, we use a number of solutions to reduce the amount of violations needed to be checked by physical verification engineers. The most important funct

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26

R., Abdul Wahab, Mohd Fuad Tengku Aziz R., Othman N., et al. "Physical Verification Flow on Multiple Foundries." International Journal of Electrical, Electronic and Communication Sciences 8.0, no. 10 (2015). https://doi.org/10.5281/zenodo.1338442.

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This paper will discuss how we optimize our physical verification flow in our IC Design Department having various rule decks from multiple foundries. Our ultimate goal is to achieve faster time to tape-out and avoid schedule delay. Currently the physical verification runtimes and memory usage have drastically increased with the increasing number of design rules, design complexity, and the size of the chips to be verified. To manage design violations, we use a number of solutions to reduce the amount of violations needed to be checked by physical verification engineers. The most important funct

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27

Budig, Michael, Oliver Heckmann, Markus Hudert, Amanda Qi Boon Ng, Zack Xuereb Conti, and Clement Jun Hao Lork. "Computational screening-LCA tools for early design stages." International Journal of Architectural Computing, August 13, 2020, 147807712094799. http://dx.doi.org/10.1177/1478077120947996.

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Life Cycle Assessment (LCA) has been widely adopted to identify the Global Warming Potential (GWP) in the construction industry and determine its high environmental impact through Greenhouse Gas (GHG) emissions, energy and resource consumptions. The consideration of LCA in the early stages of design is becoming increasingly important as a means to avoid costly changes at later stages of the project. However, typical LCA-based tools demand very detailed information about structural and material systems and thus become too laborious for designers in the conceptual stages, where such specificatio

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