Relevant bibliographies by topics / Lightly and heavily doped substrate

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers
  5. Reports

Academic literature on the topic 'Lightly and heavily doped substrate'

Author: Grafiati
Published: 4 June 2025
Last updated: 6 July 2025

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Journal articles on the topic "Lightly and heavily doped substrate"

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Sanjay, Sharma, Yadav R.P., and Janyani Vijay. "Substrate Current Evaluation for Lightly and Heavily Doped MOSFETs at 45 nm process Using Physical Models." Bulletin of Electrical Engineering and Informatics 5, no. 1 (2016): 120–25. https://doi.org/10.11591/eei.v5i1.556.

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Substrate noise is a major integration issue in mixed signal circuits; particularly at radio frequency (RF) it becomes a key issue. In deep sub micron MOSFETs hot carrier effect induces device degradation. The impact ionization phenomenon is one of the main hot carrier effects. The paper covers the process and device level simulation of MOSFETs by TCAD and the substrate current comparison in lightly and heavily doped MOS. PMOS and NMOS devices are virtually fabricated with the help of ATHENA process simulator. The modeled devices include the hot carrier effects. The MOS devices are implemented on lightly and heavily doped substrates and substrate current is evaluated and compared with the help of ATLAS device simulator. Substrate current is better in lightly doped substrate than in heavily doped one. Drain current is also better in lightly doped than heavily doped substrates. Silvaco TCAD Tool is used for Virtual fabrication and simulation. ATHENA process simulator is used for virtual fabrication and ATLAS device simulator is used for device characterization.
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Sasaki, Sho, Jun Suda, and Tsunenobu Kimoto. "Doping-Induced Lattice Mismatch and Misorientation in 4H-SiC Crystals." Materials Science Forum 717-720 (May 2012): 481–84. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.481.

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Thec- anda-lattice constants of nitrogen-doped 4H-SiC were measured in the wide temperature range (RT - 1100°C). The samples used in this study were heavily doped substrates and lightly-doped free-standing epilayers. The lattice constants at room temperature are almost identical for all the samples. However, the lattice contraction by heavy nitrogen doping was clearly observed at high temperatures, which indicates that the thermal expansion coefficients are dependent on the nitrogen concentration. The lattice mismatch (Δd/d) between a lightly-doped free-standing epilayer (Nd= 6x1014cm-3) and a heavily-doped substrate (Nd= 2x1019cm-3) was calculated as 1.7x10-4at 1100°C. The authors also investigated lattice constants of high-dose N+, P+, and Al+-implanted 4H-SiC. Reciprocal space mapping (RSM) was utilized to investigate the lattice mismatch and misorientation. The RSM images show thec-lattice expansion andc-axis tilt of the ion-implanted layers, irrespective of ion species. The authors conclude that the lattice expansion is not caused by heavy doping itself, but by secondary defects formed after the ion-implantation and activation-annealing process.
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Doi, Takuma, Shigehisa Shibayama, Mitsuo Sakashita, Kazutoshi Kojima, Mitsuaki Shimizu, and Osamu Nakatsuka. "Low-temperature formation of Mg/n-type 4H-SiC ohmic contacts with atomically flat interface by lowering of Schottky barrier height." Applied Physics Express 15, no. 1 (2021): 015501. http://dx.doi.org/10.35848/1882-0786/ac407f.

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Abstract To obtain an ohmic contact with a flat interface using a low-temperature process, we investigated the behavior of Schottky barrier height (SBH) at the Mg/n-type 4H-SiC interface to low-temperature annealing. Our results revealed that annealing at 200 °C reduced SBH; a low SBH of 0.28 eV was obtained on the lightly doped substrate. Atomic force microscopy measurements revealed negligible increase in the surface roughness after Mg deposition and annealing. Using the low-temperature process, a contact resistivity of 6.5 × 10−5 Ω·cm2 was obtained on the heavily doped substrate, which is comparable to Ni/4H-SiC subjected to annealing of above 950 °C.
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Clouter, Maynard J., Yue Ke, Robert P. Devaty, Wolfgang J. Choyke, Y. Shishkin, and Stephen E. Saddow. "Raman Spectra of a 4H-SiC Epitaxial Layer on Porous and Non-Porous 4H-SiC Substrates." Materials Science Forum 556-557 (September 2007): 415–18. http://dx.doi.org/10.4028/www.scientific.net/msf.556-557.415.

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A lightly doped n-type homo-epitaxial layer was grown by CVD onto a heavily doped n-type 4H-SiC substrate for which half of the surface had been made porous by photoelectrochemical etching. Raman spectra are obtained in the optic phonon region using three scattering geometries. An effective medium model for the porous layer is used to assist in the interpretation of the spectra. This work demonstrates that the contributions to the Raman spectra of the various layers in a sample with multiple 4H-SiC layers can be extracted.
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Xia, Xinyi, Minghan Xian, Fan Ren, Md Abu Jafar Rasel, Aman Haque, and S. J. Pearton. "Thermal Stability of Transparent ITO/n-Ga2O3/n+-Ga2O3/ITO Rectifiers." ECS Journal of Solid State Science and Technology 10, no. 11 (2021): 115005. http://dx.doi.org/10.1149/2162-8777/ac3ace.

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The thermal stability of n/n+ β-Ga2O3 epitaxial layer/substrate structures with sputtered ITO on both sides to act as rectifying contacts on the lightly doped layer and Ohmic on the heavily doped substrate is reported. The resistivity of the ITO deposited separately on Si decreased from 1.83 × 10−3 Ω.cm as-deposited to 3.6 × 10−4 Ω.cm after 300 °C anneal, with only minor reductions at higher temperatures (2.8 × 10−4 Ω.cm after 600 °C anneals). The Schottky barrier height also decreased with annealing, from 0.98 eV in the as-deposited samples to 0.85 eV after 500 °C annealing. The reverse breakdown voltage exhibited a negative temperature coefficient of −0.46 V.C−1 up to an annealing temperature of 400 °C and degraded faster at higher temperatures. Transmission Electron Microscopy showed significant reaction at the ITO and Ga2O3 interface above 300 °C, with a very degraded contact stack after annealing at 500 °C.
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Hazenboom, S., T. S. Fiez, and K. Mayaram. "A Comparison of Substrate Noise Coupling in Lightly and Heavily Doped CMOS Processes for 2.4-GHz LNAs." IEEE Journal of Solid-State Circuits 41, no. 3 (2006): 574–87. http://dx.doi.org/10.1109/jssc.2006.869790.

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Kim, Kyoung-Ho, Minh-Tan Ha, Heesoo Lee, et al. "Microstructural Gradational Properties of Sn-Doped Gallium Oxide Heteroepitaxial Layers Grown Using Mist Chemical Vapor Deposition." Materials 15, no. 3 (2022): 1050. http://dx.doi.org/10.3390/ma15031050.

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This study examined the microstructural gradation in Sn-doped, n-type Ga2O3 epitaxial layers grown on a two-inch sapphire substrate using horizontal hot-wall mist chemical vapor deposition (mist CVD). The results revealed that, compared to a single Ga2O3 layer grown using a conventional single-step growth, the double Ga2O3 layers grown using a two-step growth process exhibited excellent thickness uniformity, surface roughness, and crystal quality. In addition, the spatial gradient of carrier concentration in the upper layer of the double layers was significantly affected by the mist flow velocity at the surface, regardless of the dopant concentration distribution of the underlying layer. Furthermore, the electrical properties of the single Ga2O3 layer could be attributed to various scattering mechanisms, whereas the carrier mobility of the double Ga2O3 layers could be attributed to Coulomb scattering owing to the heavily doped condition. It strongly suggests the two-step-grown, lightly-Sn-doped Ga2O3 layer is feasible for high power electronic devices.
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Saw, Kim Guan, Sau Siong Tneh, Swee Yong Pung, Sha Shiong Ng, F. K. Yam, and Zainuriah Hassan. "Ultraviolet Photoresponse Properties of Zinc Oxide Nanorods on Heavily Boron-Doped Diamond Heterostructure." Advanced Materials Research 832 (November 2013): 172–77. http://dx.doi.org/10.4028/www.scientific.net/amr.832.172.

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Heterostructures consisting of ZnO and diamond appear to have an elusive nature. A rectifying behaviour was previously observed only for heterojunctions with very lightly doped p-type diamond using residual boron gas during the chemical vapour deposition process or type IIb diamond. Other studies, however, claimed to obtain a rectifying behaviour for heterojunctions with p-type diamond with higher carrier densities between 1018 1019 cm-3. In this work we investigate the behaviour of n-type ZnO on heavily boron-doped p-type diamond. This heterostructure that is sensitive to UV light has been fabricated using ZnO nanorods grown on heavily boron-doped chemical vapour deposition diamond substrates. The I -V measurements show a rectifying characteristic. The threshold voltages under dark and UV conditions are 3.66 and 2.52 V, respectively. The UV illumination also results in an increased current flow. The electrical behaviour due to the UV illumination will be discussed.
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de Lanerolle, N. "Titanium silicide growth by rapid-thermal processing of Ti films deposited on lightly doped and heavily doped silicon substrates." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 5, no. 6 (1987): 1689. http://dx.doi.org/10.1116/1.583649.

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Mazzola, Michael S., Swapna G. Sunkari, Janice Mazzola, et al. "Improved Resolution of Epitaxial Thin Film Doping Using FTIR Reflectance Spectroscopy." Materials Science Forum 483-485 (May 2005): 397–400. http://dx.doi.org/10.4028/www.scientific.net/msf.483-485.397.

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Room temperature Fourier Transform Infrared Reflection Spectroscopy (FTIR) was used to investigate the thickness and Free Carrier Concentration (FCC) of heavily and lightly doped 4H and 6H-SiC epitaxial films. Multiple epitaxial layer stacks typical of lateral devices such as the MESFET were grown on 6H-SiC semi-insulating substrates. The estimation of thickness and FCC of the n-channel epi layer is improved by studying the Longitudinal Optical Phonon Plasmon Coupled Modes (LPP). A modelbased analysis of the experimental reflectance spectra from these samples is performed using a dielectric function that accounts for the phonon-photon coupling and plasmonphoton coupling. The value of the LPP+ mode frequency estimated from the reflectance spectrum in the range 600-1200 cm-1 is observed to increase in direct correlation with the electron free-carrier concentration.
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Dissertations / Theses on the topic "Lightly and heavily doped substrate"

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Koteeswaran, Mohanalakshmi. "Substrate coupling macromodel for lightly doped CMOS processes." Thesis, 2002. http://hdl.handle.net/1957/31663.

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A scalable macromodel for substrate noise coupling in lightly doped substrates with and without a buried layer has been developed. This model is based on Z-parameters and is scalable with contact size and separation. This model requires process dependent parameters that can be extracted easily from a small number of device simulations or measurements. Once these parameters are known, the model can be used for any spacing between the injecting and sensing contacts and for different contact geometries. The model is validated with measurements for a lightly doped substrate with a buried layer and predicts the substrate resistance values to within 12%. The substrate resistances obtained using the model are also in close agreement with the three-dimensional simulations for a lightly doped substrate.<br>Graduation date: 2003
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張鴻儀. "Thermal oxidation of lightly and heavily doped silicon in N2O and it device applications." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/90267408402267604612.

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Sharma, Ajit. "Predictive methodologies for substrate parasitic extraction and modeling in heavily doped CMOS substrates." Thesis, 2003. http://hdl.handle.net/1957/31842.

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This thesis presents an automated methodology to calibrate the substrate profile for accurate prediction of substrate parasitics using Green's function based extractors. The technique requires fabrication of only a few test structures and results in an accurate three layered approximation of a heavily doped epitaxial silicon substrate. The obtained substrate resistances are accurate to about 10% of measurements. Advantages and limitations of several common measurement techniques used to measure substrate z-parameters and resistances are discussed. A new and accurate z-parameter based macro-model has been developed that can be used up to a few GHz for P��� for contacts that are as close as 2��m. This enhanced model also addresses the limitations of previous models with regards to implementation aspects and ease of integration in a CAD framework. Limitations of this modeling approach have been investigated. The calibration methodology can be used along with the scalable macromodel for a qualitative pre-design and pre-layout estimation of the digital switching noise that couples though the substrate to sensitive analog/RF circuits.<br>Graduation date: 2004
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Hsu, Shu-ching. "Analysis and modeling of substrate noise coupling for NMOS transistors in heavily doped substrates." Thesis, 2004. http://hdl.handle.net/1957/30203.

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This thesis examines substrate noise coupling for NMOS transistors in heavily doped substrates. The study begins with the analysis of an NMOS transistor switching noise in a digital inverter at the device level. A resistive substrate network for the NMOS transistor is proposed and verified. Coupling between N+- P+ contacts is compared both qualitatively and quantitatively with simulations. The difference between the N-P and P-P coupling is in the cross-coupling parameter. A new N-P model, which requires only five parameters, is proposed by taking advantage of an existing P-P model combined with the concept of a virtual separation. This model has been validated up to 2GHz with Medici simulations. The virtual separation concept has been validated with 2D/3D simulations and measurements from test structures fabricated in a 0.35μm TSMC CMOS heavily doped process. This model is useful when transistor switching noise is the dominant source of substrate noise. Applications of the new N-P model are demonstrated with circuit simulations.<br>Graduation date: 2004
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HUANG, GUO-SHENG, and 黃國昇. "The common models for conventional and lightly doped drain(LDD) MOSFET's:threshold voltage, drain current, substrate current, and transistor charges." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/83525941359268954334.

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博士<br>國立交通大學<br>電子研究所<br>78<br>In this thesis, the analytic common models for the threshold voltage, the drain current, the substrate current, and the transistor charges of both conventional and LDD MOSFET''s have been developed. In chapter 1, we will point out the fact that the LDD structure can reduce the high7 field effects existing in conventional. MOSFET''s but the extra parasitic resistance in the LDD structure, which is bias7 controlled, will reduce the transconductance and increase the saturation voltage. A set of test devices with conventional and LDD structures fabricated by ERSO, ITRI, have been measured and characterized. Observing from the features of the common model, the major applications are in circuit7 level analyses and simulations. Besides, the hints for device design can also be obtained by the common models due to their structure/process oriented features. In Chapter 2, the threshold7 voltage models for conventional and LDD MOSFET''s have been presented, in which the implanted channel profile is approximated by a step profile, and the short7 channel effect is modeled by combining a charge sharing scheme and the superposition of the bulk depleted charges. Considering the built7 in voltages across the setp junctions, the discontinuities of the threshold voltage have been eliminated. By replacing the heavily doped concentration of the source/drain regions to lightly doped drain doping, the threshold voltages of LDD MOSFET''s can be easily calculated. Although the disagreements of the threshold voltage for larger substrate biases can be observed from comparisons between the calculated and measured results. The deficiency is due to the assumption that the surface potential along the channel is constant. However, the developed threshold7 voltage moedls are still applicable for practical substrate biases. In Chapter 3, the drain7 current model for conventional MOSFET''s has been derived by considering field7 dependent mobility, short7 channel threshold voltage, implanted channel profile, and constant parasitic resistance. Based on the derivations for conventional MOSFET''s and taking the n-region as a buried7 channel MOSFET with a modified charge sharing scheme, the drain7 current model for LDD MOSFET''s has been developed. Besides, the drain currents for conventional and LDD MOSFET''s operated in the saturation region have been obtained by using one7 dimensional approximation. Using the parameters determined by a series of least7 square fittings, the calculated drain currents have been shown to satisfactorily agree with the measured data. In Chapter 4, the analytic substrate7 current models for conventional and LDD MOSFET''s have been developed by using the pseudo two7 dimensional approximation in the channel and drain regions to obtain both the channel length modulation factors and the maximum electric field. By using an existing simplified substrate current formula and the developed mzximum electric field, the substrate currents of conventional/ LDD MOSFET''s have been calculated. Besides, the drain current can also be self7 consistently calculated by using the I7 V moedl in Chapter 3 and the developed channel length modulation factor. Using a two7 dimensional numerical MOS device simulator, it has been shown that the accuracy of the developed maximum electric field model is acceptable for calculating the substrate currents of conventional/LDD MOSFET''s. Moreover, the parameters used in the substrate7 current models can be determined by the developed optimization technique. Comparing the calculated drain and substrate currents with the experimental data measured. form the test devices with conventional/LDD MOS structures, the developed substrate7 current models have been shown to be valid for wide ranges of channel lengths and bias conditions. Furthermore, the double7 hump characteristics of LDD MOSFET''s have been studied by using 27 D numerical slmulation. It has been shown that this phenomenon is due to the fact that the peak generation rate transfers from the channel/n-junction neat the drain side to the gate edge neat the source side. In Chapter 5, the analytic models for the intrinsic and extrinsic charges of conventional and LDD MOSFET''s have been presented. In our developed intrinsic charge model, a new parameter has been defined to smoothly connect the intrinsic charges and capacitances at the transition between the linear and saturation regions. In our developed extrinsic charge model,the n-region of LDD MOSFET''s has been modeled by three buried7 channel devices with a modified charge sharing scheme. The developed model for the n-region of LDD MOSFET''s can also be applied to the n+region of conventional MOSFET''s. In order to verify the accuracy of the developed analytic models for the intrinsic and extrinsic charges, a new calculation method for the intrinsic and extrinsic charges using 27 D numerical simulation has been presented. Comparisons of the calculated intrinsic and extrinsic charges between the developed analytic models and the numerical simulations have been made and satisfactory agreements are obtained. In Chapter 6, the major contributions and the proposed future researches have been described.
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Book chapters on the topic "Lightly and heavily doped substrate"

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Verghese, Nishath K., Timothy J. Schmerbeck, and David J. Allstot. "Substrate Modeling in Heavily-Doped Bulk Processes." In Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2239-3_6.

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Verghese, Nishath K., Timothy J. Schmerbeck, and David J. Allstot. "Controlling Substrate Coupling in Heavily-Doped Bulk Processes." In Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2239-3_9.

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Satou, A., Y. Koseki, V. Ryzhii, V. Vyurkov, and T. Otsuji. "Damping Mechanism of Terahertz Plasmons in Graphene on Heavily Doped Substrate *." In Graphene-Based Terahertz Electronics and Plasmonics. Jenny Stanford Publishing, 2020. http://dx.doi.org/10.1201/9780429328398-12.

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Conference papers on the topic "Lightly and heavily doped substrate"

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Korchnoy, Valentina. "Selective Etching of Heavily-Boron-Doped Si Substrate Using Lightly-Boron-Doped Si Epi as an Etch Stop Layer." In ISTFA 2015. ASM International, 2015. http://dx.doi.org/10.31399/asm.cp.istfa2015p0306.

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Abstract A sample preparation technique for flip chips (FC) deprocessing from the back side proposed. The technique uses HNA chemistry (consisting of a mixture of acids: hydrofluoric, nitric and acetic) to wet-etch the heavily-boron-doped Si bulk substrate selectively to the lightly-boron-doped Si epi. The procedure can be used as a FC device sample preparation technique for back-side optical probing and FIB editing.
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Sharma, Sanjay, R. P. Yadav, and Vijay Janyani. "Switching based evaluation of substrate current in lightly and heavily doped CMOS at 45nm." In 2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA). IEEE, 2016. http://dx.doi.org/10.1109/vlsi-sata.2016.7593058.

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Basu, S., B. J. Lee, and Z. M. Zhang. "Infrared Radiative Properties of Heavily Doped Silicon at Room Temperature." In ASME 2007 International Mechanical Engineering Congress and Exposition. ASMEDC, 2007. http://dx.doi.org/10.1115/imece2007-41266.

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This paper describes an experimental investigation on the infrared radiative properties of heavily-doped silicon (Si) at room temperature. Lightly-doped Si wafers were ion implanted with boron and phosphorus atoms to doping concentrations of 1×1020 and 1×1021 cm−3. Rapid thermal annealing was performed to activate the implanted dopants. A Fourier-transform infrared spectrometer was employed to measure the normal transmittance as well as reflectance of the samples in the spectral region from 2 to 20 μm. Accurate carrier mobility and ionization models were identified after carefully reviewing the available literature, and then incorporated into Drude model to predict the dielectric function of doped Si. The radiative properties of doped Si samples were calculated by treating the doped region as multilayer thin films of different doping concentrations on a thick Si substrate. The measured spectral transmittance and reflectance agree well with the model predictions. The results obtained from this study will facilitate the future applications of heavily-doped Si in semiconductor as well as MEMS devices.
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Chiang, Ching-Lang, Neeraj Khurana, Daniel T. Hurley, and Ken Teasdale. "Backside Emission Microscopy for Integrated Circuits on Heavily Doped Substrate." In ISTFA 1998. ASM International, 1998. http://dx.doi.org/10.31399/asm.cp.istfa1998p0447.

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Abstract Backside emission microscopy on heavily doped substrate materials was analyzed from the viewpoint of optical absorption by the substrate and sample preparation technique. Although it was widely believed that silicon is transparent to infrared (IR) radiation, we demonstrated by using published absorption data that silicon with doping levels above 5 x 1018cm-3 is virtually opaque, leaving only a narrow transmission window around the energy bandgap. Because the transmission depends exponentially on the thickness of die, thinning to below 100µm is shown to be required. Even an advanced IR sensor such as HgCdTe would find little light to detect without thinning the die. For imaging the circuit, an IR laser-based system produced poor images in which the diffraction patterns often ruined the contrast and obscured the image. Hence, a precise, controlled die thinning technique is required both for emission detection and backside imaging. A thinning and polishing technique was briefly described that was believed to be applicable to most ceramic packages. A software technique was employed to solve the image quality problem commonly encountered in backside imaging applications using traditional microscope light source and a scientific grade CCD camera. Finally, we showed the impact of die thickness on imaging circuits on a heavily doped n type substrate.
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Chandrasekhar, S., J. C. Campbell, A. G. Dentai, et al. "An Integrated InP/InGaAs Heterojunction Biploar Photoreceiver." In Integrated and Guided Wave Optics. Optica Publishing Group, 1989. http://dx.doi.org/10.1364/igwo.1989.tucc3.

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The rapid development of lightwave communications has created a demand for high-performance receivers for a variety of systems applications. For many of these applications, e. g. local area networks, cost is a primary consideration. It is expected that integration of the receiver components will eventually yield significant savings with little or no loss in performance. To date, most of the integrated receiver circuits that have been reported have combined p-i-n photodiodes with FET amplifier circuits1. Alternatives to the p-i-n/FET approach are a p-i-n or a phototransistor coupled to a bipolar amplifier circuit2. One motivation for the use of a phototransistor/bipolar configuration for integrated receiver circuits is better materials compatibility than p-i-n/FET circuits. A typical p-i-n photodiode structure consists of a lightly doped epitaxial absorbing layer on a heavily doped substrate. The FET amplifier circuit, on the other hand, requires a heavily doped channel on a semi-insulating substrate. In contrast, the phototransistor is functionally just a p-i-n photodiode integrated with a bipolar transistor in the common collector configuration and therefore can be fabricated from the same epitaxial layers used for a bipolar amplifier. Recently, Wang et al. have reported an all-bipolar photoreceiver for λ ≈ 0.85 μm consisting of a GaAs/AlGaAs heterojunction phototransistor (HPT) and GaAs/AlGaAs heterojunction bipolar (HBT) amplifier3. In this paper, we report, for the first time, an InP/InGaAs integrated receiver circuit which utilizes an HPT as the photodetector and a bipolar amplifier circuit. This circuit operates in the wavelength regions near 1.3 μm and 1.5 μm.
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Brown, T. G., Philip L. Bradfield, Dennis G. Hall, and R. A. Soref. "Optical confinement of bound exciton emission in a silicon epitaxial waveguide." In OSA Annual Meeting. Optica Publishing Group, 1987. http://dx.doi.org/10.1364/oam.1987.mp1.

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The widespread use of silicon in the microelectronics arena makes the notion of using silicon for integrated optics attractive. Several authors have reported schemes for making various kinds of optical waveguide in or on crystalline silicon. One approach is the epitaxial waveguide,1 in which a heavily doped substrate exhibits a depressed refractive index due to the high density of free carriers, but the guiding layer remains lightly doped and of good optical quality. Beryllium pairs form an isoelectronic complex in crystalline silicon that can bind an exciton. At sufficiently low temperatures (T = 30 K), this bound exciton radiates efficiently in a narrow line near the wavelength λ = 1.15 μm. We report the observation of optical confinement of subband gap radiation emitted by excitons bound to beryllium pairs introduced by ion implantation and suitable annealing. Photographs and transverse image scans show clear confinement of the emitted radiation within the 15.5-μm epitaxial layer.
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Schüppert, B., J. Schmidtchen, and K. Petermann. "Integrated-optical waveguides in silicon by germanium indiffusion." In Integrated Photonics Research. Optica Publishing Group, 1990. http://dx.doi.org/10.1364/ipr.1990.mi7.

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Silicon is an attractive material for monolithic integration of optical and electronic components for wavelengths above 1.1 μm. In this concept even laser diodes may be integrated by means of heteroepitaxy of III–V compounds on silicon, and detectors can be fabricated by heteroepitaxial growth of germanium1, whereas electronic components can be realized by standard techniques. Rib waveguides have been realized in Ref. 2 for an n/n + silicon and proposed in Ref. 3 for a Ge-doped epilayer grown on an undoped substrate. The basic idea of our technique for integrated-optical waveguides in silicon is to indiffuse an element with a larger refractive index than that of silicon into a lightly n-doped epilayer, which is grown on a heavily doped n+ substrate. Because losses increase with an increase of free carriers, the element for indiffusion must belong to group IV of the periodic system. Both conditions are met by Ge that is deposited as a GeSi alloy onto the epilayer, either by quasi-simultaneous evaporation of Ge x Si(1- x ) using a jumping E-beam or by evaporating a system of thin alternating Ge and Si layers. The channel waveguides are formed through standard lift-off techniques (Figs, 1a–1c). To avoid evaporation during diffusion, a SiO2-overlay is sputtered onto the epilayer (Fig. 1d). After diffusion at 1200C for 69 h (Fig. 1e) the SiO2 overlay is removed by etching (Fig. 1f). A typical depth profile of Ge is shown in Fig. 2, yielding a diffusion depth of d = 2.1 μm and a diffusion constant of D = 1.6 × 10-2 μm2/h. Various waveguides with different stripe widths, alloy ratios, and layer thicknesses have been fabricated, and the spot sizes have been measured to be in the range of 4–8 μm for the vertical and 6–12 μm for the horizontal spot. Fitting the measured vertical spot sizes to theoryyields the maximum index enhancement as a function of Ge content, which is shown in Fig. 3. The Ge content before indiffusion is given in terms of the product of the deposited layer thickness τ and the alloy ratio x from which the maximum Ge concentration at the surface after indiffusion can be calculated if we assume that the material is completely indiffused.
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Gerakis, Vasileios, and Alkis Hatzopoulos. "Interconnection coupling on lightly doped substrate for millimeter wave frequencies." In 2015 Conference on Design of Circuits and Integrated Systems (DCIS). IEEE, 2015. http://dx.doi.org/10.1109/dcis.2015.7388559.

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Suziedelis, A., S. Asmontas, J. Gradauskas, et al. "Pulsed microwave sensor on heavily doped semiconductor substrate." In 2017 Progress in Electromagnetics Research Symposium - Fall (PIERS - FALL). IEEE, 2017. http://dx.doi.org/10.1109/piers-fall.2017.8293286.

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Wang, Yongsheng, Shanshan Liu, Fang Li, Fengchang Lai, and Mingyan Yu. "Modeling of substrate coupling noise in lightly doped mixed-signal ICs." In 2012 International Conference on Optoelectronics and Microelectronics (ICOM). IEEE, 2012. http://dx.doi.org/10.1109/icoom.2012.6316320.

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Reports on the topic "Lightly and heavily doped substrate"

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Wu, A., R. D. Schrimpf, R. L. Pease, D. M. Fleetwood, and S. L. Kosier. Radiation-induced gain degradation in lateral PNP BJTs with lightly and heavily doped emitters. Office of Scientific and Technical Information (OSTI), 1997. http://dx.doi.org/10.2172/491557.

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