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Journal articles on the topic 'Linear feedback shift registers'

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Published: 4 June 2021
Last updated: 31 January 2023

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1

Chen. "Linear Dependencies in Linear Feedback Shift Registers." IEEE Transactions on Computers C-35, no. 12 (December 1986): 1086–88. http://dx.doi.org/10.1109/tc.1986.1676718.

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2

Poluyanenko, Nikolay. "DEVELOPMENT OF THE SEARCH METHOD FOR NON-LINEAR SHIFT REGISTERS USING HARDWARE, IMPLEMENTED ON FIELD PROGRAMMABLE GATE ARRAYS." EUREKA: Physics and Engineering 1 (January 31, 2017): 53–60. http://dx.doi.org/10.21303/2461-4262.2017.00271.

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The nonlinear feedback shift registers of the second order inare considered, because based on them it can be developed a generator of stream ciphers with enhanced cryptographic strength. Feasibility of nonlinear feedback shift register search is analyzed. These registers form a maximal length sequence, using programmable logic devices. Performance evaluation of programmable logic devices in the generation of pseudo-random sequence by nonlinear feedback shift registers is given. Recommendations to increase this performance are given. The dependence of the maximum generation rate (clock frequency), programmable logic devices on the number of concurrent nonlinear registers is analyzed. A comparison of the generation rate of the sequences that are generated by nonlinear feedback shift registers is done using hardware and software. The author suggests, describes and explores the search method of nonlinear feedback shift registers, generating a sequence with a maximum period. As the main result are found non-linear 26, 27, 28 and 29 degrees polynomials.
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3

Aloisi, W., and R. Mita. "Gated-Clock Design of Linear-Feedback Shift Registers." IEEE Transactions on Circuits and Systems II: Express Briefs 55, no. 6 (June 2008): 546–50. http://dx.doi.org/10.1109/tcsii.2007.914901.

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4

Jung, Jaehwan, Hoyoung Yoo, Youngjoo Lee, and In-Cheol Park. "Efficient Parallel Architecture for Linear Feedback Shift Registers." IEEE Transactions on Circuits and Systems II: Express Briefs 62, no. 11 (November 2015): 1068–72. http://dx.doi.org/10.1109/tcsii.2015.2456294.

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5

Moon, T. K., and S. Veeramachaneni. "Linear feedback shift registers as vector quantisation codebooks." Electronics Letters 35, no. 22 (1999): 1919. http://dx.doi.org/10.1049/el:19991335.

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6

Tsaban, Boaz, and Uzi Vishne. "Efficient Linear Feedback Shift Registers with Maximal Period." Finite Fields and Their Applications 8, no. 2 (April 2002): 256–67. http://dx.doi.org/10.1006/ffta.2001.0339.

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7

FUJIWARA, Hideo, Katsuya FUJIWARA, and Toshinori HOSOKAWA. "Universal Testing for Linear Feed-Forward/Feedback Shift Registers." IEICE Transactions on Information and Systems E103.D, no. 5 (May 1, 2020): 1023–30. http://dx.doi.org/10.1587/transinf.2019edp7205.

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8

Rajski, J., and J. Tyszer. "On the diagnostic properties of linear feedback shift registers." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10, no. 10 (1991): 1316–22. http://dx.doi.org/10.1109/43.88927.

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9

Hamid, M. E., and Chien-In Henry Chen. "A note to low-power linear feedback shift registers." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 45, no. 9 (1998): 1304–7. http://dx.doi.org/10.1109/82.718599.

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10

Ayinala, Manohar, and Keshab K. Parhi. "High-Speed Parallel Architectures for Linear Feedback Shift Registers." IEEE Transactions on Signal Processing 59, no. 9 (September 2011): 4459–69. http://dx.doi.org/10.1109/tsp.2011.2159495.

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11

Baragaña, Itziar, and Alicia Roca. "Linear feedback shift registers and the minimal realization problem." Linear Algebra and its Applications 576 (September 2019): 200–227. http://dx.doi.org/10.1016/j.laa.2018.06.009.

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12

Kalyvas, Marios, Kostas Yiannopoulos, Thanassis Houbavlis, and Hercules Avramopoulos. "Design Algorithm of All-Optical Linear Feedback Shift Registers." AEU - International Journal of Electronics and Communications 57, no. 5 (January 2003): 328–32. http://dx.doi.org/10.1078/1434-8411-54100179.

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13

Shin, Hwasoo, Soyeon Choi, Jiwoon Park, Byeong Yong Kong, and Hoyoung Yoo. "Area-Efficient Error Detection Structure for Linear Feedback Shift Registers." Electronics 9, no. 1 (January 20, 2020): 195. http://dx.doi.org/10.3390/electronics9010195.

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This paper presents a novel error detection linear feedback shift register (ED-LFSR), which can be used to realize error detection with a small hardware overhead for various applications such as error-correction codes, encryption algorithms and pseudo-random number generation. Although the traditional redundancy methods allow the incorporation of the error detection/correction capability in the original LFSRs, they suffer from a considerable amount of hardware overheads. The proposed ED-LFSR alleviates such problems by employing the parity check technique. The experimental results indicate that the proposed ED-LFSR requires an additional area of only 31.1% compared to that required by the conventional LFSR and it saves 39.1% and 31.9% of the resources compared to the corresponding utilization of the hardware and time redundancy methods.
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14

Lin, Zhiqiang. "On two circuit configurations of non-linear feedback shift registers." International Journal of Information and Communication Technology 7, no. 2/3 (2015): 185. http://dx.doi.org/10.1504/ijict.2015.068378.

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15

Zhang, Xinmiao. "A Low-Power Parallel Architecture for Linear Feedback Shift Registers." IEEE Transactions on Circuits and Systems II: Express Briefs 66, no. 3 (March 2019): 412–16. http://dx.doi.org/10.1109/tcsii.2018.2860934.

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16

Xu, Hong, Yonghui Zheng, and Xuejia Lai. "Construction of perfect diffusion layers from linear feedback shift registers." IET Information Security 9, no. 2 (March 1, 2015): 127–35. http://dx.doi.org/10.1049/iet-ifs.2013.0411.

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17

Gai, Silvano, Antonio Lioy, and Fabio Neri. "VLSI implementation of linear feedback shift registers for microprocessor applications." Microprocessing and Microprogramming 18, no. 1-5 (December 1986): 435–40. http://dx.doi.org/10.1016/0165-6074(86)90074-8.

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18

Awasthi, Ambrish, and Rajendra K. Sharma. "Primitive transformation shift registers over finite fields." Journal of Algebra and Its Applications 18, no. 09 (July 17, 2019): 1950171. http://dx.doi.org/10.1142/s0219498819501718.

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Linear feedback shift registers (LFSRs) are widely used cryptographic primitives for generating pseudorandom sequences. Here, we consider systems which are efficient generalizations of LFSRs and produce pseudorandom vector sequences. We study problems related to the cardinality, existence and construction of these systems and give certain results in this direction.
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19

Journal, Baghdad Science. "Stochastic Non-Linear Pseudo-Random Sequence Generator." Baghdad Science Journal 7, no. 2 (June 6, 2010): 1042–46. http://dx.doi.org/10.21123/bsj.7.2.1042-1046.

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Many of the key stream generators which are used in practice are LFSR-based in the sense that they produce the key stream according to a rule y = C(L(x)), where L(x) denotes an internal linear bit stream, produced by small number of parallel linear feedback shift registers (LFSRs), and C denotes some nonlinear compression function. In this paper we combine between the output sequences from the linear feedback shift registers with the sequences out from non linear key generator to get the final very strong key sequence
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20

Lurina, Manda, Sugondo Hadiyoso, and Rina Pudji Astuti. "Scrambling and De-Scrambling Implementation Using Linear Feedback Shift Register Method on FPGA." IJAIT (International Journal of Applied Information Technology) 1, no. 02 (August 14, 2017): 59–67. http://dx.doi.org/10.25124/ijait.v1i02.876.

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communication system, a long sequence of bits ‘0’ or ‘1’ will inherits the loss of bit synchronization, and hence it can cause the false detection on the receiver. To avoid this, long sequence of bits will be randomized first so that long sequence of bits ‘0’ or ‘1’ can be removed. This randomization process is called scrambling and the circuit that works for the process is a scrambler. In the receiver there is a descrambler that serves to return the bits to their original information. This paper presents a design of scrambler and descrambler using a combination of Linear Feedback Shift Register (LFSR) with 15 registers, XOR logic gates, and Pseudo Random Binary Sequence (PRBS) generator structure with polynomial 1 + x14 + x15. One of the two main parts of LFSR is the shift register while the other is the feedback. In LFSR, the bits contained within the selected position in the shift register will be combined in a function and the result will be put back into this register's input bit. Feedback also makes the system more stable and no error occurrence. Then special tap is taken from a certain point in XOR and returned as a feedback register. The system is implemented on FPGA board Altera De0-Nano EP4CE22F17C6 Cyclone IV E. Resource memory required <1% of available memory. Bit rate that can be achieved with clock speed 50MHz is 335570.47 bps.
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21

Williams, T. W., W. Daehn, M. Gruetzner, and C. W. Starke. "Bounds and analysis of aliasing errors in linear feedback shift registers." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 7, no. 1 (1988): 75–83. http://dx.doi.org/10.1109/43.3132.

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22

Lowy, M. "Parallel implementation of linear feedback shift registers for low power applications." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 43, no. 6 (June 1996): 458–66. http://dx.doi.org/10.1109/82.502318.

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23

Ghorpade, Sudhir R., Sartaj Ul Hasan, and Meena Kumari. "Primitive polynomials, singer cycles and word-oriented linear feedback shift registers." Designs, Codes and Cryptography 58, no. 2 (April 6, 2010): 123–34. http://dx.doi.org/10.1007/s10623-010-9387-7.

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24

Guha, A., and L. L. Kinney. "Relating the cyclic behavior of linear and intrainverted feedback shift registers." IEEE Transactions on Computers 41, no. 9 (1992): 1088–100. http://dx.doi.org/10.1109/12.165391.

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25

Moulood, Kholood J. "New Address Shift Linear Feedback Shift Register Generator." Journal of Al-Nahrain University-Science 20, no. 3 (March 2017): 139–45. http://dx.doi.org/10.22401/jnus.20.1.20.

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26

Vielhaber, Michael, Mónica del Pilar Canales Chacón, and Sergio Jara Ceballos. "Rational complexity of binary sequences, F$\mathbb {Q}$SRs, and pseudo-ultrametric continued fractions in $\mathbb {R}$." Cryptography and Communications 14, no. 2 (November 15, 2021): 433–57. http://dx.doi.org/10.1007/s12095-021-00539-2.

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AbstractWe introduce rational complexity, a new complexity measure for binary sequences. The sequence s ∈ Bω is considered as binary expansion of a real fraction $s \equiv {\sum }_{k\in \mathbb {N}}s_{k}2^{-k}\in [0,1] \subset \mathbb {R}$ s ≡ ∑ k ∈ ℕ s k 2 − k ∈ [ 0 , 1 ] ⊂ ℝ . We compute its continued fraction expansion (CFE) by the Binary CFE Algorithm, a bitwise approximation of s by binary search in the encoding space of partial denominators, obtaining rational approximations r of s with r → s. We introduce Feedback in$\mathbb {Q}$ ℚ Shift Registers (F$\mathbb {Q}$ ℚ SRs) as the analogue of Linear Feedback Shift Registers (LFSRs) for the linear complexity L, and Feedback with Carry Shift Registers (FCSRs) for the 2-adic complexity A. We show that there is a substantial subset of prefixes with “typical” linear and 2-adic complexities, around n/2, but low rational complexity. Thus the three complexities sort out different sequences as non-random.
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27

Al-Hejri, Ibraheem, and Sultan Almuhammadi. "Constructing New NLFSR Functions with Optimal Periods." International Journal of Interdisciplinary Telecommunications and Networking 12, no. 2 (April 2020): 71–80. http://dx.doi.org/10.4018/ijitn.2020040106.

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Pseudorandom bit generators are essential components in many security applications. The security of the system relies on the security of its components. Feedback shift registers are commonly used to generate pseudorandom bits. Nonlinear feedback shift registers (NLFSRs) are known to be more secure than the linear ones. However, there is no mathematical foundation on how to construct NLFSR feedback functions with optimal periods. This article considers a new type of NLFSR capable of constructing feedback functions of degree 3 with optimal periods. Using their construction method, the authors propose new functions of this type.
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28

Cotrina, Guillermo, Alberto Peinado, and Andrés Ortiz. "Gaussian Pseudorandom Number Generator Based on Cyclic Rotations of Linear Feedback Shift Registers." Sensors 20, no. 7 (April 8, 2020): 2103. http://dx.doi.org/10.3390/s20072103.

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This paper presents a new proposal to generate optimal pseudorandom numbers with Gaussian distribution. The generator is especially designed for low-cost hardware implementation, although the software version is also considered. For this reason, Linear Feedback Shift Registers in conjunction with cyclic rotations are employed. The proposal presents a low implementation cost and overcomes the limitations of the previous Gaussian generators based on linear feedback shift registers by means of a less complex algorithm to find optimal configurations. As a consequence, it turns into a really usable generator. Moreover, a further improvement, based on the simulated annealing algorithm, is applied in order for the random values to be better adjusted to the normal distribution.
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29

Cotrina, Guillermo, Alberto Peinado, and Andrés Ortiz. "Gaussian Pseudorandom Number Generator Using Linear Feedback Shift Registers in Extended Fields." Mathematics 9, no. 5 (March 6, 2021): 556. http://dx.doi.org/10.3390/math9050556.

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A new proposal to generate pseudorandom numbers with Gaussian distribution is presented. The generator is a generalization to the extended field GF(2n) of the one using cyclic rotations of linear feedback shift registers (LFSRs) originally defined in GF(2). The rotations applied to LFSRs in the binary case are no longer needed in the extended field due to the implicit rotations found in the binary equivalent model of LFSRs in GF(2n). The new proposal is aligned with the current trend in cryptography of using extended fields as a way to speed up the bitrate of the pseudorandom generators. This proposal allows the use of LFSRs in cryptography to be taken further, from the generation of the classical uniformly distributed sequences to other areas, such as quantum key distribution schemes, in which sequences with Gaussian distribution are needed. The paper contains the statistical analysis of the numbers produced and a comparison with other Gaussian generators.
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30

Krishnaswamy, Srinivasan, and Harish K. Pillai. "On the Number of Linear Feedback Shift Registers With a Special Structure." IEEE Transactions on Information Theory 58, no. 3 (March 2012): 1783–90. http://dx.doi.org/10.1109/tit.2011.2174332.

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31

Vasanthavada, N. S. "Group parity prediction scheme for concurrent testing of linear feedback shift registers." Electronics Letters 21, no. 2 (1985): 67. http://dx.doi.org/10.1049/el:19850046.

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32

Zeng, Guang, Wenbao Han, and Kaicheng He. "Analysis of the design methods of word oriented linear feedback shift registers." Wuhan University Journal of Natural Sciences 13, no. 6 (November 8, 2008): 712–16. http://dx.doi.org/10.1007/s11859-008-0615-1.

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33

Savir, J., and W. H. McAnney. "A multiple seed linear feedback shift register." IEEE Transactions on Computers 41, no. 2 (1992): 250–52. http://dx.doi.org/10.1109/12.123404.

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34

Melnyk, Oleksandr, Andriy Mykolushko, and Arsen Myshynskyi. "Nanocircuits for Protection of the Cipher Information." Electronics and Control Systems 1, no. 67 (May 12, 2021): 61–68. http://dx.doi.org/10.18372/1990-5548.67.15607.

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While using side-channel attacks, cipher devices was defenseless to power and electromagnetic analysis attacks. These attacks are due to the use of low cost equipment. Currently, most of the cipher circuits are implemented on complementary metal-oxide-semiconductor. The disadvantage is the relationship between the data processing the curcuit to energy consumption. When processing the CMOS transistor logic "1" and the logic "0", through the transistor passes a different volume of current. If don't implement significant counteractions, it will allow another person to decrypt the key of the cipher module. A new logical approach to quantum-dot cellular automata and single-electron transistors is explored. The proposed approach has low power consumption and complicated clocking circuits. In theory and practice of cipher protection one of the key problems is the formation of binary pseudorandom sequences of maximum length of acceptable statistical characteristics. Generators of pseudorandom sequences usually based on linear shift registers with linear feedback. Here expanded the concept of linear shift register, believing that his every category (memory cell) can be in one of the states. Call registers are "generalized linear shift registers".
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35

Ndaw, Babacar, Djiby Sow, and Mamadou Sanghare. "Construction of Maximum Period Linear Feedback Shift Registers (LFSR) (Primitive Polynomials and Linear Recurring Relations)." British Journal of Mathematics & Computer Science 11, no. 4 (January 10, 2015): 1–24. http://dx.doi.org/10.9734/bjmcs/2015/19442.

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36

Peinado, A., and A. Fúster-Sabater. "Generation of pseudorandom binary sequences by means of linear feedback shift registers (LFSRs) with dynamic feedback." Mathematical and Computer Modelling 57, no. 11-12 (June 2013): 2596–604. http://dx.doi.org/10.1016/j.mcm.2011.07.023.

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37

Garbolino, Tomasz. "A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures." Applied Sciences 11, no. 20 (October 12, 2021): 9476. http://dx.doi.org/10.3390/app11209476.

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Digital cores that are currently incorporated into advanced Systems on Chip (SoC) frequently include Logic Built-In Self-Test (LBIST) modules with the Self-Test Using MISR/Parallel Shift Register Sequence Generator (STUMPS) architecture. Such a solution always comprises a Pseudo-Random Pattern Generator (PRPG), usually designed as a Linear Feedback Shift Register (LFSR) with a phase shifter attached to the register and arranged as a network of XOR gates. This study discloses an original and innovative structure of such a PRPG unit referred to as the DT-LFSR-TPG module that needs no phase shifter. The module is designed as a set of identical linear registers of the DT-LFSR type with the same primitive polynomial. Each register has a form of a ring made up exclusively of D and T flip-flops. This study is focused on the investigation of those parameters of DT-LFSR registers that are essential to use these registers as components of PRPG modules. The investigated parameters include phase shifts and the correlation between sequences of bits appearing at outputs of T flip-flops, implementation cost, and the maximum frequency of the register operation. It is demonstrated that PRPG modules of the DT-LFSR-TPG type enable much higher phase shifts and substantially higher operation frequencies as compared to competitive solutions. Such modules can also drive significantly more scan paths than other PRPGs described in reference studies and based on phase shifters. However, the cost of the foregoing advantages of DT-LFSR-TPG modules is the larger hardware overhead associated with the implementation of the solution proposed.
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38

bin Rosly, Hasrul Nisham, Mamun bin Ibne Reaz, Noorfazila Kamal, and Fazida Hanim Hashim. "Design and Analysis of CMOS Linear Feedback Shift Registers for Low Power Application." Applied Mechanics and Materials 833 (April 2016): 111–18. http://dx.doi.org/10.4028/www.scientific.net/amm.833.111.

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Chip manufacturing technologies have been a key to the growth in all electronics devices over the past decade, bringing added convenience and accessibility through advantages in cost, size, and power consumption. Using recent CMOS technology, LFSR is implemented until layout level which develops low power application. One of the most frequent uses of a LFSR inside a FPGA is as a counter. Using a LFSR instead of a binary counter can increase the clock rate considerably due to the low routing resource required to produce the next state logic. This paper explores the LFSR using different architecture in a 0.18μm CMOS technology. There are 3 type architecture implemented into LFSR which is NAND gates, pass transistor and transmission gates. Those LFSR are compare in term of CMOS layout, hardware implementation and power consumption using Mentor Graphics tools. Thus, it provides analysis of LFSR for low power application in CMOS VLSI.
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39

Matsui, Hajime. "Lemma for Linear Feedback Shift Registers and DFTs Applied to Affine Variety Codes." IEEE Transactions on Information Theory 60, no. 5 (May 2014): 2751–69. http://dx.doi.org/10.1109/tit.2014.2311042.

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40

Liu, X. B., C. C. Chui, S. N. Koh, and X. W. Wu. "Primitive polynomials for robust linear feedback shift registers-based scramblers and stream ciphers." IET Information Security 6, no. 3 (September 1, 2012): 183–89. http://dx.doi.org/10.1049/iet-ifs.2011.0215.

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41

Negi, Dr Ashish. "Cryptography Playfair Cipher using Linear Feedback Shift Register." IOSR Journal of Engineering 02, no. 05 (May 2012): 1212–16. http://dx.doi.org/10.9790/3021-020512121216.

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42

Mukherjee, Nilanjan, Janusz Rajski, Grzegorz Mrugalski, Artur Pogiel, and Jerzy Tyszer. "Ring Generator: An Ultimate Linear Feedback Shift Register." Computer 44, no. 6 (June 2011): 64–71. http://dx.doi.org/10.1109/mc.2010.334.

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43

Wang, L. T., and E. J. McCluskey. "Linear feedback shift register design using cyclic codes." IEEE Transactions on Computers 37, no. 10 (1988): 1302–6. http://dx.doi.org/10.1109/12.5994.

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44

Chen, Chien-In Henry, and Yingjie Zhou. "Configurable 2-D Linear Feedback Shift Registers for VLSI Built-in Self-test Designs." VLSI Design 11, no. 2 (January 1, 2000): 149–59. http://dx.doi.org/10.1155/2000/60904.

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Recently a multiple-sequence test generator was presented based on two-dimensional linear feedback shift registers (2-D LFSR). This generator can generate a set of precomputed test vectors obtained by an ATPG tool for detecting random-pattern-resistant faults and particular hard-to-detect faults. In addition, it can generate better random patterns than a conventional LFSR. In this paper we describe an optimized BIST scheme which has a configurable 2-D LFSR structure. Starting from a set of stuck-at faults and a corresponding set of test vectors detecting these faults, the corresponding test pattern generator is determined automatically. A synthesis procedure of designing this test generator is presented. Experimental results show that the hardware overhead is considerably reduced compared with 2-D LFSR generators.
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45

Pesoshin, V. A., V. M. Kuznetsov, and D. V. Shirshova. "Generators of the equiprobable pseudorandom nonmaximal-length sequences based on linear-feedback shift registers." Automation and Remote Control 77, no. 9 (September 2016): 1622–32. http://dx.doi.org/10.1134/s0005117916090095.

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46

Kokolakis, I., I. Andreadis, and Ph Tsalides. "Comparison between cellular automata and linear feedback shift registers based pseudo-random number generators." Microprocessors and Microsystems 20, no. 10 (July 1997): 643–58. http://dx.doi.org/10.1016/s0141-9331(97)00009-4.

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47

Morales-Sandoval, M., C. Feregrino-Uribe, and P. Kitsos. "Bit-serial and digit-serial GF(2m) Montgomery multipliers using linear feedback shift registers." IET Computers & Digital Techniques 5, no. 2 (2011): 86. http://dx.doi.org/10.1049/iet-cdt.2010.0021.

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48

Manju Bhargavi, K., and B. Sreekanth Reddy. "Low Power Linear Feedback Shift Register Using DY-CML." ECS Transactions 107, no. 1 (April 24, 2022): 15545–54. http://dx.doi.org/10.1149/10701.15545ecst.

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A Linear Feedback Shift Register (LFSR) is a sequential shift register that cycles through a succession of binary values in a pseudo-random way using combinational logic. Pseudo-noise sequences, whitening sequences, and fast digital counters are some of the applications of LFSR. The design of a 4-bit LFSR employing CMOS, MOS Current-Mode Logic (MCML), and Dynamic Current-Mode Logic (DY-CML) approaches are shown in this paper. MCML has low power consumption and better performance. The disadvantage of MCML approach is that it has more static power dissipation due to the constant current source. In order to solve the issues of MCML approach, the DY-CML with a dynamic current source is used to design the LFSR. All designs are simulated using the Mentor graphics tool, which uses 90nm technology. This paper also includes a comparison of LFSR’s in terms of power, delay, and transistor count.
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49

DHARMENDRA, SINGH, SINGH ANKIT, AGRAWAL PRACHI, and AGRAWAL HARSHITA. "LOW POWER OPTIMIZATION TECHNIQUE BASED LINEAR FEEDBACK SHIFT REGISTER." i-manager's Journal on Circuits and Systems 6, no. 1 (2018): 20. http://dx.doi.org/10.26634/jcir.6.1.14058.

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50

singh, Abhishek, Shekhar Verma, and Geetam Singh Tomar. "Secure Linear Feedback Shift Register based IPv6 in VANET." International Journal of Security and Its Applications 10, no. 2 (February 28, 2016): 423–36. http://dx.doi.org/10.14257/ijsia.2016.10.2.36.

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