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Nghe, Brandon K. "Cascaded Linear Regulator with Positive Voltage Tracking Switching Regulator." DigitalCommons@CalPoly, 2020. https://digitalcommons.calpoly.edu/theses/2173.
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This thesis presents the design, simulation, and hardware implementation of a proposed method for improving efficiency of voltage regulator. Typically, voltage regulator used for noise-sensitive and low-power applications involves the use of a linear regulator due to its high power-supply rejection ratio properties. However, the efficiency of a linear regulator depends heavily on the difference between its input voltage and output voltage. A larger voltage difference across the linear regulator results in higher losses. Therefore, reducing the voltage difference is the key in increasing regulator’s efficiency. In this thesis, a pre switching regulator stage with positive voltage tracking cascaded to a linear regulator is proposed to provide an input voltage to a linear regulator that is slightly above the output of the linear regulator. The tracking capability is needed to provide the flexibility in having different positive output voltage levels while maintaining high overall regulator’s efficiency. Results from simulation and hardware implementation of the proposed system showed efficiency improvement of up to 23% in cases where an adjustable output voltage is necessary. Load regulation performance of the proposed method was also overall better compared to the case without the output voltage tracking method.
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Lei, Ernest. "Cascaded Linear Regulator with Negative Voltage Tracking Switching Regulator." DigitalCommons@CalPoly, 2020. https://digitalcommons.calpoly.edu/theses/2176.
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DC-DC converters can be separated into two main groups: switching converters and linear regulators. Linear regulators such as Low Dropout Regulators (LDOs) are straightforward to implement and have a very stable output with low voltage ripple. However, the efficiency of an LDO can fluctuate greatly, as the power dissipation is a function of the device’s input and output. On the other hand, a switching regulator uses a switch to regulate energy levels. These types of regulators are more versatile when a larger change of voltage is needed, as efficiency is relatively stable across larger steps of voltages. However, switching regulators tend to have a larger output voltage ripple, which can be an issue for sensitive systems. An approach to utilize both in cascaded configuration while providing a negative output voltage will be presented in this paper. The proposed two-stage conversion system consists of a switching pre-regulator that can track the negative output voltage of the second stage (LDO) such that the difference between input and output voltages is always kept small under varying output voltage while maintaining the high overall conversion efficiency. Computer simulation and hardware results demonstrate that the proposed system can track the negative output voltage well. Additionally, the results show that the proposed system can provide and maintain good overall efficiency, load regulation, and output voltage ripple across a wide range of outputs.
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Bryndza, Ivan. "Návrh interního napěťového regulátoru pro automobilové aplikace." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-318167.
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This work contains topology and circuit design of a linear voltage regulator with respect to suppression of disturbances coming from supplied circuit into the input of the regulator. The converter is designed for integration in automotive sensor applications.
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Šojdr, Marek. "Návrh nízko-příkonového interního napěťového regulátoru pro automobilové aplikace." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2019. http://www.nusl.cz/ntk/nusl-399493.
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This master’s thesis deals with the design of integrated voltage regulator. Topologies of linear voltage regulators and their stability are discussed. Part of the thesis deals with description and simulation of blocks of selected regulator topology. The thesis describes the difficulties of integrated circuit design in the automotive industry. The electrical scheme of the designed regulator is explained. The work also focuses on the stability of designed regulator. Then presents simulations. It discusses the layout of integrated circuits and the designed voltage regulator.
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Štibraný, Miroslav. "Řízený laboratorní zdroj." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-240809.
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Master’s thesis deals with design of laboratory supply with precise voltage and current measuring. At the beginning it presents properties, advantages and disadvantages of linear and switching supplies, based on these facts it chooses a linear type of regulator. The design continues with detailed description of power and control analog and digital circuits. The thesis includes description of taking control over the supply from the front panel or through computer. The last part is devoted to measurement results and to presentation of some static and dynamic parameters of the designed supply.
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Burgardt, Ismael. "Conversor SEPIC empregando um snubber regenerativo associado a um regulador linear de corrente para acionar e controlar LEDs de potência." Universidade Tecnológica Federal do Paraná, 2015. http://repositorio.utfpr.edu.br/jspui/handle/1/1467.
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CAPES<br>Este trabalho apresenta um sistema eletrônico com entrada universal utilizando um retificador SEPIC não isolado para fornecer e controlar a corrente de LEDs de potência. Um Snubber regenerativo que reduz as perdas de comutação e melhora a eficiência do sistema é proposto. Para realizar a dimerização, bem como reduzir a ondulação da corrente nos LEDs, um regulador linear de corrente é conectado na saída do conversor SEPIC. A utilização do regulador linear também permite que o conversor opere com entrada universal sem a utilização de circuitos adicionais. Para evitar perdas excessivas, o regulador é configurado para operar na região limiar da regulação. O ponto de perda mínimo do regulador é ajustado através de um circuito detector de mínimo com o sistema operando em malha fechada. As etapas de operação, as formas de onda e as principais equações do snubber regenerativo aplicado ao SEPIC são descritas no trabalho. Para verificar e validar a análise teórica são apresentados dois protótipos com potências de saída de 42 W e 145 W, variando de 15% a 100%, para o conversor operando com tensão de entrada de 90 a 240 V e alimentado 35 LEDs conectados em série.<br>This paper presents a universal-input AC electronic lighting system using a non-isolated SEPIC PFC rectifier to drive and control power LEDs currents. One energy regenerative snubber for reducing the converter switching losses and improve the system efficiency is proposed. The dimmable flicker-free current in the LEDs array is obtained through a linear current regulator placed in the SEPIC’s output terminals. In order to reduce the efficiency impairment, the conditions for achieving minimum energy loss in the current regulator are also detailed. Point of minimum energy loss in the linear regulator is adjusted through valley detector circuit in closed loop system operation. The operation stages as well as the theoretical waveforms and main equations at steady state of the proposed SEPIC rectifier using the regenerative snubber are described. To verify the theoretical analysis carried out, experimental results of two prototypes (42 W and 145 W) operating from 90 to 240 V and output power from 15 to 100% for 35 LEDs are also presented.
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Tejmlová, Lenka. "Laboratorní zdroj s vysokou účinností." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219100.
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The project shows the problems of power supply in electrical engineering. It describes the general parameters of these types of supplies and presents their characteristics. Based on these findings, it is also focused on the selection of specific elements of the laboratory supply, to reach the given parameters. It contains the recalculations of the parameters of other additional components. The overall scheme of the supply is divided into several blocks, thematically corresponded to subchapters. According to the accomplished concept the laboratory supply is realized and its parameters had been tested. Projects results are assessed at the end.
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Twining, Erika. "Voltage compensation in weak distribution networks using shunt connected voltage source converters." Monash University, Dept. of Electrical and Computer Systems Engineering, 2004. http://arrow.monash.edu.au/hdl/1959.1/9701.
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Resener, Mariana. "Modelo linearizado para problemas de planejamento da expansão de sistemas de distribuição." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/156487.
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Este trabalho apresenta um modelo linearizado para ser utilizado em problemas de planejamento da expansão de sistemas de distribuição de energia elétrica (SDEE) com geração distribuída (GD), em um horizonte de curto prazo. O ponto de operação em regime permanente é calculado através de um modelo linearizado da rede, sendo as cargas e geradores representados por injeções constantes de corrente, o que torna possível calcular as correntes nos ramos e as tensões nas barras através de expressões lineares. As alternativas de expansão consideradas são: (i) alocação de bancos de capacitores; (ii) alocação de reguladores de tensão; e (iii) recondutoramento. Ainda, o modelo considera a possibilidade de seleção do tap dos transformadores de distribuição como alternativa para a redução das violações de tensão. A flexibilidade do modelo permite obter soluções considerando a contribuição das GDs no controle de tensão e potência reativa sem a necessidade de especificar uma tensão para a barra da subestação. O modelo de otimização proposto para a solução destes problemas utiliza uma função objetivo linear, além de restrições lineares e variáveis contínuas e binárias. Dessa forma, o modelo de otimização pode ser representado como um problema de programação linear inteira mista (PLIM) A função objetivo considera a minimização dos custos de investimento (aquisição, instalação e remoção de equipamentos e aquisição de condutores) e dos custos de operação, que correspondem aos custos anuais de manutenção somados aos custos das perdas de energia e das violações dos limites de tensão. A variação da carga é representada através de curvas de duração, sendo que os custos das perdas e das violações são ponderados pela duração de cada nível de carregamento. Utilizando uma abordagem de PLIM, sabe-se que existem condições suficientes que garantem a otimalidade de uma dada solução factível, além de permitir que a solução seja obtida através de métodos de otimização clássica. O modelo proposto foi implementado na linguagem de programação OPL e resolvido utilizando o solver comercial CPLEX. O modelo foi validado através da comparação dos resultados obtidos para cinco sistemas de distribuição com os resultados obtidos utilizando um fluxo de carga convencional. Os casos analisados e os resultados obtidos demonstram a precisão do modelo proposto e seu potencial de aplicação.<br>This work presents a linearized model to be used in short-term expansion planning problems of power distribution systems (PDS) with distributed generation (DG). The steady state operation point is calculated through a linearized model of the network, being the loads and generators modeled as constant current injections, which makes it possible to calculate the branch currents and bus voltages through linear expressions. The alternatives considered for expansion are: (i) capacitor banks placement; (ii) voltage regulators placement; and (iii) reconductoring. Furthermore, the model considers the possibility of adjusting the taps of the distribution transformers as an alternative to reduce voltage violations. The flexibility of the model enables solutions that includes the contribution of DGs in the control of voltage and reactive power without the need to specify the substation voltage. The optimization model proposed to solve these problems uses a linear objective function, along with linear constraints, binary and continuous variables. Thus, the optimization model can be represented as a mixed integer linear programming problem (MILP) The objective function considers the minimization of the investment costs (acquisition, installation and removal of equipment and acquisition of conductors) and the operation costs, which corresponds to the annual maintenance cost plus the costs related to energy losses and violation of voltage limits. The load variation is represented by discrete load duration curves and the costs of losses and voltage violations are weighted by the duration of each load level. Using a MILP approach, it is known that there are sufficient conditions that guarantee the optimality of a given feasible solution, besides allowing the solution to be obtained by classical optimization methods. The proposed model was written in the programming language OPL and solved by the commercial solver CPLEX. The model was validated through the comparison of the results obtained for five distribution systems with the results obtained through conventional load flow. The analyzed cases and the obtained results show the accuracy of the proposed model and its potential for application.
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Hajraoui, Abderrahmane. "Architecture multi-processeurs en automatisme non linéaire." Rouen, 1989. http://www.theses.fr/1989ROUES023.
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Tseng, Nan-Hsiung, and 曾南雄. "A Capacitor-Free CMOS Low Dropout Linear Voltage Regulator." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/50122503490455813142.
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碩士<br>國立交通大學<br>電機學院IC設計產業專班<br>95<br>In the recent years, developing of low power circuits to extend battery life has become a critical research topic due to explosion growing of portable electric devices. In order to make products smaller and thinner, this is a necessary trend to integrate the circuit and reduce the external component.
A power management system usually contains serval LDO regulators and switching regulators.The conventional LDO voltage regulator requires a very large output capacitor in the single microfarad range.Large microfarad capacitors can not easy integrated in IC, and take over a large area of PCB, consuming cost.
The target of this paper is to design a low dropout linear voltage regulator without external capcitor. This LDO is based on three stage amplifiers design, and also consider the stability, resolution, transient response and other performances. The design of specification is shown is the following: The maxmium load current is 100mA. The input voltage is ranged from1.5V to 4.5V. The output voltage is 1.3V. The dropout voltage is 200mV. The quiescent current is consuming only 46uA containing the bandgap reference. This LDO is fabricated by TSMC 0.35um 2P4M process.
Experimental results show that the proposed capacitor-free LDO voltage regulator is achieved the expected specification of stability and transient response.Thus, the proposed capacitor-free LDO voltage regulator is suitable for SoC solution.
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Mao, Chih-Lan, and 茅芝蘭. "Low Drop-out linear voltage regulator with digital control loop." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/01119785132076869048.
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碩士<br>龍華科技大學<br>電子工程系碩士班<br>100<br>The thesis consists of three topics: Low-Voltage bandgap reference circuit (LBGR), low Drop-out linear regulator (LDO) and Low Drop-out linear voltage regulator with Digital Control Loop. First, we discuss the micro-power low-voltage bandgap reference circuit. This circuit is used to realize a reference voltage circuit which is low sensitivity to temperature and provides a stable voltage source to extend the lifespan of the electronic products. The second discussion topic is low Drop-out linear regulator. The proposed low Drop-out linear regulator consists of an error amplifier, compensation circuit, PMOS power transistor and voltage divider resistors. This circuit has features of small size, simple design, low price, low output ripple and providing accurate output voltage. Finally, we discusses low drop-out linear voltage regulator with digital control loop circuit. This circuit consists of voltage controlled oscillator (VCO), duty-cycle corrector (DCC), charge pump (CP), phase frequency detector (PFD), loop filter and power transistors. This Low Drop-out linear voltage regulator using digital control loop is low sensitivity to variations of temperature and fabrication processes, and it possesses characteristic of low power consumption.
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Sheng-WenLai and 賴聖文. "A Low Dropout Linear Regulator with Programmable Output Voltage for SoC Application." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/61676226486716289455.
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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>98<br>A low-dropout (LDO) regulator with a tail current control (TCC) circuit and a supply ripple isolation mechanism is presented in this thesis. The TCC circuit consists of a dual differential pair, a 5-bit current DAC, and a current summation circuit, which can adjust the tail current ratio to achieve 5-bit programmable output using external control signals. The supply ripple isolation mechanism is added to improve the power supply rejection (PSR) over a wide frequency range.
The proposed design is fabricated in the TSMC 0.18μm 1-poly 6-metal CMOS process. Experimental results show that the supply is 1.6V and that the output is a 5-bit programmable output voltage ranging from 1V to 1.2V with a maximum load current of 5mA. The LDO regulator achieves a worst-case PSR performance of -20dB over 1MHz. The results show that the proposed design is suitable for system-on-chip (SoC) applications, where the output voltage can be changed using external control signals and achieve high PSR over a wide frequency range.
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Kuo, Yi-Ping, and 郭裔平. "Ultra-Low Voltage All Digitally Controlled Linear Voltage Regulator Design for Event-Driven Energy-Efficiency Sensing Platform." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/22310366975755448024.
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碩士<br>國立交通大學<br>電子工程學系 電子研究所<br>103<br>In this thesis, two digitally controlled linear voltage regulators are proposed for event-driven energy-efficiency sensing platform. Both digitally controlled linear voltage regulators are implemented on TSMC 65-nm low-power bulk CMOS technology and designed for near-/sub- threshold operations.
The first digitally controlled linear voltage regulator includes a digital error detector (DED), which is the replacement of the analog error amplifier. A novel Process-Voltage-Temperature (PVT) –aware design is implemented to mitigate environmental variations and to guarantee the resolution of linear voltage regulator.
In the second digitally controlled linear voltage regulator, a comparator-based error detector is proposed to replace analog error amplifier. Two methods are introduced to reduce self-generated output ripple by adjusting the PMOS strength for PVT and load variations.
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Wu, Shao-Ting, and 吳紹鼎. "A 0.5V Capacitor-less Low Dropout Linear Regulator with Subthreshold Reference Voltage Circuit." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/84076769701962493313.
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碩士<br>國立交通大學<br>電機工程學系<br>105<br>With the portable battery-operated device development. In order to effectively use limited battery, designing smaller and lower power chip become more important. Therefore, this thesis introduces low voltage capacitor-less low-dropout linear regulator (LDO). Meanwhile, with subthreshold CMOS voltage generator on chip, there is no need to import external reference voltage. As a result, the proposed LDO is suitable for systematic application.
Conventional LDO requires external capacitor for transient response and equivalent series resistor (ESR) for frequency compensation. But it is hard to maintain because the location of output pole varies with load conditions. In order to achieve low power target, using error amplifier which is operating in subthreshold region for LDO. Through digitally controlling five different size auxiliary power MOSFETs to regulate transient response. Auxiliary power MOSFETs solve not only transient problem but also narrow bandwidth of error amplifier. The proposed chip in this thesis were fabricated using a standard UMC 0.18μm 1P6M CMOS process. Total area is 0.457×0.457〖mm〗^2. Output voltage is 0.5V, and input voltage range is 0.6V to 1V.
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Su, Chia Hung. "A High -Temperature, High-Voltage, Fast Response Time Linear Regulator in 0.8um BCD-on-SOI." 2010. http://trace.tennessee.edu/utk_graddiss/851.
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The sale of hybrid electric vehicles (HEVs) has increased tenfold from the year 2001 to 2009 [1]. With this the demand for high temperature electronics has also increased dramatically making, high temperature electronics for HEV applications desirable in the engine compartment, power train, and brakes where the ambient temperature normally exceeds 150°C. Power converters (i.e. DC-DC converter, DC-AC inverter) inside the HEVs require gate drivers to control the power switches. An integrated gate driver circuit has been realized in 0.8-um BCD-on-SOI process. This gate driver IC needs a step-down voltage regulator to convert the unregulated high input DC voltage (VDDH) to a regulated nominal CMOS voltage (i.e. 5 V). This step-down voltage regulator will supply voltage to the low-side buffer (pre-driver) and other digital and analog circuits inside the gate driver ICs. A linear voltage regulator is employed to accomplish this task; however, very few publications on high temperature voltage regulators are available. This research presents a high temperature linear voltage regulator designed and fabricated in a commercially available 0.8-um BCD-on-SOI process. SOI processes typically offer reduced junction leakage current by three orders of magnitude compared to the bulk-CMOS processes at temperatures beyond 150°C. In addition, a pole swap compensation technique is utilized to achieve stability over a wide range (four decades) of load current. The error amplifier inside the regulator is designed using an inversion coefficient based design methodology, and a temperature stable current reference is used to bias the error amplifier. The linear regulator provides an output voltage of 5.3 V at room temperature and can supply a maximum load current of 200 mA.
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Wu, Chun-Shien, and 吳俊賢. "Low-Cost Dual Output Voltage Level Low-dropout Linear Regulator Using a Novel MUX-based Adjustable Reference Voltage Generator." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/68777859719416065521.
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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>96<br>In this thesis, we present a dual output voltage levels low drop-out (LDO) linear regulator. The regulator could produce two different output voltage levels for the same output by using an external selection signal. The proposed LDO structure is suitable for a power management system that required more than one supply voltage level with small area. The output voltage levels are 1V and 2.5V in this design. Our proposed dual output voltage level LDO linear regulator consists of a novel two-level reference voltage generator, a fast discharging path for the switching between voltage levels to reduce the settling time, and a current limiter to prevent sudden current overshoot. Simulation results indicate that the proposed design can maintain its performance within bound under five design corners.
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張洋睿. "The Design of The Capacitor-free Low-dropout Voltage Linear Regulator with Fast Transient Response." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/69135510413973781799.
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碩士<br>逢甲大學<br>電子工程學系<br>101<br>With the development of portable battery-operated electronic devices, developing small size and low power consumption to extend battery life products have become the subject of the study. Because of low dropout voltage and quiescent current, excellent line regulation and load regulation, good transient response and simple structure, the low dropout (LDO) linear regulator is widely used in portable systems. The traditional linear regulator has to consider the external output capacitance for good stability and transient response, so it occupies a large area of the LDO regulator. Therefore, the capacitor-free low dropout voltage linear regulator, with frequency compensation circuit and output voltage sensing circuit to improve the stability and transient response of this regulator is proposed in this study.
First, this study will introduce the traditional architecture of low-dropout linear regulator. Then, the definition of basic terms and the design considerations will be introduced. Because of removing external output capacitor, we will design other circuit to create new low-frequency dominant pole for the stability of the circuit. Then, we will improve transient response by modifying the high-swing amplifier of the error amplifier and adding output voltage sensing circuit.
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Li, Hsin-Tung, and 李新通. "Design and Implementation of Low Power-Bounce Current-to-Voltage-Conversion Dropout Linear Regulator Integrated Circuits." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/gyct5d.
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碩士<br>國立臺北科技大學<br>電子電腦與通訊產業研發碩士專班<br>95<br>With the development of electronic technology, the integrated circuits is more and more widely favored, especially in VLSI circuit, embedded system, and analog and digital IC deign. By the maturity of a technology that the integrated circuit at present time, we can integrate different circuits into a single chip, and make the function of our circuit to be more completed, but there are some stray inductances and resistances between circuits and power supply which could product glitches. We call the power bounces and ground bounces [1-2]. If this stray effect is too large, it is possible to make mistake and the result of output may be incorrect. It influence grandly in mixed-signal circuit, so the purpose of this circuit is to reduce power bounce which is produced by stray components. We compare other general LDO, and observe the result.
A novel Low Power-Bounce Current-to-Voltage-Conversion Dropout Linear Regulator Integrated Circuits with single Miller compensation capacitor is presented. By utilizing the current mode architecture to suppress power bounce. The proposed Current-to-Voltage-Conversion Dropout Linear Regulator Integrated Circuits have been fabricated in TSMC 0.35μm 2P4M CMOS technology. The measurement results show the settling time which can achieve 400ns with 0.5% error for full load-current. Furthermore, the line and load regulations are 14μV/mA and 4.44ppm/mA, respectively. The dropout current is 1.0741mA for 150mA output current. The measured current efficiency is 99.4168% in 152mA supply current. The active chip area is 226μm x310μm.
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Li, Kuen-Han, and 李昆翰. "A Low-Quiescent Current Output-Capacitorless Low-Dropout Voltage Linear Regulator with Self-Tuned Dual Pass-Transistors." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/b47z56.
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碩士<br>逢甲大學<br>電子工程學系<br>102<br>With the increasing demand of portable devices, how to use the battery energy efficiently is the most concerned problem. Small size and low power consumption requirements of the power system have become the notable points of this subject. For power management system, low-dropout (LDO) liner regulator is the most common block due to its simplicity, low noise and low power consumption characteristics. However, the conventional LDO often can not simultaneously achieve low power consumption and good transient response for the system. Therefore, a self-tuned dual pass-transistor technique and output voltage detector for capacitorless LDO to having low power consumption and good transient response is proposed in this study. The proposed LDO is designed and simulated by using tsmc 0.18μm 1P6M CMOS process. The measured results show that the proposed circuit consumes a quiescent current of 7μA at no load, and regulates the output at 1.8V from a voltage supply range of 2V to 5V. The settling time is about 7μs in transient response. Total power dissipation is 14.45μW, and the chip area is 1.1×1.1mm2.
Key words：low dropout voltage(LDO) linear regulator, capacitorless, seif-tuned dual pass-transistor, voltage detector
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Chang, Chia-Ning, and 張珈寧. "Exploration and Evaluation of Low-Dropout Linear Voltage Regulator with FinFET, TFET and Hybrid TFET-FinFET Implementations." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/88x5h8.
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碩士<br>國立交通大學<br>電子研究所<br>106<br>This thesis focuses on analog low-dropout linear voltage regulator and digitally controlled linear voltage regulator with FinFET, TFET and Hybrid TFET-FinFET implementations. We use Sentaurus atomistic 3D TCAD mixed-mode to analysis fundamental physical characteristics of transistors. Also, Verilog-A look-up table calibrated with simulation results from TCAD is applied in HSPICE circuit simulation tool for further analysis.
In exploration of analog low-dropout linear voltage regulator (LDO), because the transport mechanism of TFET is different from conventional MOSFET and FinFET, we do investigation of transconductance, output resistance and intrinsic gain of devices at first. It can be observed that, TFET demonstrates better performance at low operating voltage, while FinFET exhibits outperformance in current drive ability which is an advantage in high-performance applications. Furthermore, the performance of FinFET-LDO, TFET-LDO and Hybrid-LDO including frequency response, transient response and power supply rejection ration (PSRR) are evaluated. The results indicate that for ultra-low power application, TFET-LDO and Hybrid-LDO provide better loop-gain and PSRR than FinFET-LDO under comparable operating current design.
As operating voltage further reduced, the performance of analog LDO degrades severely; therefore, digitally controlled linear voltage regulator becomes the choice. Firstly, we analyze the digital error detector (DED) based on FinFET and TFET at 0.5V operating voltage. The sense period of TFET-DED is 7x times longer than FinFET-DED. Next step, we investigate the performance of pull/push devices under FinFET, Hybrid and Parallel structures based on FinFET-DED. The results demonstrate FinFET applied in digitally controlled voltage regulator stands out at 0.5V operating voltage due to the relatively strong current drive ability.
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Chen, Yi-Jing, and 陳以晉. "Fast-Response Digital Linear Voltage Regulator with Time-Sharing and Double-Edge-Triggered Techniques using Monolithic 3D IC." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/2f2d8g.
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碩士<br>國立交通大學<br>電子研究所<br>107<br>In this thesis, a digitally controlled linear voltage regulator is proposed using monolithic 3DIC multi-FET BEOL circuits. The PMOS switch array which originally occupied the majority of the area of the digitally controlled voltage regulator is implemented between top metal layers for power grids using monolithic 3DIC BEOL technique for reducing the cost of silicon area.
In thr proposed digital voltage regulator, a comparator-based error detector is used instead of an analog amplifier. Compared to the conventional digitally controlled linear voltage regulator, a comparator triggered at the positive and negative edges is utilized to achieve a fast response for the proposed digital voltage regulator. The time sharing method is also used in the shift register to reduce the power consumption due to the double edge triggered comparator. The proposed voltage regulator can adjust the PMOS strength by itself under different PVT and load variations, and achieves settling time by 200ns, quiescent current by 7.4μs and FOM 0.089ps. Furthermore, the total power efficiency is 99.94%.
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Lin, Tien-An, and 林天安. "A Fast Response of the Low-Dropout Linear Regulator with the Voltage Detection Mode of the Adaptive Reference Control Circuit." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/45588404728933214167.
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碩士<br>淡江大學<br>電機工程學系碩士在職專班<br>100<br>The fast growing demand of portable and battery-operated electronic systems has driven the efforts to reduce power consumption or to improve the efficiency of these electronic equipments. Regulator are essential for most electrically powered systems which include the prevalent portable equipments. Regulators are required to reduce the voltage variations of the battery. Besides, regulation are often utilized to provide a lower voltage from a higher input voltage for power reduction. Current trend in portable or battery-powered electronics demands ultra-low-power consumption or high operating efficiency to prolong the service time of these battery-operated equipments.
This thesis deals with the design and realization of a low-dropout linear regulator with a fast transient response. It applies voltage detection mode to realize an adaptive reference control circuit for improving the transient response of the linear regulator. The voltage detection circuit and the adaptive reference control circuit is implemented by using a CMOS 0.35 um 2P4M 3.3V5V mixed-mode chip of Taiwan Semiconductor (TSMC). Its layout area is about 1.2143mm x 0.93465mm. Its operating voltage ranges from 3.1V to 5V with fixed output of 3.0V and its maximum output current of the design is 100mA.
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Chou, Yen-Long, and 周延龍. "A Study of Temperature Sensor Circuit and Low Dropout Linear Voltage Regulator on Readout Circuit of Capacitive Pressure Sensor Device." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/r99h93.
Full textAbstract:
碩士<br>國立臺北科技大學<br>機電整合研究所<br>102<br>The evolution of the portable electronic systems has driven the effort to reduce the power consumption and to improve the efficiency. The traditional linear regulator has to consider this external load capacitance, it constitute for a large area and it is not suitable for system on chip. The capacitive pressure sensor is temperature sensitive. Therefore, this study proposes are a temperature sensor circuit and a capacitance-less low dropout linear voltage regulator on readout circuit of capacitive pressure sensor device. The system is designed and implemented in the standard TSMC 0.18μm CMOS 1P6M process. The low dropout voltage linear regulator show that the output voltage is 1.8 volts, the line regulator is 3.36mV/mA, the maximum load current is 5mA, the quiescent current is 49μA containing the bandgap reference, the input voltage is ranged from2.1V to 3.5V. The temperature sensor show that the accuracy is ±2°C
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Das, Dibakar. "Control Strategies for Seamless Transition between Grid Connected and Islanded Modes in Microgrids." Thesis, 2017. http://etd.iisc.ernet.in/2005/3710.
Full textAbstract:
The popularity of distributed generating (DG) sources have been increasing over the past few years. With the increasing penetration of these DGs, the concept of micro grid is becoming popular. A micro grid is a small power system network with distributed generating sources which can operate seamlessly irrespective of the presence of the utility grid. Operating the micro grid in this manner increases system reliability and reduces power interruptions. However, it introduces several control challenges.
This thesis aims at analysing the behaviour of a micro grid system during the transition between grid connected mode and islanded mode of operation and address the control challenges through novel schemes. With the presence of grid, the micro grid system variables, such as voltage and frequency, are strictly regulated by the grid. The local sources follow the voltage and frequency reference set by the grid and supply constant power. With the loss of grid, that is when the system is islanded, the network variables need to be regulated by the local sources. The control structures for the inverter-based sources during the two operating modes are detailed in the present work.
With the loss of grid, the system should be able to transfer seamlessly to islanded mode without any transients. Similarly, when the grid supply is restored, the micro grid should seamlessly resynchronize to the grid without any transients. This thesis proposes two novel controller schemes for achieving seamless transfer between grid-connected and islanded mode in micro grids. The rst scheme uses an output feedback topology to reduce the transitions during mode transfer. The second scheme uses a Linear Quadratic Regulator (LQR) theory based compensator to achieve seamless transfer. The performance of the proposed schemes have been validated through simulations on a benchmark micro grid network for various operating conditions.
An experimental micro grid set-up is developed with a single inverter based DG source. The droop control scheme for islanded mode of operation has been validated on hardware.
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JHAO, SYUAN-NENG, and 趙炫能. "Integrated Power Supply with Linear and Switching Voltage Regulators." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/tmtv5d.
Full textAbstract:
碩士<br>南臺科技大學<br>電機工程系<br>104<br>The thesis proposed a hybrid power system with combined advantageous features of switching power supply and linear power amplifier. The switching power supply would provide the primary output voltage and power to the load, while the linear power amplifier would act as a correcting amplifying device to compensate for power ripple as a way to stabilize voltage output. Combination of these two components not only reduced the output voltage ripple but improved the overall efficiency simultaneously, as the power output level could be higher, in comparison with the low efficiency of a system with only the linear power amplifier. The thesis would explore two practical approaches of using alternating and direct current power supply. For alternating power supply, it combined the linear power amplifier and the full-bridge inverter to produce alternating voltage which had adjustable output frequency and voltage. The direct current power supply would use a linear power amplifier and a phase shift full-bridge converter to produce wide-ranged and low-rippled direct current which had adjustable output voltage. And, two prototypes of electric circuit with the maximum output power of 500W to produce final output of hybrid alternating power at 70 to 110 with the maximum frequency of 1 and a hybrid direct power at 5 to 50 would be modeled to prove the control method as practicable.
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Tu, Chun-Hung, and 凃俊宏. "Performance Assessment and DC-Link Voltage Regulation System Design of Slotless Tubular Linear Generator." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/13695670925498740965.
Full textAbstract:
碩士<br>國立中山大學<br>電機工程學系研究所<br>99<br>The aim of this thesis is to design a controllable DC-link output voltage for isolated slotless tubular linear generators (STLG), which is capable of directly harnessing wave and solar thermal energies. For supplying stable DC-link voltage to load, a suitable voltage regulation circuit is designed based on the integrate system performance assessment. Electrical and mechanical parameters in this refined STLG design are involved to analyze the operational behaviors through magnetic equivalent circuit analysis at different operating modes. From the theoretical modeling and experimental results, both the AC-side and DC-side properties of generator outputs can then be thoroughly investigated. Finally, based on the performance of controllable rectifier model, a three-phase PWM rectifier has been established, and then the regulated DC-link voltage can be implemented using a DSP-based controller combined with required peripheral circuits.