Relevant bibliographies by topics / Logic Arrays

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Logic Arrays'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Logic Arrays"

1

XIAO, YONG-XIN. "Logic design of decoded-programmable logic arrays." International Journal of Electronics 69, no. 3 (September 1990): 317–25. http://dx.doi.org/10.1080/00207219008920316.

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Brandenburg, G., U. Gorschutz, and K. Muller. "Poor man's gate arrays-logic cell arrays." IEEE Transactions on Nuclear Science 35, no. 1 (February 1988): 213–16. http://dx.doi.org/10.1109/23.12710.

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Prasanna de Silva, A. "Molecular Logic Gate Arrays." Chemistry - An Asian Journal 6, no. 3 (February 3, 2011): 750–66. http://dx.doi.org/10.1002/asia.201000603.

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Glasgow, J. I., M. A. Jenkins, E. Blevis, and M. P. Feret. "Logic programming with arrays." IEEE Transactions on Knowledge and Data Engineering 3, no. 3 (1991): 307–19. http://dx.doi.org/10.1109/69.91061.

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Nicolaidis, M., and B. Courtois. "Self-checking logic arrays." Microprocessors and Microsystems 13, no. 4 (May 1989): 281–90. http://dx.doi.org/10.1016/0141-9331(89)90066-5.

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Landry, Steve. ""Designer" Logic And Symbols with Logic Cell Arrays." IEEE Micro 7, no. 1 (February 1987): 51–59. http://dx.doi.org/10.1109/mm.1987.304937.

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Chen-Wen Wu and P. R. Cappello. "Easily testable iterative logic arrays." IEEE Transactions on Computers 39, no. 5 (May 1990): 640–52. http://dx.doi.org/10.1109/12.53577.

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Maundy, Brent. "Designing with programmable logic arrays." Microprocessors and Microsystems 11, no. 9 (November 1987): 475–86. http://dx.doi.org/10.1016/0141-9331(87)90010-x.

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Sasao, T. "Multiple-valued logic and optimization of programmable logic arrays." Computer 21, no. 4 (April 1988): 71–80. http://dx.doi.org/10.1109/2.52.

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Barkalov, A. A., V. A. Salomatin, K. E. Starodubov, and D. K. Das. "Optimization of mealy automaton logic using programmable logic arrays." Cybernetics and Systems Analysis 27, no. 5 (1992): 789–93. http://dx.doi.org/10.1007/bf01130555.

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Dissertations / Theses on the topic "Logic Arrays"

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Hadjinicolaou, M. G. "Synthesis of programmable logic arrays." Thesis, Brunel University, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.371168.

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Lu, Aiguo. "Logic synthesis for field programmable gate arrays." Thesis, University of Bristol, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.295061.

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Lakkaraju, Harsha Vardhan. "DPA Resistant Logic Arrays for Security Applications." University of Cincinnati / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1448037460.

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Camus, Dominic Roger. "Improved logic optimisation for field programmable gate arrays." Thesis, University of Oxford, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.301840.

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Prakash, Manu. "Micro-mechanical logic for field produceable gate arrays." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/34486.

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Thesis (S.M.)--Massachusetts Institute of Technology, School of Architecture and Planning, Program in Media Arts and Sciences, 2005.
Includes bibliographical references (leaves 106-110).
A paradigm of micro-mechanical gates for field produceable logic is explored. A desktop manufacturing system is sought after which is capable of printing functional logic devices in the field. A logic scheme which induces non-linearities via geometrical properties is considered. Logic devices in two-phase air-water fluid-dynamic system at micron scales are constructed. A systematic study of non-linearities and relevant force fields in fluid dynamics at low Reynolds Number is undertaken. Viscous forces dominate inertial forces at low Reynolds Number flows at low pressure. Thus devices based on non-linear inertial effects at high Reynolds numbers can not be scaled down to micron-sizes. Bubble microfluidic logic gates are invented to tackle the above problem, thus producing low Reynolds Number logic in Newtonian fluids. Various devices including AND/OR gates, NOT gate, nonvolatile bistable memory, shift registers and ON/OFF flow valves, based on this new scheme of bubble bubble interaction in microfluidic devices to induce non-linearity, are designed and characterized. On-chip bubble generators and annihilators are used for encoding and destroying information in bubble logic devices.
(cont.) Applications of the above described logic devices as a flow control strategy for droplet based Lab-on-chip devices is explored. A simple to construct in-situ pressure sensor based on the principle of compressibility of an air bubble in microfluidic devices is invented. A scheme of controlled bubble/droplet movement in shift registers via pulsating pressure fields for precise temporal control of start of microfluidic reactions is proposed. Excimer laser micro-machining of boro-silicate glass is developed to direct write 3D microfluidic structures. Laser ablation process using a ArF based 193nm laser for machining is characterized using laser confocal microscopy techniques. Single bubble cavitation induced by laser pulses is developed as a process for writing micro-bubbles at precise locations in microfluidic channels.
by Manu Prakash.
S.M.
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Sarabi, Andisheh. "Logic Synthesis with High Testability for Cellular Arrays." PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4752.

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The new Field Programmable Gate Array (FPGA) technologies and their structures have opened up new approaches to logic design and synthesis. The main feature of an FPGA is an array of logic blocks surrounded by a programmable interconnection structure. Cellular FPGAs are a special class of FPGAs which are distinguished by their fine granularity and their emphasis on local cell interconnects. While these characteristics call for specialized synthesis tools, the availability of logic gates other than Boolean AND, OR and NOT in these architectures opens up new possibilities for synthesis. Among the possible realizations of Boolean functions, XOR logic is shown to be more compact than AND/OR and also highly testable. In this dissertation, the concept of structural regularity and the advantages of XOR logic are used to investigate various synthesis approaches to cellular FPGAs, which up to now have been mostly nonexistent. Universal XOR Canonical Forms, Two-level AND/XOR, restricted factorization, as well as various Directed Acyclic Graph structures are among the proposed approaches. In addition, a new comprehensive methodology for the investigation of all possible XOR canonical forms is introduced. Additionally, a new compact class of XOR-based Decision Diagrams for the representation of Boolean functions, called Kronecker Functional Decision Diagrams (KFDD), is presented. It is shown that for the standard, hard, benchmark examples, KFDDs are on average 35% more compact than Binary Decision Diagrams, with some reductions of up to 75% being observed.
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Howard, Neil John. "Defect-tolerant Field-Programmable Gate Arrays." Thesis, University of York, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.359290.

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Wood, Christopher Landon. "Runtime partial FPGA reconfiguration." Thesis, Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15051.

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Malik, Usama Computer Science &amp Engineering Faculty of Engineering UNSW. "Configuration encoding techniques for fast FPGA reconfiguration." Awarded by:University of New South Wales. School of Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/26212.

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This thesis examines the problem of reducing reconfiguration time of an island-style FPGA at its configuration memory level. The approach followed is to examine configuration encoding techniques in order to reduce the size of the bitstream that must be loaded onto the device to perform a reconfiguration. A detailed analysis of a set of benchmark circuits on various island-style FPGAs shows that a typical circuit randomly changes a small number of bits in the {\it null} or default configuration state of the device. This feature is exploited by developing efficient encoding schemes for configuration data. For a wide set of benchmark circuits on various FPGAs, it is shown that the proposed methods outperform all previous configuration compression methods and, depending upon the relative size of the circuit to the device, compress within 5\% of the fundamental information theoretic limit. Moreover, it is shown that the corresponding decoders are simple to implement in hardware and scale well with device size and available configuration bandwidth. It is not unreasonable to expect that with little modification to existing FPGA configuration memory systems and acceptable increase in configuration power a 10-fold improvement in configuration delay could be achieved. The main contribution of this thesis is that it defines the limit of configuration compression for the FPGAs under consideration and develops practical methods of overcoming this reconfiguration bottleneck. The functional density of reconfigurable devices could thereby be enhanced and the range of potential applications reasonably expanded.
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Koh, Shannon Computer Science &amp Engineering Faculty of Engineering UNSW. "Generating the communication infrastracture for module-based dynamic reconfiguration of FPGas." Publisher:University of New South Wales. Computer Science & Engineering, 2008. http://handle.unsw.edu.au/1959.4/41418.

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Current approaches to supporting module-based FPGA reconfiguration focus on various aspects and sub-problems in the area but do not combine to form a coherent, top-down methodology that factors low-level device parameters into every step of the design flow. This thesis proposes such a top-down methodology from application specification to low-level implementation, centered around examining the problem of generating a point-to-point communications infrastructure to support the changing interfaces of dynamically placed modules. Low-level implementation parameters are considered at every stage to ensure that area, timing and budget constraints of the application are met. The approach advocates the regular layout of modules surrounded by a wiring harness supporting the communications for those modules, and thus provides an advanced understanding of how to implement the "fixed wiring harness" model of reconfigurable computing proposed by Brebner. Results have shown that compared to flattened net lists the regularity of the layout does not impose significant overheads on critical path delays. At high communication densities it can even result in lower delays. The core of the methodology is an infrastructure generation process that allocates modules to slots and merges configuration graphs to form wiring harnesses that support the communications for these merged configurations. This thesis suggests methods and evaluates algorithms for configuration graph merging so as to reduce run-time reconfiguration overheads. Initial experiments with a greedy merging algorithm performed on an optical flow application resulted in a substantial reduction of 64% in reconfiguration time. The effects of graph merging with the initial greedy algorithm and an improved dynamic programming algorithm were explored for a range of device sizes and architectural parameters. Results show that configuration merging using the greedy method results in significant reductions to the reconfiguration delay. The dynamic programming algorithm provides consistent improvements above and beyond the savings provided by the greedy method. In addition, a strong correlation was identified between the quality of front-end design activities such as partitioning and the effectiveness of back-end implementations. The methodology is integrated into the Xilinx commercial tool flow for partial reconfiguration, and is effective for implementing applications for module-based FPGA reconfiguration where the modules and their communications requirements are known at design time. It also allows a system designer to consider alternate device sizes and parameters until a set is found that satisfies the application constraints.
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Books on the topic "Logic Arrays"

1

Murgai, Rajeev. Logic synthesis for field-programmable gate arrays. Boston: Kluwer Academic Publishers, 1995.

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Hadjinicolaou, M. G. Synthesis of programmable logic arrays. Uxbridge: Brunel University, 1986.

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Murgai, Rajeev. Logic Synthesis for Field-Programmable Gate Arrays. Boston, MA: Springer US, 1995.

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Murgai, Rajeev, Robert K. Brayton, and Alberto Sangiovanni-Vincentelli. Logic Synthesis for Field-Programmable Gate Arrays. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2345-1.

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Ukeiley, Richard Larry. Field programmable gate arrays (FPGAs): The 3000 series. Englewood Cliffs, N.J: PTR Prentice Hall, 1993.

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C, Dorf Richard, ed. Field-programmable gate arrays: Reconfigurable logic for rapid prototyping and implementation of digital systems. New York: Wiley, 1995.

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Designing with FPGAs and CPLDs. Englewood Cliffs, N.J: Prentice Hall, 1994.

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Hennie, Frederick. Iterative arrays of logical circuits. Cambridge, Mass: MIT-Press, 2003.

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ACM International Symposium on Field-Programmable Gate Arrays (6th 1998 Monterey, Calif.). FPGA '98: ACM/SIGDA International Symposium on Field Programmable Gate Arrays. New York, NY: Association for Computing Machinery, 1998.

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International, Conference on Field Programmable Logic and Applications (18th 2008 Heidelberg Germany). 2008 International Conference on Field Programmable and Logic Applications : Heidelberg, Germany, 8-10 September 2008. Piscataway, N.J: IEEE, 2008.

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Book chapters on the topic "Logic Arrays"

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Brown, Stephen D., Robert J. Francis, Jonathan Rose, and Zvonko G. Vranesic. "Logic Block Architecture." In Field-Programmable Gate Arrays, 87–115. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_4.

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Murgai, Rajeev, Robert K. Brayton, and Alberto Sangiovanni-Vincentelli. "Logic Optimization." In Logic Synthesis for Field-Programmable Gate Arrays, 177–93. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2345-1_4.

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Lewin, D., and D. Protheroe. "Design of regular arrays." In Design of Logic Systems, 368–402. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4899-6856-2_9.

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Murgai, Rajeev, Robert K. Brayton, and Alberto Sangiovanni-Vincentelli. "Mapping Combinational Logic." In Logic Synthesis for Field-Programmable Gate Arrays, 51–176. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2345-1_3.

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Murgai, Rajeev, Robert K. Brayton, and Alberto Sangiovanni-Vincentelli. "Mapping Sequential Logic." In Logic Synthesis for Field-Programmable Gate Arrays, 255–97. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2345-1_6.

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Murgai, Rajeev, Robert K. Brayton, and Alberto Sangiovanni-Vincentelli. "Mapping Combinational Logic." In Logic Synthesis for Field-Programmable Gate Arrays, 325–95. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2345-1_8.

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Teife, John, and Rajit Manohar. "Programmable Asynchronous Pipeline Arrays." In Field Programmable Logic and Application, 345–54. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-45234-8_34.

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Sakaguchi, Kazuhiko. "Program Extraction for Mutable Arrays." In Functional and Logic Programming, 51–67. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-90686-7_4.

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Marnane, W. P., C. N. Jordan, and F. J. O'Reilly. "Compiling regular arrays onto FPGAs." In Field-Programmable Logic and Applications, 178–87. Berlin, Heidelberg: Springer Berlin Heidelberg, 1995. http://dx.doi.org/10.1007/3-540-60294-1_111.

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Seals, R. C., and G. F. Whapshott. "Field programmable gate arrays (FPGAs)." In Programmable Logic: PLDs and FPGAs, 102–39. London: Macmillan Education UK, 1997. http://dx.doi.org/10.1007/978-1-349-14003-9_4.

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Conference papers on the topic "Logic Arrays"

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Murgai, Rajeev, Yoshihito Nishizaki, Narendra Shenoy, Robert K. Brayton, and Alberto Sangiovanni-Vincentelli. "Logic synthesis for programmable gate arrays." In Conference proceedings. New York, New York, USA: ACM Press, 1990. http://dx.doi.org/10.1145/123186.123421.

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DeHon, Andre, and Michael J. Wilson. "Nanowire-based sublithographic programmable logic arrays." In Proceeding of the 2004 ACM/SIGDA 12th international symposium. New York, New York, USA: ACM Press, 2004. http://dx.doi.org/10.1145/968280.968299.

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Wang, T., M. Arshad, and R. Arrathoon. "Optically Controlled Fiber Optic Logic Arrays." In 32nd Annual Technical Symposium, edited by J. P. Letellier. SPIE, 1989. http://dx.doi.org/10.1117/12.948552.

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Thakur, S., and D. F. Wong. "On Designing ULM-Based FPGA Logic Modules." In Third International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1995. http://dx.doi.org/10.1109/fpga.1995.241856.

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Hauck, S., and G. Borriello. "Logic Partition Orderings for Multi-FPGA Systems." In Third International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1995. http://dx.doi.org/10.1109/fpga.1995.241942.

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Thakur, S., and D. F. Wong. "Universal Logic Modules for Series-Parallel Functions." In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242340.

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Lei, Lei, Jianji Dong, Yu Yu, and Xinliang Zhang. "All-optical programmable logic arrays using SOA-based canonical logic units." In Photonics Asia, edited by Feijun Song, Hui Li, Xiudong Sun, Francis T. S. Yu, Suganda Jutamulia, Kees A. Schouhamer Immink, and Keiji Shono. SPIE, 2012. http://dx.doi.org/10.1117/12.1000173.

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Kannan, L. N., and D. Sarma. "A novel technique for folding logic arrays." In [1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design. IEEE, 1991. http://dx.doi.org/10.1109/isvd.1991.185100.

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Mehrabadi, Roozbeh, Shaohua Yuan, and Resve Saleh. "Structured Logic Arrays for Future CMOS Technologies." In 2007 Canadian Conference on Electrical and Computer Engineering. IEEE, 2007. http://dx.doi.org/10.1109/ccece.2007.64.

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Meinhardt, Cristina, Ricardo Reis, and Reginaldo Tavares. "Logic and Physical Synthesis of Cell Arrays." In 2007 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS '07). IEEE, 2007. http://dx.doi.org/10.1109/icecs.2007.4511234.

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Reports on the topic "Logic Arrays"

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Alford, Cecil O. Macrostructure Logic Arrays. Volume 5. Summary. Fort Belvoir, VA: Defense Technical Information Center, November 1990. http://dx.doi.org/10.21236/ada228566.

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Tour, James M. Logic Nanocells Within 3-Terminal Ordered Arrays. Fort Belvoir, VA: Defense Technical Information Center, February 2007. http://dx.doi.org/10.21236/ada473904.

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Sarabi, Andisheh. Logic Synthesis with High Testability for Cellular Arrays. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.6638.

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Tirumalai, Parthasarathy, and Jon T. Butler. Analysis of Minimization Algorithms for Multiple-Valued Programmable Logic Arrays. Fort Belvoir, VA: Defense Technical Information Center, May 1988. http://dx.doi.org/10.21236/ada605376.

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Rose, Jonathan, Robert J. Francis, Paul Chow, and David Lewis. The Effect of Logic Block Complexity on Area of Programmable Gate Arrays. Fort Belvoir, VA: Defense Technical Information Center, January 1987. http://dx.doi.org/10.21236/ada207172.

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Grondin, Robert O. Basic Properties and Limits of Integrated Arrays of Dissipative Circuit and Logic Elements. Fort Belvoir, VA: Defense Technical Information Center, January 1989. http://dx.doi.org/10.21236/ada224533.

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Cheng, Julian. Integrated Photonic Switches and Logic Gate Arrays for Parallel Optical Switching and Computer Architectures. Fort Belvoir, VA: Defense Technical Information Center, June 1995. http://dx.doi.org/10.21236/ada297732.

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Wu, Lifei. Minimization of Permuted Reed-Muller Trees and Reed-Muller Trees for Cellular Logic Programmable Gate Arrays. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.6629.

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Hansen, N. H. The hardware accelerator array for logic simulation. Office of Scientific and Technical Information (OSTI), May 1991. http://dx.doi.org/10.2172/5569259.

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Trotter, J. D., and A. K. R. Naini. Bulk CMOS VLSI Technology Studies. Part 1. Scalable CMOS Design Rules. Part 2. CMOS Approaches to PLA (Programmable Logic Array) Design. Fort Belvoir, VA: Defense Technical Information Center, June 1985. http://dx.doi.org/10.21236/ada158367.

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