Dissertations / Theses: 'Logic Arrays'

1

Hadjinicolaou, M. G. "Synthesis of programmable logic arrays." Thesis, Brunel University, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.371168.

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Lu, Aiguo. "Logic synthesis for field programmable gate arrays." Thesis, University of Bristol, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.295061.

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Lakkaraju, Harsha Vardhan. "DPA Resistant Logic Arrays for Security Applications." University of Cincinnati / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1448037460.

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4

Camus, Dominic Roger. "Improved logic optimisation for field programmable gate arrays." Thesis, University of Oxford, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.301840.

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5

Prakash, Manu. "Micro-mechanical logic for field produceable gate arrays." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/34486.

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Thesis (S.M.)--Massachusetts Institute of Technology, School of Architecture and Planning, Program in Media Arts and Sciences, 2005.
Includes bibliographical references (leaves 106-110).
A paradigm of micro-mechanical gates for field produceable logic is explored. A desktop manufacturing system is sought after which is capable of printing functional logic devices in the field. A logic scheme which induces non-linearities via geometrical properties is considered. Logic devices in two-phase air-water fluid-dynamic system at micron scales are constructed. A systematic study of non-linearities and relevant force fields in fluid dynamics at low Reynolds Number is undertaken. Viscous forces dominate inertial forces at low Reynolds Number flows at low pressure. Thus devices based on non-linear inertial effects at high Reynolds numbers can not be scaled down to micron-sizes. Bubble microfluidic logic gates are invented to tackle the above problem, thus producing low Reynolds Number logic in Newtonian fluids. Various devices including AND/OR gates, NOT gate, nonvolatile bistable memory, shift registers and ON/OFF flow valves, based on this new scheme of bubble bubble interaction in microfluidic devices to induce non-linearity, are designed and characterized. On-chip bubble generators and annihilators are used for encoding and destroying information in bubble logic devices.
(cont.) Applications of the above described logic devices as a flow control strategy for droplet based Lab-on-chip devices is explored. A simple to construct in-situ pressure sensor based on the principle of compressibility of an air bubble in microfluidic devices is invented. A scheme of controlled bubble/droplet movement in shift registers via pulsating pressure fields for precise temporal control of start of microfluidic reactions is proposed. Excimer laser micro-machining of boro-silicate glass is developed to direct write 3D microfluidic structures. Laser ablation process using a ArF based 193nm laser for machining is characterized using laser confocal microscopy techniques. Single bubble cavitation induced by laser pulses is developed as a process for writing micro-bubbles at precise locations in microfluidic channels.
by Manu Prakash.
S.M.

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6

Sarabi, Andisheh. "Logic Synthesis with High Testability for Cellular Arrays." PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4752.

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The new Field Programmable Gate Array (FPGA) technologies and their structures have opened up new approaches to logic design and synthesis. The main feature of an FPGA is an array of logic blocks surrounded by a programmable interconnection structure. Cellular FPGAs are a special class of FPGAs which are distinguished by their fine granularity and their emphasis on local cell interconnects. While these characteristics call for specialized synthesis tools, the availability of logic gates other than Boolean AND, OR and NOT in these architectures opens up new possibilities for synthesis. Among the possible realizations of Boolean functions, XOR logic is shown to be more compact than AND/OR and also highly testable. In this dissertation, the concept of structural regularity and the advantages of XOR logic are used to investigate various synthesis approaches to cellular FPGAs, which up to now have been mostly nonexistent. Universal XOR Canonical Forms, Two-level AND/XOR, restricted factorization, as well as various Directed Acyclic Graph structures are among the proposed approaches. In addition, a new comprehensive methodology for the investigation of all possible XOR canonical forms is introduced. Additionally, a new compact class of XOR-based Decision Diagrams for the representation of Boolean functions, called Kronecker Functional Decision Diagrams (KFDD), is presented. It is shown that for the standard, hard, benchmark examples, KFDDs are on average 35% more compact than Binary Decision Diagrams, with some reductions of up to 75% being observed.

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7

Howard, Neil John. "Defect-tolerant Field-Programmable Gate Arrays." Thesis, University of York, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.359290.

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8

Wood, Christopher Landon. "Runtime partial FPGA reconfiguration." Thesis, Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15051.

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9

Malik, Usama Computer Science &amp Engineering Faculty of Engineering UNSW. "Configuration encoding techniques for fast FPGA reconfiguration." Awarded by:University of New South Wales. School of Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/26212.

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This thesis examines the problem of reducing reconfiguration time of an island-style FPGA at its configuration memory level. The approach followed is to examine configuration encoding techniques in order to reduce the size of the bitstream that must be loaded onto the device to perform a reconfiguration. A detailed analysis of a set of benchmark circuits on various island-style FPGAs shows that a typical circuit randomly changes a small number of bits in the {\it null} or default configuration state of the device. This feature is exploited by developing efficient encoding schemes for configuration data. For a wide set of benchmark circuits on various FPGAs, it is shown that the proposed methods outperform all previous configuration compression methods and, depending upon the relative size of the circuit to the device, compress within 5\% of the fundamental information theoretic limit. Moreover, it is shown that the corresponding decoders are simple to implement in hardware and scale well with device size and available configuration bandwidth. It is not unreasonable to expect that with little modification to existing FPGA configuration memory systems and acceptable increase in configuration power a 10-fold improvement in configuration delay could be achieved. The main contribution of this thesis is that it defines the limit of configuration compression for the FPGAs under consideration and develops practical methods of overcoming this reconfiguration bottleneck. The functional density of reconfigurable devices could thereby be enhanced and the range of potential applications reasonably expanded.

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Koh, Shannon Computer Science &amp Engineering Faculty of Engineering UNSW. "Generating the communication infrastracture for module-based dynamic reconfiguration of FPGas." Publisher:University of New South Wales. Computer Science & Engineering, 2008. http://handle.unsw.edu.au/1959.4/41418.

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Current approaches to supporting module-based FPGA reconfiguration focus on various aspects and sub-problems in the area but do not combine to form a coherent, top-down methodology that factors low-level device parameters into every step of the design flow. This thesis proposes such a top-down methodology from application specification to low-level implementation, centered around examining the problem of generating a point-to-point communications infrastructure to support the changing interfaces of dynamically placed modules. Low-level implementation parameters are considered at every stage to ensure that area, timing and budget constraints of the application are met. The approach advocates the regular layout of modules surrounded by a wiring harness supporting the communications for those modules, and thus provides an advanced understanding of how to implement the "fixed wiring harness" model of reconfigurable computing proposed by Brebner. Results have shown that compared to flattened net lists the regularity of the layout does not impose significant overheads on critical path delays. At high communication densities it can even result in lower delays. The core of the methodology is an infrastructure generation process that allocates modules to slots and merges configuration graphs to form wiring harnesses that support the communications for these merged configurations. This thesis suggests methods and evaluates algorithms for configuration graph merging so as to reduce run-time reconfiguration overheads. Initial experiments with a greedy merging algorithm performed on an optical flow application resulted in a substantial reduction of 64% in reconfiguration time. The effects of graph merging with the initial greedy algorithm and an improved dynamic programming algorithm were explored for a range of device sizes and architectural parameters. Results show that configuration merging using the greedy method results in significant reductions to the reconfiguration delay. The dynamic programming algorithm provides consistent improvements above and beyond the savings provided by the greedy method. In addition, a strong correlation was identified between the quality of front-end design activities such as partitioning and the effectiveness of back-end implementations. The methodology is integrated into the Xilinx commercial tool flow for partial reconfiguration, and is effective for implementing applications for module-based FPGA reconfiguration where the modules and their communications requirements are known at design time. It also allows a system designer to consider alternate device sizes and parameters until a set is found that satisfies the application constraints.

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11

Rajagopalan, Kamal. "An FPGA architecture for improved arithmetic performance /." St. Lucia, Qld, 2001. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe16460.pdf.

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12

Galindo, Juan Manuel. "A novel partial reconfiguration methodology for FPGAs of multichip systems /." Online version of thesis, 2008. http://hdl.handle.net/1850/7784.

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13

Sunki, Supriya. "Performance optimization in three-dimensional programmable logic arrays (PLAs)." [Tampa, Fla.] : University of South Florida, 2005. http://purl.fcla.edu/fcla/etd/SFE0001255.

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14

Han, Yi. "Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology." Thesis, [S.l. : s.n.], 2008. http://dk.cput.ac.za/cgi/viewcontent.cgi?article=1011&context=td_cput.

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15

Robinson, Markus F. "A method of test pattern generation for programmable logic arrays /." Thesis, McGill University, 1989. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=59285.

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A method for PLA test pattern generation based on a branch and bound algorithm that exploits function monotonicity is presented. The algorithm makes irrevocable input assignments first, resulting in the efficient generation of compact test sets. In most cases there is no backtracking. An intelligent branching heuristic is presented. The algorithm handles extended fault models including crosspoint and delay faults. Heuristics which speed up test set generation and improve test set compaction are discussed.
Results of tests on a wide range of benchmark PLAs are included.

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16

Davis, James. "Low-overhead fault-tolerant logic for field-programmable gate arrays." Thesis, Imperial College London, 2015. http://hdl.handle.net/10044/1/44382.

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While allowing for the fabrication of increasingly complex and efficient circuitry, transistor shrinkage and count-per-device expansion have major downsides: chiefly increased variation, degradation and fault susceptibility. For this reason, design-time consideration of faults will have to be given to increasing numbers of electronic systems in the future to ensure yields, reliabilities and lifetimes remain acceptably high. Many mathematical operators commonly accelerated in hardware are suited to modification resulting in datapath error detection and correction capabilities with far lower area, performance and/or power consumption overheads than those incurred through the utilisation of more established, general-purpose fault tolerance methods such as modular redundancy. Field-programmable gate arrays are uniquely placed to allow further area savings to be made thanks to their dynamic reconfigurability. The majority of the technical work presented within this thesis is based upon a benchmark hardware accelerator - a matrix multiplier - that underwent several evolutions in order to detect and correct faults manifesting along its datapath at runtime. In the first instance, fault detectability in excess of 99% was achieved in return for 7.87% additional area and 45.5% extra latency. In the second, the ability to correct errors caused by those faults was added at the cost of 4.20% more area, while 50.7% of this - and 46.2% of the previously incurred latency overhead - was removed through the introduction of partial reconfiguration in the third. The fourth demonstrates further reductions in both area and performance overheads - of 16.7% and 8.27%, respectively - through systematic data width reduction by allowing errors of less than ±0.5% of the maximum output value to propagate.

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17

Stamoulis, Iakovos. "Computer graphics hardware using ASICs, FPGAs and embedded logic." Thesis, University of Sussex, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.313943.

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The introduction of new technologies such as Field Programmable Gate Arrays (FPGAs) with high gate counts and embedded memory Applications Specific Integrated Circuits (ASICs) gives greater scope to the design of computer graphics hardware. This thesis investigates the features of the current generation of FPGAs and complex programmable logic devices (CPLD) and assesses their suitability as replacements for ASIC technologies, and as prototyping tools for their verification prior to fabrication. The traditional methodologies and techniques used for digital systems are examined for application to FPGA devices and novel design flow and implementation techniques are proposed. The new methodology and design flow uses a contemporary top down approach using hardware description languages and combines the flexibility of those methods with the efficiency of detailed low level design techniques. As an example of this methodology, a set of floating point arithmetic units consisting of a adder/subtraction, multiplication and division were designed using novel alternative algorithms that significantly outperformed algorithms designed with traditional methods in terms of both size and performance.T hese techniquesu sed were used to form a ToolKit that can accelerateth e design of systems that use floating point units for computer graphics systems. This ToolKit, in combination with a precision investigation methods can be used to generate floating point arithmetic units that have the required precision with minimum required hardware resources. Another emerging technology is that of embedded memory. Recent advancements in semiconductor fabrication processes make it feasible to integrate large amounts of DRAM, SRAM and logic on a single silicon die. This thesis will show the changes in the design flow that are require to take advantage of this new technology. A new embedded logic ToolKit was created that facilitates the exploitation of this technology. Finally, as an example to this methodology, a novel processor oriented towards 3D graphics was designedA. n architecturale xploration driven by novel trace-drivenp erformancea nalysism ethods is detailed that was used to model and tune the processor for the execution of global illumination computer graphics algorithms. The adaptation of these algorithms for execution in our processor is demonstrateda nd the performancea dvantagesth at can be extracteda re shown

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18

Seater, Robert. "Efficient handling of dependence analysis for arrays." Diss., Connect to the thesis, 2002. http://hdl.handle.net/10066/1541.

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19

Sharma, Akshay. "Place and route techniques for FPGA architecture advancement /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6108.

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20

Miles, J. R. "Cost modelling for VLSI circuit conversion to aid testability." Thesis, Brunel University, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.383718.

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21

Chang, Mark L. "Variable precision analysis for FPGA synthesis /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/5901.

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22

Mak, Wai-kei. "Partitioning and routing for multi-FPGA systems /." Digital version accessible at:, 1998. http://wwwlib.umi.com/cr/utexas/main.

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23

Lee, Kok Kiong. "CAD algorithms for field programmable logic devices /." Digital version:, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p9992847.

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24

Anderson, Jason Helge. "Architectures and algorithms for laser-programmed gate arrays with foldable logic blocks." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp04/mq29401.pdf.

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25

Parris, Matthew. "OPTIMIZING DYNAMIC LOGIC REALIZATIONS FOR PARTIAL RECONFIGURATION OF FIELD PROGRAMMABLE GATE ARRAYS." Master's thesis, University of Central Florida, 2008. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4128.

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Many digital logic applications can take advantage of the reconfiguration capability of Field Programmable Gate Arrays (FPGAs) to dynamically patch design flaws, recover from faults, or time-multiplex between functions. Partial reconfiguration is the process by which a user modifies one or more modules residing on the FPGA device independently of the others. Partial Reconfiguration reduces the granularity of reconfiguration to be a set of columns or rectangular region of the device. Decreasing the granularity of reconfiguration results in reduced configuration filesizes and, thus, reduced configuration times. When compared to one bitstream of a non-partial reconfiguration implementation, smaller modules resulting in smaller bitstream filesizes allow an FPGA to implement many more hardware configurations with greater speed under similar storage requirements. To realize the benefits of partial reconfiguration in a wider range of applications, this thesis begins with a survey of FPGA fault-handling methods, which are compared using performance-based metrics. Performance analysis of the Genetic Algorithm (GA) Offline Recovery method is investigated and candidate solutions provided by the GA are partitioned by age to improve its efficiency. Parameters of this aging technique are optimized to increase the occurrence rate of complete repairs. Continuing the discussion of partial reconfiguration, the thesis develops a case-study application that implements one partial reconfiguration module to demonstrate the functionality and benefits of time multiplexing and reveal the improved efficiencies of the latest large-capacity FPGA architectures. The number of active partial reconfiguration modules implemented on a single FPGA device is increased from one to eight to implement a dynamic video-processing architecture for Discrete Cosine Transform and Motion Estimation functions to demonstrate a 55-fold reduction in bitstream storage requirements thus improving partial reconfiguration capability.
M.S.Cp.E.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Computer Engineering MSCpE

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26

Zhang, Chengjin. "An investigation into the realisation and testing of a universal logic primitive gate array." Thesis, University of Bath, 1988. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.384137.

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27

Raghavan, Anup Kumar. "JPG : a partial bitstream generation tool to support partial reconfiguration in Virtex FPGAs /." [St. Lucia, Qld.], 2004. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe17691.pdf.

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28

Treuer, Robert. "A new design of built-in self-testing programmable logic arrays with high fault coverage and low overhead /." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63215.

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29

Orlando, Gerardo. "Efficient elliptic curve processor architectures for field programmable logic." Link to electronic thesis, 2002. http://www.wpi.edu/Pubs/ETD/Available/etd-0327102-103635.

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30

Milliord, Corey. "Dynamic Voting Schemes to Enhance Evolutionary Repair in Reconfigurable Logic Devices." Honors in the Major Thesis, University of Central Florida, 2005. http://digital.library.ucf.edu/cdm/ref/collection/ETH/id/780.

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This item is only available in print in the UCF Libraries. If this is your Honors Thesis, you can help us make it available online for use by researchers around the world by following the instructions on the distribution consent form at http://library.ucf
Bachelors
Engineering and Computer Science
Computer Engineering

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31

Biju, S., T. V. Narayana, P. Anguswamy, and U. S. Singh. "A Systolic Array Based Reed-Solomon Decoder Realised Using Programmable Logic Devices." International Foundation for Telemetering, 1995. http://hdl.handle.net/10150/611584.

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International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada
This paper describes the development of a Reed-Solomon (RS) Encoder-Decoder which implements the RS segment of the telemetry channel coding scheme recommended by the Consultative Committee on Space Data Systems (CCSDS)[1]. The Euclidean algorithm has been chosen for the decoder implementation, the hardware realization taking a systolic array approach. The fully pipelined decoder runs on a single clock and the operating speed is limited only by the Galois Field (GF) multiplier's delay. The circuit has been synthesised from VHDL descriptions and the hardware is being realised using programmable logic chips. This circuit was simulated for functional operation and found to perform correction of error patterns exactly as predicted by theory.

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32

Dhingra, Sachin Stroud Charles E. "Built-in self-test of logic resources in field programmable data arrays using partial reconfiguration." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Summer/Theses/DHINGRA_SACHIN_27.pdf.

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33

Davis, Justin S. "An FPGA-based digital logic core for ATE support and embedded test applications." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/15639.

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34

Shen, Ying. "Compiling a synchronous programming language into field programmable gate arrays." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0029/MQ47476.pdf.

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35

Wu, Lifei. "Minimization of Permuted Reed-Muller Trees and Reed-Muller Trees for Cellular Logic Programmable Gate Arrays." PDXScholar, 1993. https://pdxscholar.library.pdx.edu/open_access_etds/4745.

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The new family of Field Programmable Gate Arrays, CLI 6000 from Concurrent Logic Inc realizes truly Cellular Logic. It has been mainly designed for the realization of data path architectures. However, the realizable logic functions provided by its macrocells and their limited connectivity call also for new general-purpose logic synthesis methods. The basic cell of CLi 6000 can be programmed to realize a two-input multiplexer ( A*B + C*B ), an AND/EXOR cell ( A*B Ea C ), or the basic 2-input AND, OR and EXOR gate. This suggests to using these cells for tree-like expansions. These "cellular logic" devices require regular connection patterns in the netlists resulting from logic synthesis. This thesis presents a synthesis tree searching program PROMPT, which generates AND/EXOR tree circuits from given Boolean functions. Such circuits have the property that the gate structures are AND/EXOR ( A *B EB C ), AND and EXOR which could be realized by the CLI6000 cells. Also, the connection. way in the circuit is that usually the output of one level gate is the input of the next level gate of the tree. This matches ideally to the architecture of the CLI6000 bussing network where the macrocells have only connections to their neighboring cells. PROMPT is based on the Davio expansions ( an equivalent of the Shannon expansions for the EXOR gates ) as its Boolean decomposition methods. The program includes three versions: exact version, heuristic version and fixed-variable version. The exact version of PROMPT generates the Permuted Reed-Muller Tree circuit which has the minimum number of gates. Such tree circuit is obtained by searching through all possible combinations of the expansion variable orders to get the one which needs the least number of gates. The heuristic version of PROMPT is designed to decrease the time complexity of the search algorithm when dealing with logic functions having many input variables. It generates a Permuted Reed-Muller Tree which may not have the minimum number of gates. However, the tree searching time in this version decreases tremendously compared to the time necessary in the exact version. The fix-variable version is developed to generate Reed-Muller Tree circuits. Such circuits will have the same expansion variables at the same tree level, so they can be easier routed after the placement to the CLI6000 chips. In short, the program PROMPT generates the PRM and RM tree circuits which are particularly well matched to both the realization of logic cell and connection structure of the CLI6000 device. Thus, the PRM and RM circuits can be easily placed and routed on the CLI6000 FPGAs.

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36

Chadha, Vishal. "Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1126539992.

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37

Al-aqeeli, Abulqadir. "Reconfigurable wavelet-based architecture for pattern recognition applications using a field programmable gate array." Ohio University / OhioLINK, 1998. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1177008904.

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38

Zhuo, Yue. "Timing and Congestion Driven Algorithms for FPGA Placement." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5423/.

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Placement is one of the most important steps in physical design for VLSI circuits. For field programmable gate arrays (FPGAs), the placement step determines the location of each logic block. I present novel timing and congestion driven placement algorithms for FPGAs with minimal runtime overhead. By predicting the post-routing timing-critical edges and estimating congestion accurately, this algorithm is able to simultaneously reduce the critical path delay and the minimum number of routing tracks. The core of the algorithm consists of a criticality-history record of connection edges and a congestion map. This approach is applied to the 20 largest Microelectronics Center of North Carolina (MCNC) benchmark circuits. Experimental results show that compared with the state-of-the-art FPGA place and route package, the Versatile Place and Route (VPR) suite, this algorithm yields an average of 8.1% reduction (maximum 30.5%) in the critical path delay and 5% reduction in channel width. Meanwhile, the average runtime of the algorithm is only 2.3X as of VPR.

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39

Schlottmann, Craig Richard. "Analog signal processing on a reconfigurable platform." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29623.

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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.
Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Ghovanloo, Maysam. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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40

Van, Heerden Hein. "The design and testing of a superconducting programmable gate array." Thesis, Stellenbosch : University of Stellenbosch, 2006. http://hdl.handle.net/10019.1/1644.

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Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2006.
This thesis investigates to the design, analysis and testing of a Superconducting Programmable Gate Array (SPGA). The objective was to apply existing programmable logic concepts to RSFQ circuits and in the process develop a working prototype of a superconducting programmable logic device. Various programmable logic technologies and architectures were examined and compared to find the best solution. Using Rapid Single Flux Quantum (RSFQ) circuits as building blocks, a complete functional design was assembled incorporating a routing architecture and logic blocks. The Large-Scale Integrated circuit (LSI) layout of the final chip is presented and discussed followed by a discussion on testing. This thesis demonstrates the successful implementation of a fully functional reprogrammable logic device using RSFQ circuitry.

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41

Li, Hao. "Low power technology mapping and performance driven placement for field programmable gate arrays." [Tampa, Fla.] : University of South Florida, 2004. http://purl.fcla.edu/fcla/etd/SFE0000523.

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42

Ismailoglu, Ayse Neslin. "Asynchronous Design Of Systolic Array Architectures In Cmos." Phd thesis, METU, 2008. http://etd.lib.metu.edu.tr/upload/12609443/index.pdf.

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In this study, delay-insensitive asynchronous circuit design style has been adopted to systolic array architectures to exploit the benefits of both techniques for improved throughput. A delay-insensitivity verification analysis method employing symbolic delays is proposed for bit-level pipelined asynchronous circuits. The proposed verification method allows datadependent early output evaluation to co-exist with robust delay-insensitive circuit behavior in pipelined architectures such as systolic arrays. Regardless of the length of the pipeline, delay-insensitivity verification of a systolic array with early output evaluation paths in onedimension is reduced to analysis of three adjacent systoles for eight possible early/late output evaluation scenarios. Analyzing both combinational and sequential parts concurrently, delay-insensitivity violations are located and corrected at structural level, without diminishing the early output evaluation benefits. Since symbolic delays are used without imposing any timing constraints on the environment
the method is technology independent and robust against all physical and environmental variations. To demonstrate the verification method, adders are selected for being at the core of data processing systems. Two asynchronous adder topologies in the delay-insensitive dual-rail threshold logic style, having data-dependent early carry evaluation paths, are converted into bit-level pipelined systolic arrays. On these adders, data-dependent delay-insensitivity violations are detected and resolved using the proposed verification technique. The modified adders achieved the targeted O(log2n) average completion time and -as a result of bit-level pipelining- nearly constant throughput against increased bit-length. The delay-insensitivity verification method could further be extended to handle more early output evaluation paths in multi-dimension.

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43

Balijepalli, Heman. "Design, Implementation, and Test of Novel Quantum-dot Cellular Automata FPGAs for the beyond CMOS Era." University of Toledo / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1333730938.

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44

Wijaya, Shierly. "Fixed-point realisation of erbium doped fibre amplifer control algorithms on FPGA." University of Western Australia. School of Electrical, Electronic and Computer Engineering, 2009. http://theses.library.uwa.edu.au/adt-WU2009.0132.

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The realisation of signal processing algorithms in fixed-point offers substantial performance advantages over floating-point realisations. However, it is widely acknowledged that the task of realising algorithms in fixed-point is a challenging one with limited tool support. This thesis examines various aspects related to the translation of algorithms, given in infinite precision or floating-point, into fixed-point. In particular, this thesis reports on the implementation of a given algorithm, an EDFA (Erbium-Doped Fibre Amplifier) control algorithm, on a FPGA (Field Programmable Gate Array) using fixed-point arithmetic. An analytical approach is proposed that allows the automated realisation of algorithms in fixedpoint. The technique provides fixed-point parameters for a given floating-point model that satisfies a precision constraint imposed on the primary output of the algorithm to be realised. The development of a simulation framework based on this analysis allows fixed-point designs to be generated in a shorter time frame. Albeit being limited to digital algorithms that can be represented as a data flow graph (DFG), the approach developed in the thesis allows for a speed up in the design and development cycle, reduces the possibility of error and eases the overall effort involved in the process. It is shown in this thesis that a fixed-point realisation of an EDFA control algorithm using this technique produces results that satisfy the given constraints.

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Keller, Steven. "Group logic array device instructionless system." Thesis, Liverpool John Moores University, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.438863.

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Pearce, Maureen. "Logic synthesis for programmable devices." Thesis, University of Bristol, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.357911.

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Siqueira, Ana Raquel Calais. "An?lise matricial nebulosa de indicadores para apoio a tomada de decis?o na governan?a corporativa de TIC." Pontif?cia Universidade Cat?lica de Campinas, 2013. http://tede.bibliotecadigital.puc-campinas.edu.br:8080/jspui/handle/tede/541.

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Decision making in organizational settings has an implicit risk, since there is a degree of uncertainty about the future, in different areas like economic, governmental, customer and employee behavior, among others. Ergo, increasingly objective and clear tools like systems, processes, standards, practices, etc., must be available, supporting the business decision maker in their complex task. In this context, and given that ITC is the ground to maintain organization s operations in a structured way, the study of Governance Models for ITC is needed to retain and improve its internal controls. However, observing the different perspectives involving investment decision in ITC projects, we can realize how that model s information can be misused, neglected or misrepresented. Therefore, the Fuzzy Logic, that works with imprecision, uncertainty and partial truth, makes possible to translate and treat various scenarios, in order that computers, which deals with the absolute precision, can list and organize the information, supporting the decision making process. This paper proposes a new exempt method for fuzzy analysis, based upon mathematical operations between arrays, which allow the development of simpler and faster computational algorithms, thus increasing its utilization and enabling its codification in any computer language. Three real scenarios were used to verify its feasibility and results validation. Three real case studies were used to verify the method?s feasibility and to validate their results: Support for decision making in ICT corporate governance, analysis and study of the wireline exploration in Brazilian market and support decision making on the offensive element of a wireless network. The achieved results were satisfactory in all three case studies, showing that the method is general and good.
A tomada de decis?o em ambientes organizacionais possui um risco impl?cito, uma vez que existe um grau de incerteza quanto ao futuro, nos diversos ?mbitos: econ?mico, governamental, comportamental dos clientes e funcion?rios, etc. Da? a import?ncia de apoiar o tomador de decis?es empresariais em sua complexa tarefa com ferramentas (sistemas, processos, padr?es, pr?ticas, etc.) cada vez mais objetivas e claras. Neste contexto, e tendo em vista que a Tecnologia da Informa??o e Comunica??o (TIC) ? a base de sustenta??o para que as organiza??es mantenham suas opera??es de forma estruturada, o estudo dos modelos de governan?a em TIC ? necess?rio para manter e melhorar seus controles internos. Por?m, ao observar as diferentes perspectivas que envolvem o processo decis?rio para investimento em projetos de TIC, pode-se identificar a maneira como as informa??es daqueles modelos podem ser mal utilizadas, negligenciadas ou deturpadas. Assim, a L?gica Nebulosa que trabalha com a imprecis?o, incerteza ou verdade parcial torna poss?vel traduzir e tratar diversos cen?rios, de modo que os computadores, que s? conhecem a precis?o absoluta, possam relacionar e organizar as informa??es, apoiando o processo de tomada de decis?o. Este trabalho prop?e um novo m?todo generalista para An?lise Nebulosa, baseado em opera??es entre matrizes matem?ticas, que permite o desenvolvimento de rotinas computacionais mais simples e r?pidas, ampliando consequentemente sua utiliza??o e permitindo sua codifica??o em qualquer linguagem computacional. Para verifica??o de sua viabilidade e valida??o de seus resultados foram utilizados tr?s estudos de caso reais: Apoio ? tomada de decis?o na Governan?a corporativa de TIC, An?lise e estudo da prospec??o da Telefonia Fixa no Brasil e Apoio ? Tomada de Decis?o sobre o elemento ofensivo em uma rede Wireless. O resultado foi satisfat?rio nos tr?s estudos de caso, provando que o m?todo ? generalista e satisfat?rio.

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Choy, C. S. O. "A bipolar multilevel differential logic gate array." Thesis, University of Manchester, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.378029.

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Wang, Michael Chih-Huei 1967. "Delay timing of Sea-of-Wire Array Logic." Thesis, The University of Arizona, 1993. http://hdl.handle.net/10150/291633.

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Sea-of-Wire Array Logic has been developed to support a symbolic layout algorithm realization. A delay timing scheme is needed to direct the placement strategy of the layout. Both SPICE simulation and table lookup method are compared to verify the accuracy of delay estimation. Input waveform distortion is taken into account in the timing analysis, and correction factors are applied to increase the accuracy of delay estimation. A table lookup scheme has shown to be very accurate in comparison with SPICE value. A set of benchmark circuits have been applied to evaluate this table lookup scheme. The results obtained demonstrate a greater than 90% accuracy and five orders of magnitude increase in speed over SPICE simulation.

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Bhupatiraju, Raja D. V. "A comparative study of high speed adders." Ohio : Ohio University, 1999. http://www.ohiolink.edu/etd/view.cgi?ohiou1175891877.

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Dissertations / Theses on the topic 'Logic Arrays'

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