Journal articles: 'Logic Arrays'

1

XIAO, YONG-XIN. "Logic design of decoded-programmable logic arrays." International Journal of Electronics 69, no. 3 (September 1990): 317–25. http://dx.doi.org/10.1080/00207219008920316.

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2

Brandenburg, G., U. Gorschutz, and K. Muller. "Poor man's gate arrays-logic cell arrays." IEEE Transactions on Nuclear Science 35, no. 1 (February 1988): 213–16. http://dx.doi.org/10.1109/23.12710.

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3

Prasanna de Silva, A. "Molecular Logic Gate Arrays." Chemistry - An Asian Journal 6, no. 3 (February 3, 2011): 750–66. http://dx.doi.org/10.1002/asia.201000603.

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4

Glasgow, J. I., M. A. Jenkins, E. Blevis, and M. P. Feret. "Logic programming with arrays." IEEE Transactions on Knowledge and Data Engineering 3, no. 3 (1991): 307–19. http://dx.doi.org/10.1109/69.91061.

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5

Nicolaidis, M., and B. Courtois. "Self-checking logic arrays." Microprocessors and Microsystems 13, no. 4 (May 1989): 281–90. http://dx.doi.org/10.1016/0141-9331(89)90066-5.

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6

Landry, Steve. ""Designer" Logic And Symbols with Logic Cell Arrays." IEEE Micro 7, no. 1 (February 1987): 51–59. http://dx.doi.org/10.1109/mm.1987.304937.

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7

Chen-Wen Wu and P. R. Cappello. "Easily testable iterative logic arrays." IEEE Transactions on Computers 39, no. 5 (May 1990): 640–52. http://dx.doi.org/10.1109/12.53577.

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8

Maundy, Brent. "Designing with programmable logic arrays." Microprocessors and Microsystems 11, no. 9 (November 1987): 475–86. http://dx.doi.org/10.1016/0141-9331(87)90010-x.

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9

Sasao, T. "Multiple-valued logic and optimization of programmable logic arrays." Computer 21, no. 4 (April 1988): 71–80. http://dx.doi.org/10.1109/2.52.

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10

Barkalov, A. A., V. A. Salomatin, K. E. Starodubov, and D. K. Das. "Optimization of mealy automaton logic using programmable logic arrays." Cybernetics and Systems Analysis 27, no. 5 (1992): 789–93. http://dx.doi.org/10.1007/bf01130555.

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11

Mowchenko, J. T., and M. Y. M. Pong. "Clocked ratioed logic for implementing synchronous circuits in logic arrays." Electronics Letters 31, no. 2 (January 19, 1995): 89–90. http://dx.doi.org/10.1049/el:19950095.

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12

Lyul’kin, A. E. "Testing AND-EXOR programmable logic arrays." Russian Microelectronics 29, no. 3 (May 2000): 194–99. http://dx.doi.org/10.1007/bf02773261.

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13

Bo-Gwan Kim and D. L. Dietmeyer. "Multilevel logic synthesis with extended arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 11, no. 2 (1992): 142–57. http://dx.doi.org/10.1109/43.124395.

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14

Murdocca, Miles J., Alan Huang, Jurgen Jahns, and Norbert Streibl. "Optical design of programmable logic arrays." Applied Optics 27, no. 9 (May 1, 1988): 1651. http://dx.doi.org/10.1364/ao.27.001651.

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15

Lehtonen, Eero, Jussi H. Poikonen, Jari Tissari, Mika Laiho, and Lauri Koskinen. "Recursive Algorithms in Memristive Logic Arrays." IEEE Journal on Emerging and Selected Topics in Circuits and Systems 5, no. 2 (June 2015): 279–92. http://dx.doi.org/10.1109/jetcas.2015.2435531.

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16

Manzoul, Mahmoud A. "FAULTS IN FUZZY LOGIC SYSTOLIC ARRAYS." Cybernetics and Systems 21, no. 5 (September 1990): 513–24. http://dx.doi.org/10.1080/01969729008902257.

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17

Somenzi, F., and S. Gai. "Fault detection in programmable logic arrays." Proceedings of the IEEE 74, no. 5 (1986): 655–68. http://dx.doi.org/10.1109/proc.1986.13529.

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18

de Silva, A. Prasanna. "ChemInform Abstract: Molecular Logic Gate Arrays." ChemInform 42, no. 25 (May 26, 2011): no. http://dx.doi.org/10.1002/chin.201125266.

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19

Bolton, Martin, and David Milford. "Using Silvar-Lisco for Logic Cell Array Design." International Journal of Electrical Engineering & Education 26, no. 1-2 (January 1989): 92–99. http://dx.doi.org/10.1177/002072098902600114.

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Instead of gate arrays, the logic cell array (LCA) has been used as the implementation medium in an undergraduate design exercise. Software has been written to link the SL-2000 database to the LCA layout and routing system (XACT). The result has been improved student motivation and a higher proportion of completed designs.

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20

Apt, Krzysztof R. "Arrays, bounded quantification and iteration in logic and constraint logic programming." Science of Computer Programming 26, no. 1-3 (May 1996): 133–48. http://dx.doi.org/10.1016/0167-6423(95)00020-8.

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21

Nachtergaele, Bruno, and Vipul Periwal. "Quantum gate arrays as coherent sums over classical logic gate arrays." Journal of Physics A: Mathematical and General 30, no. 24 (December 21, 1997): 8685–92. http://dx.doi.org/10.1088/0305-4470/30/24/027.

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22

Bazurin, Vitalii M. "МЕТОДИКА НАВЧАННЯ УЧНІВ РОЗВ’ЯЗУВАННЯ ЗАДАЧ З ОПРАЦЮВАННЯ МАСИВІВ У СЕРЕДОВИЩІ ВІЗУАЛЬНОГО ПРОГРАМУВАННЯ DELPHI." Information Technologies and Learning Tools 47, no. 3 (May 14, 2015): 25. http://dx.doi.org/10.33407/itlt.v47i3.1190.

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Delphi visual programming environment provides ample opportunities for visual mapping arrays. There are a number of Delphi screen form components, which help you to visualize the array on the form. Processing arrays programs in Delphi environment have their differences from the same programs in Pascal. The article describes these differences. Also, the features of student learning methods for solving problems of array processing using Delphi visual components are highlighted. It has been exposed sequence and logic of the teaching material on arrays processing using TStringGrid and TMemo components.

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23

Ting-Ting Hwang, R. M. Owens, M. J. Irwin, and Kuo Hua Wang. "Logic synthesis for field-programmable gate arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13, no. 10 (1994): 1280–87. http://dx.doi.org/10.1109/43.317471.

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24

Qinghong Wu, C. Y. R. Chen, and B. S. Carlson. "LILA: layout generation for iterative logic arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 14, no. 11 (1995): 1359–69. http://dx.doi.org/10.1109/43.469662.

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25

JEWELL, J. L., S. L. McCALL, Y. H. LEE, A. SCHERER, A. C. GOSSARD, and J. H. ENGLISH. "SCALING OF OPTICAL LOGIC DEVICES AND ARRAYS." Le Journal de Physique Colloques 49, no. C2 (June 1988): C2–39—C2–42. http://dx.doi.org/10.1051/jphyscol:1988209.

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26

Samson, Giby, and Lawrence T. Clark. "Low-Power Race-Free Programmable Logic Arrays." IEEE Journal of Solid-State Circuits 44, no. 3 (March 2009): 935–46. http://dx.doi.org/10.1109/jssc.2009.2013764.

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27

Gojman, B., H. Manem, G. S. Rose, and A. DeHon. "Inversion schemes for sublithographic programmable logic arrays." IET Computers & Digital Techniques 3, no. 6 (2009): 625. http://dx.doi.org/10.1049/iet-cdt.2008.0128.

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28

Ratha, N. K., and A. K. Jain. "Computer vision algorithms on reconfigurable logic arrays." IEEE Transactions on Parallel and Distributed Systems 10, no. 1 (1999): 29–43. http://dx.doi.org/10.1109/71.744833.

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29

Cheng, W. T., and J. H. Patel. "Testing in two-dimensional iterative logic arrays." Computers & Mathematics with Applications 13, no. 5-6 (1987): 443–54. http://dx.doi.org/10.1016/0898-1221(87)90074-5.

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30

Hurst, S. L. "Logic synthesis for field-programmable gate arrays." Microelectronics Journal 27, no. 8 (November 1996): 803–4. http://dx.doi.org/10.1016/0026-2692(96)82780-7.

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31

Becker, Bernd, Ralf Hahn, Joachim Hartmann, and Uwe Sparmann. "On the testability of iterative logic arrays." Integration 18, no. 2-3 (June 1995): 201–18. http://dx.doi.org/10.1016/0167-9260(95)00002-w.

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32

Rakos, Balázs. "Coulomb-Coupled, Protein-Based Computing Arrays." Advanced Materials Research 222 (April 2011): 181–84. http://dx.doi.org/10.4028/www.scientific.net/amr.222.181.

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The present work continues the exploration of the potential advantages of proteins in Coulomb-coupled, molecular logic arrays by extending our previous study [1]. We show through simulations that the utilization of certain advantageous potential energy curve arrangements provides an alternative means for the realization of protein chains suitable for digital signal propagation, and universal logic gates.

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33

Chin, Scott Y. L., Clarence S. P. Lee, and Steven J. E. Wilton. "On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays." International Journal of Reconfigurable Computing 2008 (2008): 1–13. http://dx.doi.org/10.1155/2008/751863.

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We investigate the power and energy implications of using embedded FPGA memory blocks to implement logic. Previous studies have shown that this technique provides extremely dense implementations of some types of logic circuits, however, these previous studies did not evaluate the impact on power. In this paper, we measure the effects on power and energy as a function of three architectural parameters: the number of available memory blocks, the size of the memory blocks, and the flexibility of the memory blocks. We show that although embedded memories provide area efficient implementations of many circuits, this technique results in additional power consumption. We also show that blocks containing smaller-memory arrays are more power efficient than those containing large arrays, but for most array sizes, the memory blocks should be as flexible as possible. Finally, we show that by combining physical arrays into larger logical memories, and mapping logic in such a way that some physical arrays can be disabled on each access, can reduce the power consumption penalty. The results were obtained from place and routed circuits using standard experimental physical design tools and a detailed power model. Several results were also verified through current measurements on a 0.13 μm CMOS FPGA.

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34

James, Alex, Olga Krestinskaya, and Akshay Maan. "Recursive Threshold Logic—A Bioinspired Reconfigurable Dynamic Logic System With Crossbar Arrays." IEEE Transactions on Biomedical Circuits and Systems 14, no. 6 (December 2020): 1311–22. http://dx.doi.org/10.1109/tbcas.2020.3027554.

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35

Bo Lu, Yin-Chen Lu, J. Cheng, M. J. Hafich, J. Klem, and J. C. Zolper. "High-speed, cascaded optical logic operations using programmable optical logic gate arrays." IEEE Photonics Technology Letters 8, no. 1 (January 1996): 166–68. http://dx.doi.org/10.1109/68.475814.

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36

Laskowski, Michael C., and Caroline A. Terry. "Uniformly Bounded Arrays and Mutually Algebraic Structures." Notre Dame Journal of Formal Logic 61, no. 2 (May 2020): 265–82. http://dx.doi.org/10.1215/00294527-2020-0004.

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37

Takahashi, Yasuo, Shinichiro Ueno, and Masashi Arita. "Multifunctional Logic Gate by Means of Nanodot Array with Different Arrangements." Journal of Nanomaterials 2013 (2013): 1–7. http://dx.doi.org/10.1155/2013/702094.

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Multifunctional logic gate devices consisting of a nanodot array are studied from the viewpoint of single electronics. In a nanodot array, the dots come in a random variety of sizes, which sometimes has a negative effect on the performance of electrical device applications. Here, this feature is used in a positive sense to achieve higher functionality in the form of flexible logic gates with low power consumption in which the variability of logic functions is guaranteed. Nanodot arrays with two input gates and one control gate in a variety of arrangements are considered, in which the two-input logic functions (such as NAND, NOR, or exclusive-OR (XOR) gates) are selected by changing the voltage applied to the control gate. To ensure the flexibility of the device, it is important to guarantee the performance with any one of the six important logic functions: NAND, AND, NOR, OR, XOR, and XNOR. We ran a selection simulation using a nanodot array consisting of six nanodots with different dot arrangements to clarify the relation between the variability of the logic functions and the dot arrangements.

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38

Yang, Ted C., and Che W. Chiou. "Universal syndrome-testable design of programmable logic arrays." Integration 10, no. 1 (September 1990): 3–8. http://dx.doi.org/10.1016/s0167-9260(05)80031-8.

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39

Serra, M., and J. C. Muzio. "Testing Programmable Logic Arrays by Sum of Syndromes." IEEE Transactions on Computers C-36, no. 9 (September 1987): 1097–101. http://dx.doi.org/10.1109/tc.1987.5009540.

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40

Fuchs, W. K., C. Y. R. Chen, and J. A. Abraham. "Concurrent error detection in highly structured logic arrays." IEEE Journal of Solid-State Circuits 22, no. 4 (August 1987): 583–94. http://dx.doi.org/10.1109/jssc.1987.1052776.

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41

Chen, Congzhou, Jin Xu, and Xiaolong Shi. "Multiform DNA origami arrays using minimal logic control." Nanoscale 12, no. 28 (2020): 15066–71. http://dx.doi.org/10.1039/d0nr00783h.

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42

Reiss, G., and D. Meyners. "Reliability of field programmable magnetic logic gate arrays." Applied Physics Letters 88, no. 4 (January 23, 2006): 043505. http://dx.doi.org/10.1063/1.2167609.

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43

Lu, Shyue-Kung, Cheng-Wen Wu, and Ruei-Zong Hwang. "Cell delay fault testing for iterative logic arrays." Journal of Electronic Testing 9, no. 3 (December 1996): 311–16. http://dx.doi.org/10.1007/bf00134694.

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44

Saluja, K. K., C. Y. Liu, and S. M. Reddy. "Detection of bridging faults in programmable logic arrays." Electronics Letters 28, no. 13 (1992): 1226. http://dx.doi.org/10.1049/el:19920774.

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45

Shyue-Kung Lu, Jen-Chuan Wang, and Cheng-Wen Wu. "C-testable design techniques for iterative logic arrays." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3, no. 1 (March 1995): 146–52. http://dx.doi.org/10.1109/92.365462.

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46

Tirumalai, P. P., and J. T. Butler. "Minimization algorithms for multiple-valued programmable logic arrays." IEEE Transactions on Computers 40, no. 2 (1991): 167–77. http://dx.doi.org/10.1109/12.73587.

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47

Fordyce, Kenneth, Manuel Alfonseca, James Brown, and Gerald Sullivan. "Solving two-state logic problems with Boolean arrays." ACM SIGAPL APL Quote Quad 22, no. 4 (June 1992): 10–11. http://dx.doi.org/10.1145/140660.140673.

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48

Breuer, M. A., and F. Saheban. "Built-in test for folded programmable logic arrays." Microprocessors and Microsystems 11, no. 6 (July 1987): 319–29. http://dx.doi.org/10.1016/0141-9331(87)90476-5.

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49

Jing-Jou Tang, Kuen-Jong Lee, and Bin-Da Liu. "A graph representation for programmable logic arrays to facilitate testing and logic design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17, no. 10 (1998): 1030–43. http://dx.doi.org/10.1109/43.728922.

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50

TAYARI, MAHSHID, and MOHAMMAD ESHGHI. "DESIGN OF 3-INPUT REVERSIBLE PROGRAMMABLE LOGIC ARRAY." Journal of Circuits, Systems and Computers 20, no. 02 (April 2011): 283–97. http://dx.doi.org/10.1142/s0218126611007256.

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In this paper, for the first time a design for a Reversible Programmable Logic Array (RPLA) is introduced. This is the first RPLA design because the reversible PLA design, presented in previous research, is not a programmable circuit. In our presented RPLAs, four reversible AND array designs with different specifications are proposed. A reversible OR array, which can be programmed to generate any Boolean function, is also designed. This reversible and programmable OR array is also cascadable. That is, it produces a copy of inputted midterms at its outputs to be fed to another OR array in order to design another Boolean function, with no need for another AND array. The proposed 3-input RPLA is programmed to design three reversible circuits, a 1-bit full adder, a 1-bit full subtractor, and a 2-to-1 line multiplexer. Five figures of merit, including number of gates, number of constant inputs, number of garbage outputs, depth and quantum cost of the circuit are considered to evaluate and compare the designs. A comparison between the proposed reversible AND arrays and the same circuit presented in previous research, against these figures of merit, shows a better performance of our proposed designs. The proposed RPLAs are also evaluated, using these five figures of merit.

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Journal articles on the topic 'Logic Arrays'

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