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Relevant bibliographies by topics / Logic circuit design / Dissertations / Theses

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Dissertations / Theses on the topic 'Logic circuit design'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Chen, Kailiang. "Circuit design for logic automata." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/52781.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged from student-submitted PDF version of thesis.<br>Includes bibliographical references (p. 143-148).<br>The Logic Automata model is a universal distributed computing structure which pushes parallelism to the bit-level extreme. This new model drastically differs from conventional computer architectures in that it exposes, ra

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2

Parameswaran, Nair Ravi Sankar. "Delay-insensitive ternary logic (DITL)." Diss., Rolla, Mo. : University of Missouri-Rolla, 2007. http://scholarsmine.umr.edu/thesis/pdf/Parameswaran_Nair_09007dcc803bc548.pdf.

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Thesis (M.S.)--University of Missouri--Rolla, 2007.<br>Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 27, 2007) Includes bibliographical references (p. 55-56).

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3

Ramirez, Ortiz Rolando Carleton University Dissertation Engineering Electronics. "Circuit design rules for mixed static and dynamics CMOS logic circuits." Ottawa, 1999.

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4

Ramirez, Ortiz Rolando. "Circuit design rules for mixed static and dynamic CMOS logic circuits." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp03/NQ37076.pdf.

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5

Eckhardt, James P. "An investigation of high-performance logic circuitry in BiCMOS." Diss., Georgia Institute of Technology, 1990. http://hdl.handle.net/1853/15759.

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6

Sharratt, A. A. "The design of high-speed bipolar current-switched logic gates." Thesis, University of Huddersfield, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.234781.

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7

Hadjinicolaou, M. G. "Synthesis of programmable logic arrays." Thesis, Brunel University, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.371168.

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8

Reich, Christoph. "Qualitative and fuzzy analogue circuit design." Thesis, De Montfort University, 1999. http://hdl.handle.net/2086/4188.

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9

Mallepalli, Samarsen Reddy. "Generic algorithms and NULL Convention Logic hardware implementation for unsigned and signed quad-rail multiplication." Diss., Rolla, Mo. : University of Missouri-Rolla, 2007. http://scholarsmine.umr.edu/thesis/pdf/Mallepalli_09007dcc803c4eec.pdf.

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Thesis (M.S.)--University of Missouri--Rolla, 2007.<br>Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 27, 2007) Includes bibliographical references (p. 66-67).

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10

Padua, C. I. P. S. "A logic synthesis approach to silicon compilation." Thesis, University of Southampton, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.381234.

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11

Tang, Xun. "Diagnosis Of VLSI circuit defects: defects in scan chain and circuit logic." Diss., University of Iowa, 2010. https://ir.uiowa.edu/etd/894.

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Given a logic circuit that fails a test, diagnosis is the process of narrowing down the possible locations of the defects. Diagnosis to locate defects in VLSI circuits has become very important during the yield ramp up process, especially for 90 nm and below technologies where physical failure analysis machines become less successful due to reduced defect visibility by the smaller feature size and larger leakage currents. Successful defect isolation relies heavily on the guidance from fault diagnosis and will depend even more for the future technologies. To assist a designer or a failure analy

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12

Clarke, Christopher T. "The implementation and applications of multiple-valued logic." Thesis, University of Warwick, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.386944.

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13

Gani, Sohail M. "A gate matrix approach to VLSI logic layout." Thesis, University of Essex, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.238380.

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14

Dhingra, Inderpreet Singh. "Formalising an integrated circuit design style in higher order logic." Thesis, University of Cambridge, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.278296.

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15

Sah, Puja. "Implementing Digital Logic Design Concepts Using Paper Electronics." Thesis, University of North Texas, 2018. https://digital.library.unt.edu/ark:/67531/metadc1157633/.

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This thesis presents the implementation of some of the basic concepts of digital logic design in a fun and creative way with the help of paper electronics. This involves circuit building on paper using conductive tape or conductive ink and circuit components as electronics craft materials. Paper electronics toolkit called circuit sticker microcontroller which is deployed by a company named Chibitronics and AT89C51 microcontroller were used for the computational functioning of the circuits built on paper. This can be used to teach the fundamentals of digital logic design to the students in thei

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16

Niewenhuis, Benjamin T. "A Logic Test Chip for Optimal Test and Diagnosis." Research Showcase @ CMU, 2018. http://repository.cmu.edu/dissertations/1176.

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The benefits of the continued progress in integrated circuit manufacturing have been numerous, most notably in the explosion of computing power in devices ranging from cell phones to cars. Key to this success has been strategies to identify, manage, and mitigate yield loss. One such strategy is the use of test structures to identify sources of yield loss early in the development of a new manufacturing process. However, the aggressive scaling of feature dimensions, the integration of new materials, and the increase in structural complexity in modern technologies has challenged the capabilities

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17

MAO, WUJIN. "DESIGN AND TEST GENERATION FOR CLOCK SKEW FAULTS OF CLOCK-DELAYED DOMINO LOGIC CIRCUITS." University of Cincinnati / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1175553714.

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18

Zheng, Yexin. "Circuit Design Methods with Emerging Nanotechnologies." Diss., Virginia Tech, 2009. http://hdl.handle.net/10919/30000.

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As complementary metal-oxide semiconductor (CMOS) technology faces more and more severe physical barriers down the path of continuously feature size scaling, innovative nano-scale devices and other post-CMOS technologies have been developed to enhance future circuit design and computation. These nanotechnologies have shown promising potentials to achieve magnitude improvement in performance and integration density. The substitution of CMOS transistors with nano-devices is expected to not only continue along the exponential projection of Moore's Law, but also raise significant challenges and

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19

Diril, Abdulkadir Utku. "Circuit Level Techniques for Power and Reliability Optimization of CMOS Logic." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6929.

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Technology scaling trends lead to shrinking of the individual elements like transistors and wires in digital systems. The main driving force behind this is cutting the cost of the systems while the systems are filled with extra functionalities. This is the reason why a 3 GHz Intel processor now is priced less than what a 50MHz processor was priced 10 years ago. As in most cases, this comes with a price. This price is the complex design process and problems that stem from the reduction in physical dimensions. As the transistors became smaller in size and the systems became faster, issues like

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20

Bavaresco, Simone. "On-silicon testbench for validation of soft logic cell libraries." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2008. http://hdl.handle.net/10183/14907.

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Projeto baseado em células-padrão é a abordagem mais aplicada no mercado de ASIC atualmente. Essa abordagem de projeto consiste no reuso de bibliotecas de células pré-customizadas para gerar sistemas digitais mais complexos. Portanto a eficiência de um projeto ASIC está relacionado com a biblioteca em uso. A utilização de portas lógicas CMOS geradas automaticamente no fluxo de projeto de circuito integrado baseado em células-padrão representa uma perspectiva atraente para melhorar a qualidade de projeto ASIC. Essas células geradas por software são os elementos-chave dessa nova abordagem de map

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21

Srinivasan, Venkataramanujam. "Gigahertz-Range Multiplier Architectures Using MOS Current Mode Logic (MCML)." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/9643.

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The tremendous advancement in VLSI technologies in the past decade has fueled the need for intricate tradeoffs among speed, power dissipation and area. With gigahertz range microprocessors becoming commonplace, it is a typical design requirement to push the speed to its extreme while minimizing power dissipation and die area. Multipliers are critical components of many computational intensive circuits such as real time signal processing and arithmetic systems. The increasing demand in speed for floating-point co-processors, graphic processing units, CDMA systems and DSP chips has shaped the ne

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22

Bortolon, Felipe Todeschini. "Static noise margin analysis for CMOS logic cells in near-threshold." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2018. http://hdl.handle.net/10183/178664.

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Os avanços na tecnologia de semicondutores possibilitou que se fabricasse dispositivos com atividade de chaveamento mais rápida e com maior capacidade de integração de transistores. Estes avanços, todavia, impuseram novos empecilhos relacionados com a dissipação de potência e energia. Além disso, a crescente demanda por dispositivos portáteis levaram à uma mudança no paradigma de projeto de circuitos para que se priorize energia ao invés de desempenho. Este cenário motivou à reduzir a tensão de alimentação com qual os dispositivos operam para um regime próximo ou abaixo da tensão de limiar, co

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23

Luria, David M. "Logic Encryption for Resource Constrained Designs." University of Cincinnati / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1613742372174729.

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24

Lackmann-Zimpeck, Alexandra. "Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells." Thesis, Toulouse, ISAE, 2019. http://www.theses.fr/2019ESAE0026/document.

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Les contraintes imposées par la roadmap technologique nanométrique imposent aux fabricants de microélectronique une réduction de la variabilité de fabrication mais également de durcissement vis-à-vis des erreurs logiques induits par l’environnement radiatif naturel afin d’assurer un haut niveau de fiabilité. Certains travaux ont mis en évidence l'influence de la variabilité de fabrication et SET sur les circuits basés sur les technologies FinFET. Cependant jusqu’à lors, aucune approche pour les atténuer n’ont pu être présenté pour les technologies FinFET. Pour ces raisons, du point de vue de l

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25

Imvidhaya, Ming. "VHDL simulation of the implementation of a costfunction circuit." Thesis, Monterey, California : Naval Postgraduate School, 1990. http://handle.dtic.mil/100.2/ADA240430.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, September 1990.<br>Thesis Advisor(s): Lee, Chin-Hwa. Second Reader: Butler, Jon T. "September 1990." Description based on title screen as viewed on December 29, 2009. DTIC Identifier(s): Computerized simulation, computer aided design, logic circuits, subroutines, theses, integrated circuits. Author(s) subject terms: VHDL, costfunction, hardware description language. Includes bibliographical references (p. 77). Also available in print.

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26

Heim, Marcus Edwin Allan. "ANALYSIS OF MOS CURRENT MODE LOGIC (MCML) AND IMPLEMENTATION OF MCML STANDARD CELL LIBRARY FOR LOW-NOISE DIGITAL CIRCUIT DESIGN." DigitalCommons@CalPoly, 2015. https://digitalcommons.calpoly.edu/theses/1422.

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MOS current mode logic (MCML) offers low noise digital circuits that reduce noise that can cripple analog components in mixed-signal integrated circuits, when compared to CMOS digital circuits. An MCML standard cell library was developed for the Cadence Virtuoso Integrated Circuit (IC) design software that gives IC designers the ability to design complex, low noise digital circuits for use in mixed-signal and noise sensitive systems at a high level of abstraction, allowing them to get superior products to market faster than competitors. The MCML standard cell library developed and presented he

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27

Dal, Bem Vinícius. "CMOS digital integrated circuit design faced to NBTI and other nanometric effects." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2010. http://hdl.handle.net/10183/37180.

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Esta dissertação explora os desafios agravados pela miniaturização da tecnologia na fabricação e projeto de circuitos integrados digitais. Os efeitos físicos do regime nanométrico reduzem o rendimento da produção e encurtam a vida útil dos dispositivos, restringindo a utilidade dos padrões de projeto convencionais e ameaçando a evolução da tecnologia CMOS como um todo. Nesta dissertação é exposta uma consistente revisão bibliográfica dos principais efeitos físicos parasitas presentes no regime nanométrico. Como o NBTI tem recebido destaque na literatura relacionada à confiabilidade de circuito

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28

Lee, Chris Y. "Full Custom VLSI Design of On-Line Stability Checkers." DigitalCommons@CalPoly, 2011. https://digitalcommons.calpoly.edu/theses/607.

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A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly. A meth

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29

Tennakoon, Hiran Kasturiratne. "Efficient and accurate gate sizing with piecewise convex delay models /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/5999.

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30

Cornelia, Olivian E. "Conditional stuck-at fault model for PLA test generation." Thesis, McGill University, 1987. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63959.

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31

Lopes, Jeremy. "Design of an Innovative GALS (Globally Asynchronous Locally Synchronous), Non-Volatile Integrated Circuit for Space Applications." Thesis, Montpellier, 2017. http://www.theses.fr/2017MONTS052/document.

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Aujourd'hui, il existe plusieurs façons de développer des circuits microélectroniques adaptés aux applications spatiales qui répondent aux contraintes sévères de l'immunité contre les radiations, que ce soit en termes de technique de conception ou de processus de fabrication. Le but de ce doctorat est d'une part de combiner plusieurs techniques nouvelles de microélectronique pour concevoir des architectures adaptées à ce type d'application et d'autre part, d'incorporer des composants magnétiques non-volatiles intrinsèquement robustes aux rayonnements. Un tel couplage serait tout à fait novateu

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32

Butzen, Paulo Francisco. "Aging aware design techniques and CMOS gate degradation estimative." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/61868.

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O advento da utilização de circuitos integrados pela sociedade se deu por dois motivos. O primeiro consiste na miniaturização das dimensões dos dispositivos integrados. Essa miniaturização permitiu a construção de dispositivos menores, mais rápidos e que consomem menos frequência. O outro fator é a utilização da metodologia baseada em biblioteca de células. Esta metodologia permite o projeto de um circuito eficiente em um curto espaço de tempo. Com a redução dos dispositivos, novos fatores que eram desconsiderados no fluxo automático passaram a ter importância. Dentre eles podemos citar o cons

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33

Chadha, Vishal. "Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1126539992.

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34

Venkataraman, Mahalingam. "Techniques for VLSI Circuit Optimization Considering Process Variations." Scholar Commons, 2009. https://scholarcommons.usf.edu/etd/66.

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Technology scaling has increased the transistor's susceptibility to process variations in nanometer very large scale integrated (VLSI) circuits. The effects of such variations are having a huge impact on performance and hence the timing yield of the integrated circuits. The circuit optimization objectives namely power, area, and delay are highly correlated and conflicting in nature. The inception of variations in process parameters have made their relationship intricate and more difficult to optimize. Traditional deterministic methods ignoring variation effects negatively impacts timing yield.

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35

An, Qi. "Modélisation compacte et conception de circuit à base d'injection de spin." Thesis, Université Paris-Saclay (ComUE), 2017. http://www.theses.fr/2017SACLS240/document.

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La technologie CMOS a contribué au développement de l'industrie des semi-conducteurs. Cependant, au fur et à mesure que le noeud technologique est réduit, la technologie CMOS fait face à des défis importants liés à la dissipation dûe aux courants de fuite et aux effets du canal court. Pour résoudre ce problème, les chercheurs se sont intéressés à la spintronique ces dernières années, compte tenu de la possibilité de fabriquer des dispositifs de taille réduite et d'opérations de faible puissance. La jonction tunnel magnétique (MTJ) est l'un des dispositifs spintroniques les plus importants qui

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36

Schreiber, Jansch Ingrid Eleonora. "Conception de contrôleurs autotestables pour des hypothèses de pannes analytiques." Phd thesis, Grenoble INPG, 1985. http://tel.archives-ouvertes.fr/tel-00319479.

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Contrôleurs utilisés dans les systèmes autotestables pour le test des sorties combinatoires ou séquentielles. Conception des contrôleurs NMOS à partir de l'assemblage des cellules, des règles de conception pour celle-ci, et des hypothèses de pannes pouvant survenir. Les considérations pratiques sont basées sur des hypothèses de pannes analytiques

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37

Boussetta, Chokri. "Modélisation électromagnétique des interconnexions en micro-onde et en logique rapide." Grenoble INPG, 1996. http://www.theses.fr/1996INPG0153.

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La modelisation electromagnetique est un outil tres important dans l'amelioration des performances des circuits logiques rapides. La haute densite d'integration et la diminution du temps de montee necessite l'utilisation des cao de plus en plus performants. Ces outils doivent integrer une caracterisation precise des interconnexions, et plus particulierement des discontinuites. Parmi les differents methodes de caracterisation et de modelisation en hyperfrequence qui ont ete developpes, nous avons choisi la methode tlm. Nous avons mis au point un logiciel d'extraction des elements des schemas eq

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38

Hanriat, Stéphane. "Synthèse logique à base de règles pour les compilateurs de silicium." Phd thesis, Grenoble INPG, 1986. http://tel.archives-ouvertes.fr/tel-00322203.

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L'optimisation de la synthèse logique de circuits dépend de la structure matérielle cible pour les circuits combinatoires (logique aléatoire, réseaux prédiffusés, PLA...) ainsi que de l'architecture choisie par le concepteur pour les circuits plus complexes (contrôleur). On propose un système de synthèse flexible à base de règles (système ASYL). Ces règles traduisent les critères d'optimisation des structures cibles ainsi que les choix de conception. L'illustration pratique concerne essentiellement la synthèse des fonctions booléennes sur PLA et la synthèse de contrôleur

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39

Benhaddou, Mohamed. "Définition d'une méthodologie de conception de circuits intégrés numériques indépendante de la technologie : application à la conception d'un processeur flou." Vandoeuvre-les-Nancy, INPL, 1995. http://www.theses.fr/1995INPL067N.

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Les technologies de fabrication de circuits intégrés numériques et les outils de CAO pour la conception de ceux-ci ont régulièrement évolué. La tendance actuelle est de décrire le comportement du concept à un niveau d'abstraction élevé à l'aide d'un langage de description du matériel standard comme Verilog ou VHDL, et laisser le soin aux outils de synthèse de générer les masques du circuit ou sa liste d'équipotentielles dans la bibliothèque d'un fondeur. Le problème est le prix élevé de ces outils de synthèse de haut niveau qui est dissuasif pour les PME/PMI. L’objectif de ce travail est de mo

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40

Jebelli, Ali. "Design of an Autonomous Underwater Vehicle with Vision Capabilities." Thesis, Université d'Ottawa / University of Ottawa, 2016. http://hdl.handle.net/10393/35358.

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In the past decade, the design and manufacturing of intelligent multipurpose underwater vehicles has increased significantly. In the wide range of studies conducted in this field, the flexibility and autonomy of these devices with respect to their intended performance had been widely investigated. This work is related to the design and manufacturing of a small and lightweight autonomous underwater vehicle (AUV) with vision capabilities allowing detecting and contouring obstacles. It is indeed an exciting challenge to build a small and light submarine AUV, while making tradeoffs between

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Perez, Segovia Tomás. "Paola : un système d'optimisation topologique de PLA." Grenoble INPG, 1985. http://tel.archives-ouvertes.fr/tel-00316330.

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Lors de la conception des circuits intégrés VLSI, les Réseaux Logiques Programmables (P. L. A. ) permettent le dessin automatique des masques à partir d'une description logique. La surface occupée par ces PLAs peut, dans certains cas, s'avérer prohibitive; d'où l'intérêt des méthodes d'optimisation topologique de ceux-ci. Après avoir défini les différentes représentations possibles des PLAs, on présente l'état en ce qui concerne l'optimisation topologique des PLAs. La méthode des «Lignes Brisées» est ensuite détaillée en insistant sur les heuristiques choisies ainsi que sur les interactions qu

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42

Mohamed, Mohamed Hassan Wahba Ayman. "Diagnostic des erreurs de conception dans les circuits digitaux : le cas des erreurs simples." Grenoble 1, 1997. http://www.theses.fr/1997GRE10086.

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Le diagnostic automatique des erreurs de conception est un probleme important dans le domaine de la cao. Bien que des outils automatises de synthese soient employes pour generer des structures de circuits correctes-par-construction, celles-ci sont souvent modifiees manuellement pour refleter des petites modifications faites sur la specification, ou pour ameliorer certaines caracteristiques critiques de la conception. Les outils de verification peuvent reveler l'existence d'erreurs, mais ils ne donnent aucune information sur leurs emplacements ou la facon de les corriger. Ces outils generent se

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43

Dekhissi, Habri. "Etude des performances des technologies HCMOS 3 et HCMOS 4." Grenoble 2 : ANRT, 1987. http://catalogue.bnf.fr/ark:/12148/cb37604368s.

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44

Belhadj, Mohamed Hichem. "Spécification et synthèse de systèmes à controle intensif." Grenoble INPG, 1996. http://www.theses.fr/1996INPG0084.

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La realisation avec succes de nouveaux produits fiables, performants et peu couteux est le resume des defis actuels du marche de l'electronique. Relever ces defis passe par un bon choix des moyens de modelisation et de specification et par l'utilisation d'outils specifiques aux applications visees et aux technologies cibles. Cette these propose quelques elements de reponse pour la specification et la synthese des systemes a controle intensif sur les technologies programmables du type fpga et cpld. Les aspects de specification etudies sont relatifs aux modeles abstraits, aux langages de descrip

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45

Kalganova, Tatiana. "Evolvable hardware design of combinational logic circuits." Thesis, Edinburgh Napier University, 2000. http://researchrepository.napier.ac.uk/Output/4341.

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Evolvable Hardware (EHW), as an alternative method for logic design, became more attractive recently, because of its algebra-independent techniques for generating selfadaptive self-reconfigurable hardware. This thesis investigates and relates both evaluation and evolutionary processes, emphasizing the need to address problems arising from data complexity. Evaluation processes, capable of evolving cost-optimised fully functional circuits are investigated. The need for an extrinsic EHW approach (software models) independent of the concerns of any implementation technologies is emphasized. It is

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46

Minařík, Vojtěch. "Využití SAT solverů v úloze optimalizace kombinačních obvodů." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2019. http://www.nusl.cz/ntk/nusl-399701.

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This thesis is focused on the task of application of SAT problem and it's modifications in area of evolution logic circuit development. This task is supposed to increase speed of evaluating candidate circuits by fitness function in cases where simulation usage fails. Usage of SAT and #SAT problems make evolution of complex circuits with high input number significantly faster. Implemented solution is based on #SAT problem. Two applications were implemented. They differ by the approach to checking outputs of circuit for wrong values. Time complexity of implemented algorithm depends on logical co

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47

Nguyen, Loc Bao. "Logic design using programmable logic devices." PDXScholar, 1988. https://pdxscholar.library.pdx.edu/open_access_etds/4103.

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The Programmable Logic Devices, PLO, have caused a major impact in logic design of digital systems in this decade. For instance, a twenty pin PLO device can replace from three hundreds to six hundreds Transistor Transistor Logic gates, which people have designed with since the 60s. Therefore, by using PLD devices, designers can squeeze more features, reduce chip counts, reduce power consumption, and enhance the reliability of the digital systems. This thesis covers the most important aspects of logic design using PLD devices. They are Logic Minimization and State Assignment. In addition, the t

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Liu, Tai-hung. "Logic synthesis for high-performance digital circuits /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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Chong, Kian Haur. "Self-calibrating differential output prediction logic /." Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/5985.

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Ramakrishnan, Lakshmi Narasimhan. "SDMLp - Secure Differential Multiplexer Logic : Logic Design for DPA-Resistant Cryptographic Circuits." University of Cincinnati / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1311691925.

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