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Journal articles on the topic 'Logic circuit design'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Bundalo, Dusanka, Zlatko Bundalo, and Branimir Ðordjevic. "Design of quaternary logic systems and circuits." Facta universitatis - series: Electronics and Energetics 18, no. 1 (2005): 45–56. http://dx.doi.org/10.2298/fuee0501045b.

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The principles and possibilities of design of fully quaternary multiple valued combinational logic systems and circuits are described and proposed in the paper. Different ways of design of fully quaternary combinational logic systems and circuits are considered and described first. Then algorithm for automated computerized design of such systems and circuits is considered and proposed. The algorithm gives possibility for synthesis and optimization of quaternary logic systems and circuits. It is applied on design of CMOS quaternary multiple valued logic systems and circuits. The algorithm inclu

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Sun, Junwei, Qinfei Yang, and Yanfeng Wang. "Memristive Circuit Design of Five-Person Voter Based on Memristor Ratioed Logic." Journal of Nanoelectronics and Optoelectronics 15, no. 12 (2020): 1482–93. http://dx.doi.org/10.1166/jno.2020.2895.

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Conventional CMOS-based logic circuits are approaching their limits when it comes to speed and energy consumption, so the development of new electronic components becomes critical. Memristor is a nano-structured special electronic device with the advantages of simple structure, low power consumption and easy integration. This invention supplys a new method for developing complex logic circuits. This article mainly presents the design of a five-person voter circuit. The OR/AND logic can be accomplished by varying the polarity of two parallel memristors. On the basis of the two logic circuits, a

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Shi, Jian Ying, Hui Ya Li, and Yan Bin Xu. "Design of the Approved Low Power Energy Recovery Logic Circuit." Advanced Materials Research 662 (February 2013): 851–55. http://dx.doi.org/10.4028/www.scientific.net/amr.662.851.

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An approved energy recovery logic circuit (AERL) was designed in this paper. In order to further reduce the power consumption of energy recovery logic circuits, the NMOS transmission gate and NMOS bootstrap technique ware used. The characteristics of the AERL circuit ware simulated using 0.5 micrometer BSIM3V3 spice models in HSPICE. The results show that the AERL circuit has much lower power consumption compared with PT-BCRL, BERL, ECRL and 2N2N-2P logic.

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Koshy, Kamal J., and Poras T. Balsara. "QMOS digital logic circuit design." International Journal of Electronics 87, no. 5 (2000): 531–45. http://dx.doi.org/10.1080/002072100131968.

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Sasipriya, P., and V. S. Kanchana Bhaaskaran. "Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL)." Journal of Circuits, Systems and Computers 27, no. 04 (2017): 1850052. http://dx.doi.org/10.1142/s0218126618500524.

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This paper presents the quasi-adiabatic logic for low power powered by two phase sinusoidal clock signal. The proposed logic called two phase adiabatic dynamic logic (2PADL) realizes the advantages of energy efficiency through the use of gate overdrive and reduced switching power. It has a single rail output and the proposed logic does not require the complementary input signals for any of its variables. The 2PADL logic is operated by two complementary clock signals acting as power supply. The validation of the proposed logic is carried out through practical circuits such as (i) sequential cir

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Reis, Cecília, J. A. Tenreiro Machado, and J. Boaventura Cunha. "Evolutionary Design of Combinational Logic Circuits." Journal of Advanced Computational Intelligence and Intelligent Informatics 8, no. 5 (2004): 507–13. http://dx.doi.org/10.20965/jaciii.2004.p0507.

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This paper proposes a genetic algorithm for designing combinational logic circuits and studies four different case examples: 2-to-1 multiplexer, one-bit full adder, four-bit parity checker and a two-bit multiplier. The objective of this work is to generate a functional circuit with the minimum number of gates.

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Neutzling, Augusto, Jody Maick Matos, Alan Mishchenko, Andre Reis, and Renato P. Ribas. "Effective Logic Synthesis for Threshold Logic Circuit Design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38, no. 5 (2019): 926–37. http://dx.doi.org/10.1109/tcad.2018.2834434.

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Li, Ji-Xiang, Yan-Feng Wang, and Jun-Wei Sun. "Odd Judgment Circuit of Four Inputs Based on DNA Strand Displacement." Journal of Nanoelectronics and Optoelectronics 15, no. 3 (2020): 415–24. http://dx.doi.org/10.1166/jno.2020.2718.

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In the development of electronic technology integrated circuits, researchers focus on new calculation methods and new calculation models. The alternative technology of DNA strands is the rapid development of existed biotechnological methods for calculating new types of faster growth. In addition, a new idea for the odd judgment logic circuit based on DNA strand displacement reaction technology is proposed to solve practical problems in mathematics, and which is widely used for those various logic circuits and computing systems to acquire important roles in biological computers. The operational

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9

Avdeev, N. A., and P. N. Bibilo. "Design of Digital Operational Units with Low Power Consumption." Programmnaya Ingeneria 12, no. 2 (2021): 63–73. http://dx.doi.org/10.17587/prin.12.63-73.

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The lowering of power consumption in CMOS VLSI digital systems is one of the most important problems that appear now for developers of CAD systems. One of the effective approaches to lowering the dynamic power consumption is creation of an algorithmic description of the VHDL project, which provides for the deactivation of some functional blocks which are not necessary in particular moments. Contemporary synthesizers fulfill the high level synthesis of logic circuits by substitution of description of each VHDL construction with functionally structural description of a proper logic subcircuit. T

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Kumar, Manish, Md Anwar Hussain, and Sajal K. Paul. "Effective Circuit Design Methodologies for Standby Leakage Power Reduction." Advanced Science, Engineering and Medicine 12, no. 2 (2020): 168–72. http://dx.doi.org/10.1166/asem.2020.2484.

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This paper presents circuit level design methodologies for significantly reducing the standby leakage power. Layout of different CMOS logic circuits such as a 2-input XOR, a 2-input XNOR, and a 4-input XNOR are designed and simulated by using BSIM4 MOS transistor model parameters. Layout simulations are done at a supply voltage of 0.4 V in 45 nm CMOS technology. Logic circuits designed by using the proposed circuit design methodologies proved to be effective in minimizing the standby leakage power. All layout design and simulation of the circuits are carried out by using Microwind EDA software

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11

Lin, Shan, Tao Lin, and Zhan Wen Liu. "A Discussion of the Design Method of Full Adder Circuit." Applied Mechanics and Materials 135-136 (October 2011): 15–20. http://dx.doi.org/10.4028/www.scientific.net/amm.135-136.15.

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A bit full adder is a very important component in the digital system. Design of a full-adder circuit, as an example, by changing its output function expression in the form of expression, use the gates, decoder, multiplexer etc 74 series devices, the eight circuits realization form are given respectively, and briefly analyzed the advantages and disadvantages of the various circuit implementation. The example show that the design of combinational logic circuits has mobility and variety, it could give the instructiveness and the guiding for other design of combinational logic circuits.

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Upadhyay, Shipra, R. A. Mishra, R. K. Nagaria, and S. P. Singh. "DFAL: Diode-Free Adiabatic Logic Circuits." ISRN Electronics 2013 (February 10, 2013): 1–12. http://dx.doi.org/10.1155/2013/673601.

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The manufacturing advances in semiconductor processing (continually reducing minimum feature size of transistors, increased complexity and ever increasing number of devices on a given IC) change the design challenges for circuit designers in CMOS technology. The important challenges are low power high speed computational devices. In this paper a novel low power adiabatic circuit topology is proposed. By removing the diode from the charging and discharging path, higher output amplitude is achieved and also the power dissipation of the diodes is eliminated. A mathematical expression has been dev

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Santhi, C., and Dr Moparthy Gurunadha Babu. "Symmetric stacked fast binary counters based on reversible logic." International Journal of Engineering & Technology 7, no. 4 (2018): 2747. http://dx.doi.org/10.14419/ijet.v7i4.14141.

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A Symmetric Stacked Fast Binary counter design is proposed in this paper. In the circuit design, the first phase is occupied by 3-bit stacking circuits, which are further followed by combining circuits. The resultant novel circuit thus becomes a 6-bit stacker. A 6:3 counter has been chosen as an example to demonstrate the working of the proposed circuit. The proposed circuit is further implemented by using reversible logic gates. Heat dissipation is a major problem in the designing of a digital circuit. Rolf Landauer has proved that the information loss in a digital circuit is directly proport

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TAYARI, MAHSHID, and MOHAMMAD ESHGHI. "DESIGN OF 3-INPUT REVERSIBLE PROGRAMMABLE LOGIC ARRAY." Journal of Circuits, Systems and Computers 20, no. 02 (2011): 283–97. http://dx.doi.org/10.1142/s0218126611007256.

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In this paper, for the first time a design for a Reversible Programmable Logic Array (RPLA) is introduced. This is the first RPLA design because the reversible PLA design, presented in previous research, is not a programmable circuit. In our presented RPLAs, four reversible AND array designs with different specifications are proposed. A reversible OR array, which can be programmed to generate any Boolean function, is also designed. This reversible and programmable OR array is also cascadable. That is, it produces a copy of inputted midterms at its outputs to be fed to another OR array in order

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15

Abdulhamid, Mohanad, and Okoth Masimba. "Design of Combinational Logic Circuit Prober." Land Forces Academy Review 24, no. 4 (2019): 317–25. http://dx.doi.org/10.2478/raft-2019-0040.

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Abstract The objective of this paper is to design and implement a logic circuit prober to display truth tables of a three input combinational logic circuit. The truth table is to be as “1” and “0” on an ordinary 60 MHz oscilloscope. This paper meets this objective by using Lissajous Patterns to plot a “0” or a “1” on the oscilloscope screen. To plot a “0” on the oscilloscope screen, two sinusoidal signals in quadrature are supplied to the two inputs of the oscilloscope with the scope set to X-Y mode. To plot a “1” on the oscilloscope, only the signal to the Y input is allowed to reach the osci

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16

Shukla, Vandana, O. P. Singh, G. R. Mishra, and R. K. Tiwari. "Design and Implementation of Four Bit Binary Shifter Circuit Using Reversible Logic Approach." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 3 (2015): 213. http://dx.doi.org/10.11591/ijres.v4.i3.pp213-218.

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Shifter circuits are the key component of arithmetic logic unit as well as storage unit of any digital computing device. Designing these shifter circuits using reversible logic approach leads to create low power loss digital systems. Reversible circuit design approach is nowadays widely applicable in various disciplines such as Nanotechnology, Low power CMOS design, Optical computing etc. This paper presents two design approaches for four bit binary combinational shifter circuit with the help of different types of reversible logic gates. The proposed optimized design is simulated using Modelsi

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17

TAKAGI, Kazuyoshi, Nobutaka KITO, and Naofumi TAKAGI. "Circuit Description and Design Flow of Superconducting SFQ Logic Circuits." IEICE Transactions on Electronics E97.C, no. 3 (2014): 149–56. http://dx.doi.org/10.1587/transele.e97.c.149.

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18

Verma, Nidhi, and Sanjoy Mandal. "Performance analysis of optical micro-ring resonator as all-optical reconfigurable logic and multiplexer in Z-domain." Journal of Nonlinear Optical Physics & Materials 25, no. 01 (2016): 1650013. http://dx.doi.org/10.1142/s0218863516500132.

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Performance and design methodology of [Formula: see text] multiplexer (MUX) and all-optical reconfigurable logic circuit using GaAs–AlGaAs-based optical micro-ring resonator (OMRR) are presented in current paper. Proposed design of reconfigurable logic circuit is capable to perform eight different logic operations. Performances of the logic circuits have been theoretically analyzed using Z-domain modeling. Numerical simulation results confirming the method are explained in the present paper. Proposed circuit is simple, compact, efficient as it have minimum number of OMRR, low operating power,

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19

WAWRYN, KRZYSZTOF. "AN ARTIFICIAL INTELLIGENCE APPROACH TO ANALOG CIRCUIT DESIGN." Journal of Circuits, Systems and Computers 01, no. 02 (1991): 149–76. http://dx.doi.org/10.1142/s0218126691000033.

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This article deals with a new approach to an intelligent analog circuit design. The iterative closed loop design methodology adopts an expert system approach to provide topological synthesis, the SPICE circuit simulator to evaluate the circuit performance and a new approach of the diagnostic expert system to provide advice on how to improve the design. Unlike previous design methods, this approach introduces formal circuit representation for both numerical and heuristic knowledge of the design system. The predicate logic circuit representation is proposed to introduce a new concept of a formal

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20

Khadir, Mohammad, S. Renukarani, Tunikipati Usharani, and D. Hemanth Kumar. "Design of High Performance Decoder with Mixed Logic Styles." International Journal of Engineering & Technology 7, no. 2.20 (2018): 119. http://dx.doi.org/10.14419/ijet.v7i2.20.12187.

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The CMOS technology is the mostly portable technology used in the designing of the circuits and in its fabrication. Designing of the circuits using CMOS technology requires the high power, high transistors count and low performance. The basic idea of the project is in order to reduce the count of transistors, time delay, and power consumption and to increase the performance of the circuits such as line decoders. The line decoder is a combinational circuits to which „n‟ no .of inputs are given as input and the output is 2^n based on the selected input and it requires 20 and more than 20 transis

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21

Et.al, M. Naga Gowtham. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 3037–45. http://dx.doi.org/10.17762/turcomat.v12i3.1338.

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In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power

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22

K Jeevitha, K Hari Kishore, E Raghuveera, Shaik Razia, M. Naga Gowtham, P. S. Hari Krishna Reddy,. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (2021): 92–100. http://dx.doi.org/10.17762/turcomat.v12i5.734.

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In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power

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23

Weis, M., R. Emling, and D. Schmitt-Landsiedel. "Circuit design with Independent Double Gate Transistors." Advances in Radio Science 7 (May 19, 2009): 231–36. http://dx.doi.org/10.5194/ars-7-231-2009.

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Abstract. Circuits with transistors using independently controlled gates have been proposed to reduce the number of transistors and to increase the logic density per area. This paper introduces a novel Vertical Slit Field Effect Transistor with unique independent double gate properties to demonstrate the possible advantages for independent double gate circuits. A new adder circuit is proposed, where the power could be reduced by one fifth and the area by on third compared to a tied gate configuration.

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Mei, Feng Na, and Peng Jun Wang. "Design of Ternary Clocked Adiabatic Synchronous Reversible Counter." Applied Mechanics and Materials 88-89 (August 2011): 154–59. http://dx.doi.org/10.4028/www.scientific.net/amm.88-89.154.

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Based on the study of synchronous counter and adiabatic circuits, a new design scheme of ternary adiabatic synchronous reversible counter is proposed. According to the theory of three essential circuit elements, circuit structure of four-bit ternary adiabatic synchronous reversible counter is realized by using NMOS transistors with different thresholds and cross-storage structure and combining with the principle of energy recovery. Computer simulation results indicate that the designed circuits have correct logic function. Compared with traditional CMOS counter, the average power consumption o

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25

Fadaei, Mohammadreza. "Designing ALU using GDI method." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 3 (2019): 151. http://dx.doi.org/10.11591/ijres.v8.i3.pp151-161.

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<p>As CMOS technology is continuously becoming smaller and smaller in nanoscale regimes, and circuit resistance to changes in the process for the design of the circuit is a major obstacle. Storage elements such as memory and flip-flops are particularly vulnerable to the change process. Power consumption is also another challenge in today's Digital IC Design. In modern processors, there are a large number of transistors, more than a billion transistors, which increases the temperature and the breakdown of its performance. Therefore, circuit design with low power consumption is a critical

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O'Connor, Ian, Junchen Liu, FrÉdÉric Gaffiot, et al. "CNTFET Modeling and Reconfigurable Logic-Circuit Design." IEEE Transactions on Circuits and Systems I: Regular Papers 54, no. 11 (2007): 2365–79. http://dx.doi.org/10.1109/tcsi.2007.907835.

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27

Thanh, Toi Le, Lac Truong Tri, and Hoang Trang. "Power Consumption Improvements in AES Decryption Based on Null Convention Logic." International Journal of Circuits, Systems and Signal Processing 15 (April 7, 2021): 254–64. http://dx.doi.org/10.46300/9106.2021.15.29.

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In this paper, we propose a new asynchronous method based on a Null Convention Logic (NCL) to improve power consumption for low power integrated circuits. The reason is because the NCL based designs do not use a clock, it eliminates the problems related to the clock and its power consumption reduces significantly. To show the advantages of the selected method, we propose two design models using the synchronous circuit design method, and the NCL based asynchronous circuit design method. To test these two design models conveniently, we also propose an extra automatic test model. In this study, t

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Huang, Mingqiang, Xingli Wang, Guangchao Zhao, Philippe Coquet, and Bengkang Tay. "Design and Implementation of Ternary Logic Integrated Circuits by Using Novel Two-Dimensional Materials." Applied Sciences 9, no. 20 (2019): 4212. http://dx.doi.org/10.3390/app9204212.

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With the approaching end of Moore’s Law (that the number of transistors in a dense integrated circuit doubles every two years), the logic data density in modern binary digital integrated circuits can hardly be further improved due to the physical limitation. In this aspect, ternary logic (0, 1, 2) is a promising substitute to binary (0, 1) because of its higher number of logic states. In this work, we carry out a systematical study on the emerging two-dimensional (2D) materials (MoS2 and Black Phosphorus)-based ternary logic from individual ternary logic devices to large scale ternary integrat

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Maity, Heranmoy, Arijit Kumar Barik, Arindam Biswas, Anup Kumar Bhattacharjee, and Anita Pal. "Design of Quantum Cost, Garbage Output and Delay Optimized BCD to Excess-3 and 2’s Complement Code Converter." Journal of Circuits, Systems and Computers 27, no. 12 (2018): 1850184. http://dx.doi.org/10.1142/s0218126618501840.

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In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2’s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2’s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verifi

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Chen, Shen Li, and C. K. Lee. "A Single-Chip Design for the Three-Phase BDCM System." Applied Mechanics and Materials 271-272 (December 2012): 742–46. http://dx.doi.org/10.4028/www.scientific.net/amm.271-272.742.

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In this work, we present a sensorless single-chip design for the three-phase brushless DC motors (BDCM) system, and which is implemented by a 0.35um CMOS process. A mixed-signal IC will be accomplished by the implementation of analog circuit and digital circuit in the same chip. Eventually, this chip system includes an analog circuit (Hall signal amplifier), a digital circuit (logic process block), and a frequency voltage converter (FVC) to complete the control & driving circuits. Experimental results are included to verify the proposed scheme.

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Et. al., Rajender Udutha ,. "Tunable Sub Threshold Logic Design Through Adaptive Feedback Equalization." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 2 (2021): 1540–45. http://dx.doi.org/10.17762/turcomat.v12i2.1430.

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An Efficient tunable subthreshold logic circuit planned by utilizing adaptive feedback equalization circuit. This circuit utilized in the Ladner Fischer adder. This circuit utilized in a successive advanced logic circuit to moderate the cycle variety impacts and lessen the prevailing spillage energy part in the subthreshold area. Feedback equalizer circuit changes the switching edge of its inverter. It depends on the output of the flip-flop in the past cycle to lessen the charging and releasing season of the flip-flop's information capacitance. Besides, the more modest info capacitance of the

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32

Sun, Jun-Wei, Xing-Tong Zhao, and Yan-Feng Wang. "Multi-Input Look-Up-Table Design Based on Nanometer Memristor." Journal of Nanoelectronics and Optoelectronics 15, no. 1 (2020): 113–21. http://dx.doi.org/10.1166/jno.2020.2721.

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The logic blocks of Field Programmable Gate Array (FPGA) basic unit are mainly composed of Look-Up-Tables (LUTs). The traditional LUTs use the static random access memory (SRAM), which causes FPGA reach the limitation in term of the density, speed, and configuration overhead. In this paper, a novel nanometer memristor-based LUT (NMLUT) is composed of memristors, MOS field effect transistors, decoders, resistors. A three-input NMLUT and a four-input NMLUT circuits are investigated. Moreover, an adder is used to verify the practicality of NMLUT circuit. The proposed NMLUT circuit can implement s

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SHAN, WEIWEI, YAN LIANG, and DONGMING JIN. "CMOS CIRCUIT DESIGN OF A TAKAGI-SUGENO FUZZY LOGIC CONTROLLER." Journal of Circuits, Systems and Computers 18, no. 04 (2009): 841–56. http://dx.doi.org/10.1142/s0218126609005009.

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This paper presents a low power CMOS analog integrated circuit of a Takagi–Sugeno fuzzy logic controller with voltage/voltage interface, small chip area, relatively high accuracy and medium speed, which is composed of several improved functional blocks. Z-shaped, Gaussian and S-shaped membership function circuits with compact structures are designed, performing well with low power, high speed and small areas. A current minimization circuit is provided with high accuracy and high speed. A follower-aggregation defuzzification block composed of several multipliers for center of gravity (COG) defu

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Saman, B., R. H. Gudlavalleti, R. Mays, J. Chandy, Evan Heller, and F. Jain. "3-Bit Analog-to-Digital Converter Using Multi-State Spatial Wave-Function Switched FETs." International Journal of High Speed Electronics and Systems 29, no. 01n04 (2020): 2040014. http://dx.doi.org/10.1142/s0129156420400145.

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Multi-valued logic using multi-state spatial wavefunction switched (SWS)-FETs offers overall reduction in size and power as compared to conventional FET based circuits. This paper presents the design of compact 3-bit Analog-to-Digital Converters (ADC) implemented with SWS-FETs. A novel multi-valued Threshold Inverter Quantization (TIQ) based voltage comparator using SWS FET transistors has been proposed. Unlike conventional FETs, SWS-FETs are comprised of two or more vertically stacked coupled quantum well or quantum dot channels, and the spatial location of carriers within these channels is u

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Shibata, T., and T. Ohmi. "Neuron MOS binary-logic integrated circuits. I. Design fundamentals and soft-hardware-logic circuit implementation." IEEE Transactions on Electron Devices 40, no. 3 (1993): 570–76. http://dx.doi.org/10.1109/16.199362.

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AL-RABADI, ANAS N. "QUANTUM LOGIC CIRCUIT DESIGN OF MANY-VALUED GALOIS REVERSIBLE EXPANSIONS AND FAST TRANSFORMS." Journal of Circuits, Systems and Computers 16, no. 05 (2007): 641–71. http://dx.doi.org/10.1142/s0218126607003939.

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Many-valued quantum circuit synthesis of many-valued reversible expansions and fast transforms is introduced in this paper. Since the reduction of power consumption is a major requirement for the circuit design in future technologies, such as in quantum computing, the main features of several future technologies will include reversibility. Consequently, the new quantum circuits can play an important task in the design of future circuits that consume minimal power. In addition, the new quantum circuit methodology is general and can be used to realize any multiple-valued function in the quantum

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Jain, Ankita, and Ashish Raghuwanshi. "A Design and Implementation of Reversible Logic Based Combinational Circuit with low Quantum Cost." International Journal of Trend in Scientific Research and Development Volume-1, Issue-6 (2017): 62–68. http://dx.doi.org/10.31142/ijtsrd2477.

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Prabhu, C. M. R., Tan Wee Xin Wilson, and T. Bhuvaneswari. "Low Power 11T Adder Comparator Design." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 1 (2020): 28. http://dx.doi.org/10.11591/ijres.v9.i1.pp28-33.

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Comparator is a basic arithmetic component in a digital system and adders are the basic block of processor unit, the performance of adder will improve the system performance. The proposed 11T adder comparator is consists of three main components, namely XOR, inverter, and MUX logic. The circuit is designed and implemented based on top-down approach with 11 transistors. The proposed cell can be used at higher temperature with minimal power loss. It also gives faster response for the carry output. The proposed comparator circuit shows 63.80% improvement in power consumption than other circuits.

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Shukla, Vandana, O. P. Singh, G. R. Mishra, and R. K. Tiwari. "A Novel Approach to Design 2-bit Binary Arithmetic Logic Unit (ALU) Circuit Using Optimized 8:1 Multiplexer with Reversible logic." Journal of Communications Software and Systems 11, no. 2 (2015): 104. http://dx.doi.org/10.24138/jcomss.v11i2.109.

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Reversible circuit designing is the area where researchers are focussing more and more for the generation of low loss digital system designs. Researchers are using the concept of Reversible Logic in many areas such as Nanotechnology, low loss computing, optical computing, low power CMOS design etc. Here we have proposed a novel design approach for a 2-bit binary Arithmetic Logic Unit (ALU) using optimized 8:1 multiplexer circuit with reversible logic concept [1]. This ALU circuit can perform complement, transfer, addition, subtraction, multiplication, OR, XOR, NAND functions on given values. T

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Upadhyay, Shipra, R. K. Nagaria, and R. A. Mishra. "Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic." VLSI Design 2013 (November 7, 2013): 1–9. http://dx.doi.org/10.1155/2013/726324.

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Efficiency of adiabatic logic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. The lesser will be these losses circuit will be more energy efficient. In this paper, a new approach is presented for minimizing power consumption in quasistatic energy recovery logic (QSERL) circuit which involves optimization by removing the nonadiabatic losses completely by replacing the diodes with MOSFETs whose gates are controlled by power clocks. Proposed circuit inherits the advantages of quasistatic ERL (QSERL) family but is with

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KANCHANA BHAASKARAN, V. S., and J. P. RAINA. "PRE-RESOLVE AND SENSE ADIABATIC LOGIC FOR 100 KHZ TO 500 MHZ FREQUENCY CLASSES." Journal of Circuits, Systems and Computers 21, no. 05 (2012): 1250045. http://dx.doi.org/10.1142/s0218126612500454.

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The novel pre-resolve and Sense Adiabatic Logic (PSAL) is a less complex quasi-adiabatic logic circuit usable for frequency range from 100 KHz to 500 MHz. It employs a large height pre-resolved nMOS structured tree and a differential sensing logic. The logic realizes superior energy efficiency through reduced silicon area requirement, low circuit latency, glitch-free output and less switching transients. Significant reduction in switched capacitance realizes enhanced speed performance. Furthermore, evaluation of more than one level of gate (or a complex gate) in each phase makes use of less nu

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Keote, Minal, and P. T. Karule. "Design and Implementation of Low Power Multiplier Using Proposed Two Phase Clocked Adiabatic Static CMOS Logic Circuit." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 6 (2018): 4959. http://dx.doi.org/10.11591/ijece.v8i6.pp4959-4971.

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<p class="Abstract">This paper presents a design and implementation of 2*2 array and 4*4 array multiplier using proposed Two Phase Clocked Adiabatic Static CMOS logic (2PASCL) circuit. The proposed 2PASCL circuit is based on adiabatic energy recovery principle which consumes less power. The proposed 2PASCL uses two sinusoidal power clocks which are 1800 phase shifted with each other. The measurement result of 2*2 array proposed 2PASCL multiplier gives 80.16 % and 97.67 %power reduction relative to reported 2PASCL and conventional CMOS logic and the measurement result of 4*4 array propose

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Zhou, Liang, Scott Smith, and Jia Di. "Radiation Hardened NULL Convention Logic Asynchronous Circuit Design." Journal of Low Power Electronics and Applications 5, no. 4 (2015): 216–33. http://dx.doi.org/10.3390/jlpea5040216.

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Jain, A. K., R. J. Bolton, and M. H. Abd-El-Barr. "CMOS multiple-valued logic design. I. Circuit implementation." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 40, no. 8 (1993): 503–14. http://dx.doi.org/10.1109/81.242320.

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Jelemenská, Katarína, Miroslav Siebert, Dominik Macko, and Pavel Čičák. "Logic circuit design verification support tool - Fit Board." Procedia - Social and Behavioral Sciences 28 (2011): 305–10. http://dx.doi.org/10.1016/j.sbspro.2011.11.058.

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Starzyk, Janusz A., and Haibo He. "A Novel Low-Power Logic Circuit Design Scheme." IEEE Transactions on Circuits and Systems II: Express Briefs 54, no. 2 (2007): 176–80. http://dx.doi.org/10.1109/tcsii.2006.883093.

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Takahashi, Ryuichi, and Takashi Nanya. "Logic circuit design for testability using orthonormal expansions." Systems and Computers in Japan 26, no. 11 (1995): 1–11. http://dx.doi.org/10.1002/scj.4690261101.

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Dhar, Tapobrata, Surajit Kumar Roy, and Chandan Giri. "Hardware Trojan Horse Detection through Improved Switching of Dormant Nets." ACM Journal on Emerging Technologies in Computing Systems 17, no. 3 (2021): 1–22. http://dx.doi.org/10.1145/3439951.

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Covert Hardware Trojan Horses (HTH) introduced by malicious attackers during the fabless manufacturing process of integrated circuits (IC) have the potential to cause malignant functions within the circuit. This article employs a Design-for-Security technique to detect any HTHs present in the circuit by inserting tri-state buffers (TSB) in the ICs that inject the internal nets with weighted logic values during the test phase. This increases the transitions in the logic values of the nets within the IC, thereby stimulating any inserted HTH circuits. The TSBs are efficiently inserted in the IC c

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THOMSEN, MICHAEL KIRKEDAL, and HOLGER BOCK AXELSEN. "PARALLELIZATION OF REVERSIBLE RIPPLE-CARRY ADDERS." Parallel Processing Letters 19, no. 02 (2009): 205–22. http://dx.doi.org/10.1142/s0129626409000171.

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The design of fast arithmetic logic circuits is an important research topic for reversible and quantum computing. A special challenge in this setting is the computation of standard arithmetical functions without the generation of garbage. Here, we present a novel parallelization scheme wherein m parallel k-bit reversible ripple-carry adders are combined to form a reversible mk-bit ripple-block carry adder with logic depth [Formula: see text] for a minimal logic depth [Formula: see text], thus improving on the mk-bit ripple-carry adder logic depth [Formula: see text]. The underlying mechanisms

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Gan, Kwang-Jow, Cher-Shiung Tsai, and Shih-Hao Liu. "Multiple-input logic circuit design using BiCMOS-based negative differential resistance circuits." Analog Integrated Circuits and Signal Processing 73, no. 1 (2011): 409–14. http://dx.doi.org/10.1007/s10470-011-9709-3.

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