Relevant bibliographies by topics / Logic circuits

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Logic circuits'

Author: Grafiati
Published: 4 June 2021
Last updated: 31 July 2024

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Journal articles on the topic "Logic circuits"

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Jin, Chen. "A review on multiple-valued logic circuits." Applied and Computational Engineering 43, no. 1 (February 26, 2024): 322–26. http://dx.doi.org/10.54254/2755-2721/43/20230857.

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Since the traditional binary logic has several disadvantages including inaccuracy, high complexity, and limited applications. Multiple-Valued Logic (MVL), which can store more information in one digit than binary logics, require less number of logic gates and take the third value in practical logic problems, is developed and introduced. More information stored per digit leads to higher computational efficiency. Less logic gates results in more spaces on the circuit board. Considering the third value means higher accuracy. In this research, some examples of different MVL circuit are designed to give a rough picture of current research in this domain. These designs are based on ternary and quaternary logics rather than binary logics. Besides, reliability evaluation through mathematical approach is presented in order to prove that the new design is more preferable. This can be carried out with mathematical analysis such as calculating a matrix that reflects its reliability, and simulating different designs to obtain certain values and comparing them with each other. Despite facing various challenges, including complicated physical implementation and difficulty to modulate the signals. This means that there is still potential of further research in this domain of logic circuits. This result in the conclusion that the MVL logic circuits will replace the conventional binary logic circuits in the future, and probably that decimal logic would be developed and no binary-to-decimal conversion unit will be required.
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Patel, Ambresh, and Ritesh Sadiwala. "Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 15, no. 01 (January 30, 2023): 91–95. http://dx.doi.org/10.18090/10.18090/samriddhi.v15i01.13.

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The demand for VLSI low voltage high-performance low power systems are increasing significantly. Today's deviceapplications necessitate a system that consumes little power and conserves performance. Recent battery-powered lowvoltagedevices optimize power and high-speed constraints. Aside from that, there is a design constraint with burst-modetype integrated circuits for small devices to scale down. Low voltage low power static CMOS logic integrated circuitsoperate at a slower rate and cannot be used in high performance circuits. As a result, dynamic CMOS logic is used inintegrated circuits because it requires fewer transistors, has lower parasitic capacitance, is faster, and enables pipelinedsystem architecture with glitch-free circuits. It has, however, increased power dissipation. Both types of CMOS circuits withlow power dissipation overcome their own shortcomings.This paper discusses dynamic CMOS logic circuits and their structures. Various logics are also discussed and on the basisof the results obtained, logic which is best suited for designing CMOS logic circuit will be found out. The logic on the basisof structure layout and design which gives best results for high-speed VLSI circuits, is found out.
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Bundalo, Dusanka, Zlatko Bundalo, and Branimir Ðordjevic. "Design of quaternary logic systems and circuits." Facta universitatis - series: Electronics and Energetics 18, no. 1 (2005): 45–56. http://dx.doi.org/10.2298/fuee0501045b.

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The principles and possibilities of design of fully quaternary multiple valued combinational logic systems and circuits are described and proposed in the paper. Different ways of design of fully quaternary combinational logic systems and circuits are considered and described first. Then algorithm for automated computerized design of such systems and circuits is considered and proposed. The algorithm gives possibility for synthesis and optimization of quaternary logic systems and circuits. It is applied on design of CMOS quaternary multiple valued logic systems and circuits. The algorithm includes the most important aspects of design of quaternary logic circuits: logic circuit scheme synthesis and logic circuit optimization. Methods for synthesis of quaternary CMOS combinational logic circuits are proposed and described. Also, method for optimization of CMOS quaternary logic circuits, according to operation conditions and needed characteristics, is proposed and described. Design procedure is realized by personal computer using PSPICE for circuit simulation. Computer PSPICE simulation results confirming described methods and conclusions are given in the paper.
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Bansal, Deepika, Brahmadeo Prasad Singh, and Ajay Kumar. "Stack Contention-alleviated Precharge Keeper for Pseudo Domino Logic." Bulletin of Electrical Engineering and Informatics 6, no. 2 (June 1, 2017): 122–32. http://dx.doi.org/10.11591/eei.v6i2.597.

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The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.
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Upadhyay, Shipra, R. A. Mishra, R. K. Nagaria, and S. P. Singh. "DFAL: Diode-Free Adiabatic Logic Circuits." ISRN Electronics 2013 (February 10, 2013): 1–12. http://dx.doi.org/10.1155/2013/673601.

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The manufacturing advances in semiconductor processing (continually reducing minimum feature size of transistors, increased complexity and ever increasing number of devices on a given IC) change the design challenges for circuit designers in CMOS technology. The important challenges are low power high speed computational devices. In this paper a novel low power adiabatic circuit topology is proposed. By removing the diode from the charging and discharging path, higher output amplitude is achieved and also the power dissipation of the diodes is eliminated. A mathematical expression has been developed to explain the energy dissipation in the proposed circuit. Performance of the proposed logic is analyzed and compared with CMOS and reported adiabatic logic styles. Also the layout of proposed inverter circuit has been drawn. Subsequently proposed topology-based various logic gates, combinational and sequential circuits and multiplier circuit are designed and simulated. The simulations were performed by VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In proposed inverter the energy efficiency has been improved to almost 60% up to 100 MHz in comparison to conventional CMOS circuits. The present research provides low power high speed results up to 100 MHz, and proposal has proven to be used in power aware high-performance VLSI circuitry.
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Kamde, Shilpa, Jitesh Shinde, Sanjay Badjate, and Pratik Hajare. "Comparative Analysis Domino Logic Based Techniques For VLSI Circuit." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 12, no. 8 (March 21, 2014): 3803–8. http://dx.doi.org/10.24297/ijct.v12i8.2998.

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Domino logic is a CMOS-based evolution of the dynamic logic techniques  based on either PMOS or NMOS transistors. Domino logic technique is widely used in modern digital VLSI circuit. Dynamic logic is twice as fast as static CMOS logic because it uses only N fast transistors. The Dynamic (Domino) logic circuit are often favored in high performance designs because of the high speed and low area advantage.Four different dynamic circuit techniques including Basic domino logic circuit are compared in this paper for low power consumption and speed of domino logic circuits. For digital circuit simulation used BSIM(Berkeley Short Channel IGFET ) Model because it control leakage current.
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Muneesa, Sk Haleem, Jakkala Yoga Deepika, Obulam Yogendra Lakshmi Prasanna, Gummadi Sumasree, and Shaik Thaslim. "Design of Reconfigurable Logic Block Based Sequential Circuits Using Look Up Table Logics." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 15, no. 1 (March 4, 2024): 195–204. http://dx.doi.org/10.61841/turcomat.v15i1.14612.

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Reconfigurable sequential circuits find applications in various digital systems, including communication networks, data processing units, embedded systems, and FPGA-based designs. Their ability to adapt and reconfigure their functionality onthe-fly allows them to accommodate dynamic requirements and optimize the use of hardware resources. Traditional implementations of sequential circuits involve static configurations, where the logic and functionality are fixed during synthesis. While these methods are straightforward to design and implement, they lack adaptability and cannot be modified without redesigning the entire circuit. The proposed method involves the utilization of a dedicated Reconfigurable Logic Block (RLB) within the sequential circuits, allowing for dynamic configuration changes without altering the overall circuit structure. The RLB can be programmed to provide different logic functions using look up tables, multiplexers, enabling the sequential circuit such as counters and shift registers to change its behaviour.
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Sun, Junwei, Qinfei Yang, and Yanfeng Wang. "Memristive Circuit Design of Five-Person Voter Based on Memristor Ratioed Logic." Journal of Nanoelectronics and Optoelectronics 15, no. 12 (December 1, 2020): 1482–93. http://dx.doi.org/10.1166/jno.2020.2895.

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Conventional CMOS-based logic circuits are approaching their limits when it comes to speed and energy consumption, so the development of new electronic components becomes critical. Memristor is a nano-structured special electronic device with the advantages of simple structure, low power consumption and easy integration. This invention supplys a new method for developing complex logic circuits. This article mainly presents the design of a five-person voter circuit. The OR/AND logic can be accomplished by varying the polarity of two parallel memristors. On the basis of the two logic circuits, adder and comparator are constructed. Further, based on the adder and comparator, a five-person voter is implemented. The correctness and rationality of the five-person voter based on MRL are confirmed via logistical analysis and simulation. Compared with the traditional logic circuits, the logic circuit designed in this paper has advantages in area cost. The realization of the five-person voter circuit further proves that the logic circuit based on memristor can be cascaded. The research results are expected to build more complex circuits, which may provide a reference for the design of other practical circuits.
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Raman, Karthik, and Andreas Wagner. "The evolvability of programmable hardware." Journal of The Royal Society Interface 8, no. 55 (June 9, 2010): 269–81. http://dx.doi.org/10.1098/rsif.2010.0212.

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In biological systems, individual phenotypes are typically adopted by multiple genotypes. Examples include protein structure phenotypes, where each structure can be adopted by a myriad individual amino acid sequence genotypes. These genotypes form vast connected ‘neutral networks’ in genotype space. The size of such neutral networks endows biological systems not only with robustness to genetic change, but also with the ability to evolve a vast number of novel phenotypes that occur near any one neutral network. Whether technological systems can be designed to have similar properties is poorly understood. Here we ask this question for a class of programmable electronic circuits that compute digital logic functions. The functional flexibility of such circuits is important in many applications, including applications of evolutionary principles to circuit design. The functions they compute are at the heart of all digital computation. We explore a vast space of 10 45 logic circuits (‘genotypes’) and 10 19 logic functions (‘phenotypes’). We demonstrate that circuits that compute the same logic function are connected in large neutral networks that span circuit space. Their robustness or fault-tolerance varies very widely. The vicinity of each neutral network contains circuits with a broad range of novel functions. Two circuits computing different functions can usually be converted into one another via few changes in their architecture. These observations show that properties important for the evolvability of biological systems exist in a commercially important class of electronic circuitry. They also point to generic ways to generate fault-tolerant, adaptable and evolvable electronic circuitry.
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Sun, Jun-Wei, Yu-Qi Tian, and Yan-Feng Wang. "Eight-Person Voter Implementation Based on Hewlett-Packard Memristor." Journal of Nanoelectronics and Optoelectronics 15, no. 3 (March 1, 2020): 404–14. http://dx.doi.org/10.1166/jno.2020.2728.

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The logic function based on memristor has been proved and can be applied to the future large scale integrated circuits. In this paper, we use logic circuit based on memristor to realize the function of eight-person voter. The basic logic circuit designed in this paper is consisted of two Hewlett-Packard memristors in series connection and an operational amplifier. Operational amplifiers are used to regulate the output voltages to meet the requirements of the input signals in the next stage circuits. The adder, binary comparator and multi-input logic gate are realized by using the designed logic circuit. Full adders, binary comparators and multi-input logic gates are combined into eight-person voter circuit. Theoretical analysis and spice simulation results verify the feasibility of the circuit under different cases. This method is expected to be applied to more complex voter logic circuits based on memristor.
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Dissertations / Theses on the topic "Logic circuits"

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Parameswaran, Nair Ravi Sankar. "Delay-insensitive ternary logic (DITL)." Diss., Rolla, Mo. : University of Missouri-Rolla, 2007. http://scholarsmine.umr.edu/thesis/pdf/Parameswaran_Nair_09007dcc803bc548.pdf.

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Thesis (M.S.)--University of Missouri--Rolla, 2007.
Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 27, 2007) Includes bibliographical references (p. 55-56).
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Silva, Augusto Neutzling. "Syhthesis of thereshold logic based circuits." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/119435.

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Circuitos baseados em portas lógicas de limiar (threshold logic gates – TLG) vem sendo estudados como uma alternativa promissora em relação ao tradicional estilo lógico CMOS, baseado no operadores AND e OR, na construção de circuitos integrados digitais. TLGs são capazes de implementar funções Booleanas mais complexas em uma única porta lógica. Diversos novos dispositivos, candidatos a substituir o transistor MOS, não se comportam como chaves lógicas e são intrinsicamente mais adequados à implementação de TLGs. Exemplos desses dispositivos são os memristores, spintronica, diodos de tunelamento ressonante (RTD), autômatos celulares quânticos (QCA) e dispositivos de tunelamento de elétron único (SET). Para o desenvolvimento de um fluxo de projeto de circuitos integrados baseados em lógica threshold, duas etapas são fundamentais: (1) identificar se uma dada função Booleana corresponde a uma função lógica threshold (TLF), isto é, pode ser implementada em um único TLG e computar os pesos desse TLG; (2) se uma função não é identificada como TLF, outro método de síntese lógica deve construir uma rede de TLGs otimizada que implemente a função. Este trabalho propõe métodos para atacar cada um desses dois problemas, e os resultados superam os métodos do estado-da-arte. O método proposto para realizar a identificação de TLFs é o primeiro método heurístico capaz de identificar todas as funções de cinco e seis variáveis, além de identificar mais funções que os demais métodos existentes quando o número de variáveis aumenta. O método de síntese de redes de TLGs é capaz de sintetizar circuitos reduzindo o número de portas TLG utilizadas, bem como a profundidade lógica e o número de interconexões. Essa redução é demonstrada através da síntese dos circuitos de avaliação da MCNC em comparação com os métodos já propostos na literatura. Tais resultados devem impactar diretamente na área e desempenho do circuito.
In this work, a novel method to synthesize digital integrated circuits (ICs) based on threshold logic gates (TLG) is proposed. Synthesis considering TLGs is quite relevant, since threshold logic has been revisited as a promising alternative to conventional CMOS IC design due to its suitability to emerging technologies, such as resonant tunneling diodes, memristors and spintronics devices. Identification and synthesis of threshold logic functions (TLF) are fundamental steps for the development of an IC design flow based on threshold logic. The first contribution is a heuristic algorithm to identify if a function can be implemented as a single TLG. Furthermore, if a function is not detected as a TLF, the method uses the functional composition approach to generate an optimized TLG network that implements the target function. The identification method is able to assign optimal variable weights and optimal threshold value to implement the function. It is the first heuristic algorithm that is not based on integer linear programming (ILP) that is able to identify all threshold functions with up to six variables. Moreover, it also identifies more functions than other related heuristic methods when the number of variables is more than six. Differently from ILP based approaches, the proposed algorithm is scalable. The average execution time is less than 1 ms per function. The second major contribution is the constructive process applied to generate optimized TLG networks taking into account multiple goals and design costs, like gate count, logic depth and number of interconnections. Experiments carried out over MCNC benchmark circuits show an average gate count reduction of 32%, reaching up to 54% of reduction in some cases, when compared to related approaches.
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Chu, Kan Man. "Cascode voltage switch logic circuits." Thesis, University of British Columbia, 1986. http://hdl.handle.net/2429/26283.

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Cascode voltage switch (CVS) logic is a CMOS circuit technique which has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation and logic flexibility. This thesis presents two new procedures for constructing differential CVS circuits to perform random logic functions. The first procedure makes use of a Karnaugh map and the second procedure is a tabular method based on the Quine-McCluskey approach. Both static and dynamic circuit techniques employing the CVS logic concept are discussed. Some wiring and layout methods based on theoretical graph models are presented to ensure the wirability of CVS circuits. An 8x8 NORA CVS multiplier has been designed using the 3μm CMOS technology of Northern Telecom. The chip measures 4mm by 4mm and simulations indicate that it can be run at a throughput rate of 50MHz.
Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
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Thulasi, Raman Sudheer Ram. "Logic Encryption of Sequential Circuits." University of Cincinnati / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1553251689992143.

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Ramirez, Ortiz Rolando. "Circuit design rules for mixed static and dynamic CMOS logic circuits." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp03/NQ37076.pdf.

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Ramirez, Ortiz Rolando Carleton University Dissertation Engineering Electronics. "Circuit design rules for mixed static and dynamics CMOS logic circuits." Ottawa, 1999.

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Sandireddy, Raja Kiran Kumar Reddy Agrawal Vishwani D. "Hierarchical fault collapsing for logic circuits." Auburn, Ala., 2005. http://repo.lib.auburn.edu/EtdRoot/2005/SPRING/Electrical_and_Computer_Engineering/Thesis/SANDIREDDY_RAJA-KIRAN-KUMAR_48.pdf.

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Bystrov, Alexandre. "Optimal testing of multilevel logic circuits." Thesis, Edinburgh Napier University, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.300327.

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Stone, Nicholas Jim. "Single electron memory and logic circuits." Thesis, University of Cambridge, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.621922.

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Blakely, Scott. "Probabilistic Analysis for Reliable Logic Circuits." PDXScholar, 2014. https://pdxscholar.library.pdx.edu/open_access_etds/1860.

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Continued aggressive scaling of electronic technology poses obstacles for maintaining circuit reliability. To this end, analysis of reliability is of increasing importance. Large scale number of inputs and gates or correlations of failures render such analysis computationally complex. This paper presents an accurate framework for reliability analysis of logic circuits, while inherently handling reconvergent fan-out without additional complexity. Combinational circuits are modeled stochastically as Discrete-Time Markov Chains, where propagation of node logic levels and error probability distributions through circuitry are used to determine error probabilities at nodes in the circuit. Model construction is scalable, as it is done so on a gate-by-gate basis. The stochastic nature of the model lends itself to allow various properties of the circuit to be formally analyzed by means of steady-state properties. Formal verifying the properties against the model can circumvent strenuous simulations while exhaustively checking all possible scenarios for given properties. Small combinational circuits are used to explain model construction, properties are presented for analysis of the system, more example circuits are demonstrated, and the accuracy of the method is verified against an existing simulation method.
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Books on the topic "Logic circuits"

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International Solid-State Circuits Conference (1995 San Francisco, Calif.). Logic and memory circuits. Edited by Gillingham Peter and Draper Don. New York: IEEE, 1995.

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J, Martin Alain, ed. Asynchronous pulse logic. Boston: Kluwer Academic Publishers, 2002.

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Lewin, Douglas. Design of logic systems. Berkshire, England: Van Nostrand Reinhold, 1985.

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Lewin, Douglas. Design of logic systems. London: Chapman & Hall, 1985.

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1930-, Pierce Bill, ed. Digital logic: Circuits and systems. Albany, N.Y: Delmar Publishers, 1988.

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Unger, Stephen H. The essence of logic circuits. 2nd ed. New York: Institute of Electrical and Electronic Engineers, 1997.

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1936-, Chen Wai-Kai, ed. Logic design. Boca Raton, Fla: CRC Press, 2003.

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Nicholls, Peter. Logic in action. 2nd ed. Southampton: NEMEC, 1988.

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L, Heiserman David. Logic IC master reference. San Diego: Academic Press, 1991.

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Corporation, National Semiconductor. LS/S/TTL logic databook. Santa Clara, Calif: The Corporation, 1989.

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Book chapters on the topic "Logic circuits"

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Nixon, Mark S. "Logic Circuits." In Introductory Digital Design, 49–84. London: Macmillan Education UK, 1995. http://dx.doi.org/10.1007/978-1-349-13508-0_3.

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Jayendran, Ariacutty, and Rajah Jayendran. "Logic circuits." In Englisch für Elektroniker, 129–37. Wiesbaden: Vieweg+Teubner Verlag, 1996. http://dx.doi.org/10.1007/978-3-322-84907-6_17.

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Tooley, Mike. "Logic Circuits." In Aircraft Digital Electronic and Computer Systems, 70–94. 3rd ed. London: Routledge, 2022. http://dx.doi.org/10.1201/9781003215516-5.

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Hsu, John Y. "Transistor Circuits." In Computer Logic, 62–90. New York, NY: Springer New York, 2002. http://dx.doi.org/10.1007/978-1-4613-0047-2_3.

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Tietze, Ulrich, Christoph Schenk, and Eberhard Gamm. "Logic Families." In Electronic Circuits, 611–34. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-78655-9_7.

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Tietze, Ulrich, Christoph Schenk, and Eberhard Gamm. "Sequential Logic Systems." In Electronic Circuits, 659–88. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-78655-9_9.

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Hsu, John Y. "Combinational Logic Circuits." In Computer Logic, 91–142. New York, NY: Springer New York, 2002. http://dx.doi.org/10.1007/978-1-4613-0047-2_4.

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Hsu, John Y. "Sequential Logic Circuits." In Computer Logic, 143–84. New York, NY: Springer New York, 2002. http://dx.doi.org/10.1007/978-1-4613-0047-2_5.

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Uyemura, John P. "Static Logic Circuits." In Circuit Design for CMOS VLSI, 115–66. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3620-8_4.

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Chalk, B. S. "Digital Logic Circuits." In Computer Organisation and Architecture, 8–22. London: Macmillan Education UK, 1996. http://dx.doi.org/10.1007/978-1-349-13871-5_2.

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Conference papers on the topic "Logic circuits"

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Brown, J. J., J. T. Gardner, and S. R. Forrest. "Optically powered monolithically integrated logic circuits." In Integrated Photonics Research. Washington, D.C.: Optica Publishing Group, 1991. http://dx.doi.org/10.1364/ipr.1991.tuc5.

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Optical powering of optoelectron integrated circuits (OEICs) significantly improves their performance in high density photonic systems as compared to conventional designs employing electrical powering of circuits.1 Here optical powering replaces the dc bias lines with integrated photovoltaic (PV) cells in each pixel. The PV cell is illuminated with an external light source (e.g. laser) and converts this optical power beam into electrical power which subsequently drives the circuitry within that pixel. The total absence of the parasitic capacitances and inductances in the optical beam reduces inter-pixel cross-talk as compared with conventional dc bias lines. This leads to significantly increased bandwidths in the optically powered case. In addition, optical powering reduces interconnection complexity associated with routing bias lines to each pixel in a high-density, two dimensional array. An optically powered interconnection system has already been demonstrated in hybrid form.2,3 In this present work, we discuss an integrated optoelectronic logic circuit in which the power and control are both provided using optical sources.
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Kane, Terence, Michael P. Tenney, John Bruley, and Steven Boettcher. "Defect Localization Technique for Logic Circuits in Sub 90nm SOI Microprocessors." In ISTFA 2006. ASM International, 2006. http://dx.doi.org/10.31399/asm.cp.istfa2006p0419.

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Abstract The emergence of multiple core, high speed microprocessors in sub 90nm node technologies present challenges for defect localization, especially in SRAM logic circuits involving Array Built In Self Test (ABIST). Voltage sensitive, temperature sensitive and frequency sensitive soft defects in these ABIST logic circuits can spell the difference between pass and failure, especially for Silicon on Insulator (SOI) designs. High density SRAM arrays with ever shrinking critical dimensions in multiple core, high speed microprocessor designs dictate an increased number of ABIST logic circuits of complex hierarchical design. Scan chain diagnostics to pinpoint the failing scan latch logic circuit following ABIST testing frequently results in ever greater uncertainty; increased number of suspect circuits related to the failure. A case study analysis successfully applied to pinpointing a voltage sensitive logic circuit defect in a 90nm SOI design is described here, followed by root cause TEM analysis.
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Afonso, Joao, and Jose Monteiro. "Analysis of short-circuit conditions in logic circuits." In 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2017. http://dx.doi.org/10.23919/date.2017.7927102.

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Baek, Gwanghyeon, John Keane, and Martin von Haartman. "Laser Logic State Imaging Using Transient Voltage Collapse Circuits." In ISTFA 2015. ASM International, 2015. http://dx.doi.org/10.31399/asm.cp.istfa2015p0021.

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Abstract A laser based logic state imaging (LLSI) by activating transient voltage collapse (TVC) circuits of SRAM blocks is demonstrated. In order to induce a voltage modulation on a power rail, significant numbers of TVC units are activated. The image quality of LLSI strongly depends on a number of activated TVC circuits. From this experiment, it is concluded that an additional circuit or experimental setup is not necessary for LLSI.
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Liu, Shutian, Chunfei Li, and Jie Wu. "Programmable optical binary threshold logic implementation via optoelectronic bistable circuit." In OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1989. http://dx.doi.org/10.1364/oam.1989.tht22.

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Integrated optoelectronic logic circuits are promising for use in optical computing. Much attention has been paid to demonstrate binary and multiple-valued optical logic implementation using optoelectronic circuits. In this paper we present what we believe to be the first demonstration of optical binary threshold logic using a modified optoelectronic PD LED bistable circuit (BILED).
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Pritika, K., and M. Vinodhini. "Logic Encryption of Combinational Circuits." In 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech). IEEE, 2019. http://dx.doi.org/10.1109/iementech48150.2019.8981198.

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Pham, Cong-Kha. "Simple Logic Threshold Conversion Circuits." In 2006 13th IEEE International Conference on Electronics, Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/icecs.2006.379777.

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K.S., Vasundara Patel, and K. S. Gurumurthy. "Quaternary CMOS Combinational Logic Circuits." In 2009 International Conference on Information and Multimedia Technology. IEEE, 2009. http://dx.doi.org/10.1109/icimt.2009.42.

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Shende, Vivek V., Stephen S. Bullock, and Igor L. Markov. "Synthesis of quantum logic circuits." In the 2005 conference. New York, New York, USA: ACM Press, 2005. http://dx.doi.org/10.1145/1120725.1120847.

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Bachtold, A. "Logic circuits with carbon nanotubes." In STRUCTURAL AND ELECTRONIC PROPERTIES OF MOLECULAR NANOSTRUCTURES: XVI International Winterschool on Electronic Properties of Novel Materials. AIP, 2002. http://dx.doi.org/10.1063/1.1514171.

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Reports on the topic "Logic circuits"

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Robinson, Jacob. Reconfigurable Optical Directed-Logic Circuits. Fort Belvoir, VA: Defense Technical Information Center, November 2015. http://dx.doi.org/10.21236/ad1003358.

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Blakely, Scott. Probabilistic Analysis for Reliable Logic Circuits. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.1859.

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Reddy, Sudhakar M. On Timing Faults in Digital Logic Circuits. Fort Belvoir, VA: Defense Technical Information Center, August 1993. http://dx.doi.org/10.21236/ada268714.

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Onneweer, Siep, Hans Kerkhoff, and Jon Butler. Structural Computer-Aided Design of Current-Mode CMOS Logic Circuits. Fort Belvoir, VA: Defense Technical Information Center, January 1988. http://dx.doi.org/10.21236/ada608071.

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Hargett, Terry W., G. Ronald Hadley, Darwin Keith Serkland, Ethan L. Blansett, Kent Martin Geib, Charles Thomas Sullivan, Gordon Arthur Keeler, et al. Final report on LDRD project :leaky-mode VCSELs for photonic logic circuits. Office of Scientific and Technical Information (OSTI), November 2005. http://dx.doi.org/10.2172/876352.

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Richter, Schachar E. Construction and Operation of Three-Dimensional Memory and Logic Molecular Devices and Circuits. Fort Belvoir, VA: Defense Technical Information Center, July 2013. http://dx.doi.org/10.21236/ada587368.

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Lala, P. K., and H. L. Martin. Application of Error Correcting Codes in Fault-Tolerant Logic Design for VLSI Circuits. Fort Belvoir, VA: Defense Technical Information Center, May 1990. http://dx.doi.org/10.21236/ada228840.

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Schueller, Kriss A., and Jon T. Butler. Complexity Analysis of the Cost-Table Approach to the Design of Multiple-Valued Logic Circuits. Fort Belvoir, VA: Defense Technical Information Center, October 1995. http://dx.doi.org/10.21236/ada605390.

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Weiss, Ron, and Liliana Wroblewska. An RNAi-enhanced Logic Circuit for Cancer Specific Detection and Destruction. Fort Belvoir, VA: Defense Technical Information Center, July 2010. http://dx.doi.org/10.21236/ada542442.

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Weiss, Ron, Liliana Wroblewska, and Zhen Xie. An RNAi-Enhanced Logic Circuit for Cancer Specific Detection and Destruction. Fort Belvoir, VA: Defense Technical Information Center, July 2012. http://dx.doi.org/10.21236/ada567986.

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