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1

Muroga, Saburo. Logic design and switching theory. R.E. Krieger, 1990.

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2

Taher, Abbasi, ed. Logic synthesis using Synopsys. 2nd ed. Kluwer Academic, 1997.

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3

Taher, Abbasi, ed. Logic synthesis using Synopsys. Kluwer Academic Publishers, 1995.

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4

Logic design for array-based circuits: A structured design methodology. Academic Press, 1992.

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5

Automatic logic synthesis techniques for digital systems. Macmillan Press, 1992.

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6

Automatic logic synthesis techniques for digital systems. Macmillan Press, 1992.

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7

Edwards, Martyn D. Automatic logic synthesis techniques for digital systems. McGraw-Hill, 1992.

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8

1964-, Ghosh Abhijit, and Keutzer Kurt William 1955-, eds. Logic synthesis. McGraw-Hill, 1994.

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9

Lala, Parag K. Practical digital logic design and testing. Prentice Hall, 1996.

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10

Khatri, Sunil P. Advanced techniques in logic synthesis, optimizations and applications. Springer, 2011.

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11

Monteiro, José. Computer-aided design techniques for low power sequential logic circuits. Kluwer Academic, 1997.

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12

Contemporary logic design. Benjamin/Cummings, 1994.

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13

Gaetano, Borriello, ed. Contemporary logic design. 2nd ed. Pearson Prentice Hall, 2005.

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14

Monteiro, José. Computer-aided design techniques for low power sequential logiccircuits. Kluwer, 1997.

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15

Wolfgang, Kunz. Reasoning in Boolean networks: Logic synthesis and verification using testing techniques. Kluwer Academic Publishers, 1997.

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16

Yu, Meng-Lin. Automatic random logic layout synthesis: A module generator approach. Dept. of Computer Science, University of Illinois at Urbana-Champaign, 1986.

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17

Ashar, Pranav. Sequential logic synthesis. Kluwer Academic Publishers, 1992.

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18

Krishnaswamy, Smita. Design, Analysis and Test of Logic Circuits Under Uncertainty. Springer Netherlands, 2013.

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19

F, Schulz Mark, ed. Logic design with Pascal: Computer-aided design techniques. Van Nostrand Reinhold, 1988.

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20

Healey, Steven Thomas. Abstract partitioning and routing of logic networks for custom module generation. Dept. of Computer Science, University of Illinois at Urbana-Champaign, 1987.

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21

G, Vranesic Zvonko, ed. Fundamentals of digital logic with Verilog design. McGraw-Hill, 2003.

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22

McMillan, Kenneth L. Symbolic model checking. Kluwer Academic, 1993.

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23

Fabio, Somenzi, ed. Logic synthesis and verification algorithms. Kluwer Academic Publishers, 1996.

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24

Hachtel, Gary D. Logic Synthesis and Verification Algorithms. Kluwer Academic Publishers, 2002.

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25

A, Riedel Susan, and Nilsson James William, eds. Introduction to PSpice manual using Orcad release 9.2 for Introductory circuits for electrical and computing engineering. Prentice Hall, 2002.

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26

1943-, Agrawal Vishwani D., and Bushnell Michael L. 1950-, eds. Neural models and algorithms for digital testing. Kluwer Academic Publishers, 1991.

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27

Workshop on Designing Correct Circuits (3rd 1996 Båstad, Sweden). Designing correct circuits: Proceedings of the 3rd Workshop on Designing Correct Circuits (DCC96), Båstad, Sweden, 2-4 September 1996. Springer, 1997.

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28

Workshop on Designing Correct Circuits (3rd 1996 Båstad, Sweden). Designing correct circuits: Proceedings of the 3rd Workshop on Designing Correct Circuits (DCC96), Båstad, Sweden, 2-4 September 1996. Springer, 1996.

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29

King, Brayton Robert, ed. Integrating functional and temporal domains in logic design: The false path problem and its implications. Kluwer Academic, 1991.

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30

International Workshop on Logic and Architecture Synthesis for Silicon Compilers (1988 Grenoble, France). Logic and architecture synthesis for silicon compilers: Proceedings of the International Workshop on Logic and Architecture Synthesis for Silicon Compilers held in Grenoble, France, 25-27 May, 1988. North-Holland, 1989.

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31

Iman, Sasan. Logic synthesis for low power VLSI designs. Kluwer Academic Publishers, 1998.

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32

Eschermann, B. Testfreundliche Synthese hochintegrierter Schaltungen. Springer, 1992.

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33

Principles of digital design. Prentice-Hall International, 1997.

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34

Minns, Anthony W. Artificial neural networks as subsymbolic process descriptors. A.A. Balkema, 1998.

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35

Gajski, Daniel D. Principles of digital design. Prentice Hall, 1997.

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36

Christian, Schuster. Simulation, analysis, and parameter extraction of electronic components and circuits using the finite difference time domain method. Hartung-Gorre, 2000.

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37

Higher order logic and hardware verification. Cambridge University Press, 1993.

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38

Airiau, Roland. Circuit synthesis with VHDL. Kluwer Academic Publishers, 1994.

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39

Advanced digital design with the Verilog HDL. Prentice Hall, 2003.

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40

Lee, Sunggu. Advanced digital logic design: Using Verilog, state machines, and synthesis for FPGAs. Thomson, 2006.

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41

Hill, Fredrick J. Computer aided logical design with emphasis on VLSI. 4th ed. Wiley, 1993.

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42

VHDL and AHDL digital system implementation. Prentice Hall PTR, 1998.

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43

Bhatnagar, Himanshu. Advanced ASIC chip synthesis: Using Synopsys Design Compiler, Physical Compiler, and PrimeTime. 2nd ed. Kluwer Academic Publishers, 2002.

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44

Bhatnagar, Himanshu. Advanced ASIC chip synthesis: Using Synopsys Design Compiler, Physical Compiler, and PrimeTime. 2nd ed. Kluwer Academic Publishers, 2002.

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45

Glick, Robert R. Six Sigma design of a wideband digital communication system. Addison-Wesley, 1992.

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46

G, Vranesic Zvonko, ed. Fundamentals of digital logic with VHDL design. 3rd ed. McGraw-Hill, 2008.

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47

G, Vranesic Zvonko, ed. Fundamentals of digital logic with VHDL design. 2nd ed. McGraw-Hill Companies, 2005.

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48

Gabrièle, Saucier, and McLellan Paul Michael, eds. Logic and architecture synthesis for silicon compilers: Proceedings of the International Workshop onLogic and Architecture Synthesis for Silicon Compilers held in Grenoble, France, 25-27 May, 1988. North-Holland, 1989.

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49

Reeder, John. Using MultiSIM: Troubleshooting DC/AC circuits. 4th ed. Thomson Delmar Learning, 2006.

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50

Using MultiSIM: Troubleshooting DC/AC circuits. 4th ed. Thomson Delmar Learning, 2006.

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