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Dissertations / Theses on the topic 'Logic circuits – Data processing'

Author: Grafiati

Published: 4 June 2021

Last updated: 5 February 2022

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1

Kusalik, Anthony Joseph. "Logic programming as a formalism for specification and implementation of computer systems." Thesis, University of British Columbia, 1988. http://hdl.handle.net/2429/28848.

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The expressive power of logic-programming languages allows utilization of conventional constructs in development of computer systems based on logic programming. However, logic-programming languages have many novel features and capabilities. This thesis investigates how advantage can be taken of these features in the development of a logic-based computer system. It demonstrates that innovative approaches to software, hardware, and computer system design and implementation are feasible in a logic-programming context and often preferable to adaptation of conventional ones. The investigation ce

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2

Roumeliotis, Emmanuel. "Multi-processor logic simulation at the chip level." Diss., Virginia Polytechnic Institute and State University, 1986. http://hdl.handle.net/10919/71180.

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This dissertation presents the design and development of a multi-processor logic simulator. After an introduction to parallel processing, the concept of distributed simulation is described as well as the possibility of deadlock in a distributed system. It is proven that the proposed system does not deadlock. Next, the modeling techniques are discussed along with the timing mechanisms used for logic simulation. A new approach, namely process oriented simulation is studied in depth. It is shown that modeling for this kind of simulation is more efficient regarding modeling ease, computer memory a

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3

Wist, Dominic. "Attacking complexity in logic synthesis of asynchronous circuits." Phd thesis, Universität Potsdam, 2011. http://opus.kobv.de/ubp/volltexte/2012/5970/.

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Most of the microelectronic circuits fabricated today are synchronous, i.e. they are driven by one or several clock signals. Synchronous circuit design faces several fundamental challenges such as high-speed clock distribution, integration of multiple cores operating at different clock rates, reduction of power consumption and dealing with voltage, temperature, manufacturing and runtime variations. Asynchronous or clockless design plays a key role in alleviating these challenges, however the design and test of asynchronous circuits is much more difficult in comparison to their synchronous coun

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4

Rahman, Md Raqibur. "Online testing in ternary reversible logic." Thesis, Lethbridge, Alta. : University of Lethbridge, c2011, 2011. http://hdl.handle.net/10133/3208.

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In recent years ternary reversible logic has caught the attention of researchers because of its enormous potential in different fields, in particular quantum computing. It is desirable that any future reversible technology should be fault tolerant and have low power consumption; hence developing testing techniques in this area is of great importance. In this work we propose a design for an online testable ternary reversible circuit. The proposed design can implement almost all of the ternary logic operations and is also capable of testing the reversible ternary network in real time (online). T

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5

Del, Duce A. "Quantum Logic circuits for solid-state quantum information processing." Thesis, University College London (University of London), 2010. http://discovery.ucl.ac.uk/20166/.

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This thesis describes research on the design of quantum logic circuits suitable for the experimental demonstration of a three-qubit quantum computation prototype. The design is based on a proposal for optically controlled, solid-state quantum logic gates. In this proposal, typically referred to as SFG model, the qubits are stored in the electron spin of donors in a solid-state substrate while the interactions between them are mediated through the optical excitation of control particles placed in their proximity. After a brief introduction to the area of quantum information processing, the basi

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6

Rappaport, David 1955. "The complexity of computing simple circuits in the plane /." Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=75339.

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As far back as Euclid's ruler and compass constructions, computation and geometry have been domains for the exploration and development of fundamental mathematical concepts and ideas. The invention of computers has spurred new research in computation, and now with a variety of applications couched in the fundamentals of Euclidean geometry, the study of geometric algorithms has again become a popular mathematical pursuit.<br>In this thesis, the computational aspects of a fundamental problem in Euclidean geometry is examined. Given a set of line segments in the Euclidean plane, one is asked to c

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7

Goebel, Randy. "A logic data model for the machine representation of knowledge." Thesis, University of British Columbia, 1985. http://hdl.handle.net/2429/25799.

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DLOG is a logic-based data model developed to show how logic-programming can combine contributions of Data Base Management (DBM) and Artificial Intelligence (AI). The DLOG specification includes a language syntax, a proof (or query evaluation) procedure, a description of the language's semantics, and a specification of the relationships between assertions, queries, and application databases. DLOG's data description language is the Horn clause subset of first order logic [Kowalski79, Kowalski81], augmented with descriptive terms and non-Horn integrity constraints. The descriptive terms are mot

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8

Ahmed, Abdulbasit. "Online network intrusion detection system using temporal logic and stream data processing." Thesis, University of Liverpool, 2013. http://livrepository.liverpool.ac.uk/12153/.

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These days, the world is becoming more interconnected, and the Internet has dominated the ways to communicate or to do business. Network security measures must be taken to protect the organization environment. Among these security measures are the intrusion detection systems. These systems aim to detect the actions that attempt to compromise the confidentiality, availability, and integrity of a resource by monitoring the events occurring in computer systems and/or networks. The increasing amounts of data that are transmitted at higher and higher speed networks created a challenging problem for

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9

Li, Ying-chi, and 李應賜. "Accelerated circuit simulation via Faber series and hierarchical matrix techniques." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2013. http://hub.hku.hk/bib/B50900092.

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This dissertation presents two circuit simulation techniques to accelerate the simulation time for time-domain transient circuit simulation and circuit thermal analysis. Matrix exponential method is one of the state-of-the-art methods for millionth-order time-domain circuit simulations due to its explicit nature and global stability. The matrix exponential is commonly computed by Krylov subspace methods, which become inefficient when the circuit is stiff, namely when the time constants of the circuit differ by several orders. The truncated Faber series is suitable for accurate evaluation of t

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10

Xia, Bing 1972 Nov 7. "A direct temporal domain approach for ultrafast optical signal processing and its implementation using planar lightwave circuits /." Thesis, McGill University, 2006. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=103007.

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Ultrafast optical signal processing, which shares the same fundamental principles of electrical signal processing, can realize numerous important functionalities required in both academic research and industry. Due to the extremely fast processing speed, all-optical signal processing and pulse shaping have been widely used in ultrafast telecommunication networks, photonically-assisted RFlmicro-meter waveform generation, microscopy, biophotonics, and studies on transient and nonlinear properties of atoms and molecules. In this thesis, we investigate two types of optical spectrally-periodic (SP)

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11

Chaudhari, Gunavant Dinkar. "Simulation and emulation of massively parallel processor for solving constraint satisfaction problems based on oracles." PDXScholar, 2011. https://pdxscholar.library.pdx.edu/open_access_etds/11.

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Most part of my thesis is devoted to efficient automated logic synthesis of oracle processors. These Oracle Processors are of interest to several modern technologies, including Scheduling and Allocation, Image Processing and Robot Vision, Computer Aided Design, Games and Puzzles, and Cellular Automata, but so far the most important practical application is to build logic circuits to solve various practical Constraint Satisfaction Problems in Intelligent Robotics. For instance, robot path planning can be reduced to Satisfiability. In short, an oracle is a circuit that has some proposition of so

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12

Meng, Lingling, and 孟玲玲. "Computational electromagnetics methods for IC modeling." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2013. http://hdl.handle.net/10722/195993.

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Two kinds of computational electromagnetics (CEM) methodology are discussed for the challenges in integrated circuit (IC) and printed circuit board (PCB) design. One is an extension of Cagniard-de Hoop method that provides analytic time-domain expressions for the field constituents, making up some drawbacks of numerical techniques that would lose power in super-high frequency simulation or extreme fine structure. A modeling of line-source excited by electromagnetic pulse is analyzed for a thin sheet with high-contrast dielectric and conductive properties. The response of reflection and transmi

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13

Hanson, Craig Demorest 1956. "Demonstration of capabilities of gallium arsenide etalons for practical optical logic." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277204.

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All-optical logic gates made from GaAs etalons were studied to see if they may be useful for optical computing. We have demonstrated that GaAs etalons may produce a change in output optical signal four times larger than the change in the input signal, and that the contrast of the output signal may be as high as 10 to 1. We have cascaded two GaAs etalons, i.e. the output change in the first causes the second one to switch. We have combined two signal beams and a biasing beam onto a GaAs etalon using polarized beams for a fan-in investigation, and have demonstrated that this setup may be used as

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14

馮潤開 and Yun-hoi Fung. "Linguistic fuzzy-logic control of autonomous vehicles." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1998. http://hub.hku.hk/bib/B29812690.

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15

Bartlett, Viv A. "Exploiting data dependencies in low power asynchronous VLSI signal processors." Thesis, University of Westminster, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.252037.

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16

Eskenazi, Cem. "An automated visual inspection system for bare hybrid boards /." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63302.

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17

Herre, Heinrich, and Axel Hummel. "A paraconsistent semantics for generalized logic programs." Universität Potsdam, 2010. http://opus.kobv.de/ubp/volltexte/2010/4149/.

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We propose a paraconsistent declarative semantics of possibly inconsistent generalized logic programs which allows for arbitrary formulas in the body and in the head of a rule (i.e. does not depend on the presence of any specific connective, such as negation(-as-failure), nor on any specific syntax of rules). For consistent generalized logic programs this semantics coincides with the stable generated models introduced in [HW97], and for normal logic programs it yields the stable models in the sense of [GL88].

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18

Herre, Heinrich, and Axel Hummel. "Stationary generated models of generalized logic programs." Universität Potsdam, 2010. http://opus.kobv.de/ubp/volltexte/2010/4150/.

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The interest in extensions of the logic programming paradigm beyond the class of normal logic programs is motivated by the need of an adequate representation and processing of knowledge. One of the most difficult problems in this area is to find an adequate declarative semantics for logic programs. In the present paper a general preference criterion is proposed that selects the ‘intended’ partial models of generalized logic programs which is a conservative extension of the stationary semantics for normal logic programs of [Prz91]. The presented preference criterion defines a partial model of a

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19

Taber, Caleb N. "Conversion of Digital Circuits Labs." Digital Commons @ East Tennessee State University, 2016. https://dc.etsu.edu/honors/395.

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The engineering technology department at ETSU currently lacks a modern method to teach digital circuits. The aim of this thesis is to convert our current digital circuits labs to equivalent labs suited to run on the Basys 3. The Basys has several advantages over the aging NI Elvis boards (and now just breadboards) currently in use. The first advantage is that the Basys gives students a taste of FPGA programming without being overwhelmingly; like the systems currently in place for the digital signal processing class. The Basys is also a more modern system; our current integrated circuit and bre

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20

Bharath, Karthik. "The logic of information flow a graded approach /." Diss., Online access via UMI:, 2008.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2008.<br>Includes bibliographical references.

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21

Dongier, François. "ND, a rule-based implementation of natural deduction : design of the theorem-prover and tutoring system." Thesis, McGill University, 1988. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63952.

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22

Zhou, Lixin. "Testability Design and Testability Analysis of a Cube Calculus Machine." PDXScholar, 1995. https://pdxscholar.library.pdx.edu/open_access_etds/4911.

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Cube Calculus is an algebraic model popular used to process and minimize Boolean functions. Cube Calculus operations are widely used in logic optimization, logic synthesis, computer image processing and recognition, machine learning, and other newly developing applications which require massive logic operations. Cube calculus operations can be implemented on conventional general-purpose computers by using the appropriate "model" and software which manipulates this model. The price that we pay for this software based approach is severe speed degradation which has made the implementation of seve

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23

Mirchandani, Chandru, David Fisher, and Parminder Ghuman. "Cost Beneficial Solution for High Rate Data Processing." International Foundation for Telemetering, 1999. http://hdl.handle.net/10150/606836.

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International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada<br>GSFC in keeping with the tenets of NASA has been aggressively investigating new technologies for spacecraft and ground communications and processing. The application of these technologies, together with standardized telemetry formats, make it possible to build systems that provide high-performance at low cost in a short development cycle. The High Rate Telemetry Acquisition System (HRTAS) Prototype is one such effort that has validated Goddard's push towards

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24

Eben-Chaime, Moshe. "The physical design of printed circuit boards : a mathematical programming approach." Diss., Georgia Institute of Technology, 1989. http://hdl.handle.net/1853/25505.

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25

Jin, Ruxiang. "Nonlinear etalons and nonlinear waveguides as decision-making elements in photonic switching." Diss., The University of Arizona, 1989. http://hdl.handle.net/10150/184807.

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This dissertation describes our recent results in the study of various types of photonic switches. Special attention is given to the devices with Fabry-Perot etalon or planar waveguide structures based on dispersive optical nonlinearities. Basic optical logic functions, such as digital pattern recognition, symbolic substitution, and all-optical compare-and-exchange operation are demonstrated using ZnS and ZnSe nonlinear interference filters. Differential gain, cascading, and optical latching circuits are demonstrated using GaAs/AlGaAs multiple-quantum-well nonlinear etalons that are compatible

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26

Mortensen, Clifton H. "A Computational Fluid Dynamics Feature Extraction Method Using Subjective Logic." BYU ScholarsArchive, 2010. https://scholarsarchive.byu.edu/etd/2208.

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Computational fluid dynamics simulations are advancing to correctly simulate highly complex fluid flow problems that can require weeks of computation on expensive high performance clusters. These simulations can generate terabytes of data and pose a severe challenge to a researcher analyzing the data. Presented in this document is a general method to extract computational fluid dynamics flow features concurrent with a simulation and as a post-processing step to drastically reduce researcher post-processing time. This general method uses software agents governed by subjective logic to make deci

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27

Wilson, Jeffrey. "Analysis of power requirements inside of NMOS integrated circuits." Full text open access at:, 1986. http://content.ohsu.edu/u?/etd,134.

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28

Hirani, Neal S. "Scheduling parallel batch processing machines to minimize makespan using genetic algorithms." Diss., Online access via UMI:, 2006.

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29

Ismailoglu, Ayse Neslin. "Asynchronous Design Of Systolic Array Architectures In Cmos." Phd thesis, METU, 2008. http://etd.lib.metu.edu.tr/upload/12609443/index.pdf.

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In this study, delay-insensitive asynchronous circuit design style has been adopted to systolic array architectures to exploit the benefits of both techniques for improved throughput. A delay-insensitivity verification analysis method employing symbolic delays is proposed for bit-level pipelined asynchronous circuits. The proposed verification method allows datadependent early output evaluation to co-exist with robust delay-insensitive circuit behavior in pipelined architectures such as systolic arrays. Regardless of the length of the pipeline, delay-insensitivity verification of a systolic ar

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30

Linck, Barbara. "Test items for and misconceptions of competences in the domain of logic programming." Universität Potsdam, 2013. http://opus.kobv.de/ubp/volltexte/2013/6446/.

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Development of competence-oriented curricula is still an important theme in informatics education. Unfortunately informatics curricula, which include the domain of logic programming, are still input-orientated or lack detailed competence descriptions. Therefore, the development of competence model and of learning outcomes' descriptions is essential for the learning process in this domain. A prior research developed both. The next research step is to formulate test items to measure the described learning outcomes. This article describes this procedure and exemplifies test items. It also relates

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31

Anderson, Christopher R. "Evaluation of gigabit links for use in HEP trigger processing." Thesis, University of Liverpool, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.367118.

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32

Măndoiu, Ion I. "Approximation algorithms for VLSI routing." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/9128.

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33

Ling, Yong-Long Calvin. "Hierarchical multiprocessor architecture design in VLSI for real-time robotic control applications /." The Ohio State University, 1986. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487322984317077.

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34

Petta, Angelo Carleton University Dissertation Engineering Electrical. "Design and implementation of the analog signal processing circuits for a single chip mixed analog/digital mobile radio baseband data demodulator." Ottawa, 1990.

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35

Chidambar, Munavalli Sainath. "Structural Data Acquisition Using Sensor Network." FIU Digital Commons, 2013. http://digitalcommons.fiu.edu/etd/879.

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The development cost of any civil infrastructure is very high; during its life span, the civil structure undergoes a lot of physical loads and environmental effects which damage the structure. Failing to identify this damage at an early stage may result in severe property loss and may become a potential threat to people and the environment. Thus, there is a need to develop effective damage detection techniques to ensure the safety and integrity of the structure. One of the Structural Health Monitoring methods to evaluate a structure is by using statistical analysis. In this study, a civil stru

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36

Teske, Alexander. "Automated Risk Management Framework with Application to Big Maritime Data." Thesis, Université d'Ottawa / University of Ottawa, 2018. http://hdl.handle.net/10393/38567.

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Risk management is an essential tool for ensuring the safety and timeliness of maritime operations and transportation. Some of the many risk factors that can compromise the smooth operation of maritime activities include harsh weather and pirate activity. However, identifying and quantifying the extent of these risk factors for a particular vessel is not a trivial process. One challenge is that processing the vast amounts of automatic identification system (AIS) messages generated by the ships requires significant computational resources. Another is that the risk management process partially r

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37

Chai, Sek Meng. "Real time image processing on parallel arrays for gigascale integration." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/15513.

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38

Hawkins, Kevin Michael. "Development of an automated anesthesia system for the stabilization of physiological parameters in rodents." Link to electronic thesis, 2003. http://www.wpi.edu/Pubs/ETD/Available/etd-0424103-105500/.

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39

Deo, Nitin. "Completion and validation of the design of a reconfigurable image processing board." Thesis, Virginia Polytechnic Institute and State University, 1985. http://hdl.handle.net/10919/53064.

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Starting in September 1984, the Telesign project is an extensive and complex project proposed and undertaken by Dr. Nadler at Virginia Tech. The emphasis of this project is to enable the members of the deaf community to communicate visually using sign language or lip reading over the telephone network. The Image Processing Board (IPB) is the 'Brain' of the whole system. The IPB processes a given frame of an image to transmit only selected data. It uses the pseudo-laplacian operator, invented by Dr. Nadler, for edge detection. According to a recent survey of various edge detection algorithms

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40

Geske, Ulrich, and Armin Wolf. "Preface." Universität Potsdam, 2010. http://opus.kobv.de/ubp/volltexte/2010/4140/.

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The workshops on (constraint) logic programming (WLP) are the annual meeting of the Society of Logic Programming (GLP e.V.) and bring together researchers interested in logic programming, constraint programming, and related areas like databases, artificial intelligence and operations research. In this decade, previous workshops took place in Dresden (2008), Würzburg (2007), Vienna (2006), Ulm (2005), Potsdam (2004), Dresden (2002), Kiel (2001), and Würzburg (2000). Contributions to workshops deal with all theoretical, experimental, and application aspects of constraint programming (CP) and log

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41

Kim, Kwanghyun. "An interactive design rule checker for integrated circuit layout." Thesis, Virginia Polytechnic Institute and State University, 1985. http://hdl.handle.net/10919/50034.

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An implementation of an interactive design rule checker is described in this thesis. Corner-based design rule checking algorithm is used for the implementation. Due to the locality of checking mechanism of the corner-based algorithm, it is suitable for hierarchical and interactive local design rule checking. It also allows the various design rules to be specified very easily. Interactive operations are devised so that the design rule checker can be invoked from inside the layout editor. All the information about the violation, such as position, type of violation, and symbol definition name ar

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42

Ali, Shirook M. Nikolova Natalia K. "Efficient sensitivity analysis and optimization with full-wave EM solvers." *McMaster only, 2004.

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43

Shelor, Charles F. "Dataflow Processing in Memory Achieves Significant Energy Efficiency." Thesis, University of North Texas, 2018. https://digital.library.unt.edu/ark:/67531/metadc1248478/.

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The large difference between processor CPU cycle time and memory access time, often referred to as the memory wall, severely limits the performance of streaming applications. Some data centers have shown servers being idle three out of four clocks. High performance instruction sequenced systems are not energy efficient. The execute stage of even simple pipeline processors only use 9% of the pipeline's total energy. A hybrid dataflow system within a memory module is shown to have 7.2 times the performance with 368 times better energy efficiency than an Intel Xeon server processor on the ana

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44

Ivanov, André. "Dynamic testibility measures and their use in ATPG." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63324.

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45

Jett, David B. "Selection of flip-flops for partial scan paths by use of a statistical testability measure." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-12302008-063234/.

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Kim, Kwanghyun. "An expert system for self-testable hardware design." Diss., Virginia Polytechnic Institute and State University, 1989. http://hdl.handle.net/10919/54216.

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BIDES (A BIST Design Expert System) is an expert system for incorporating BIST into a digital circuit described with VHDL. BIDES modifies a circuit to produce a self-testable circuit by inserting BIST hardware such as pseudorandom pattern generators and signature analysis registers. In inserting BIST hardware, BIDES not only makes a circuit self-testable, but also incorporates the appropriate type of BIST structure so that a set of user-specified constraints on hardware overhead and testing time can be satisfied. This flexibility comes from the formulation of the BIST design problem as a searc

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47

Zhuo, Yue. "Timing and Congestion Driven Algorithms for FPGA Placement." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5423/.

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Placement is one of the most important steps in physical design for VLSI circuits. For field programmable gate arrays (FPGAs), the placement step determines the location of each logic block. I present novel timing and congestion driven placement algorithms for FPGAs with minimal runtime overhead. By predicting the post-routing timing-critical edges and estimating congestion accurately, this algorithm is able to simultaneously reduce the critical path delay and the minimum number of routing tracks. The core of the algorithm consists of a criticality-history record of connection edges and a cong

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48

Kang, Hoyoung. "New approaches in optical lithography technology for subwavelength resolution /." Link to online version, 2005. https://ritdml.rit.edu/dspace/handle/1850/1119.

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49

Morozov, Alexei. "Optimierung von Fehlererkennungsschaltungen auf der Grundlage von komplementären Ergänzungen für 1-aus-3 und Berger Codes." Phd thesis, Universität Potsdam, 2005. http://opus.kobv.de/ubp/volltexte/2005/536/.

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Die Dissertation stellt eine neue Herangehensweise an die Lösung der Aufgabe der funktionalen Diagnostik digitaler Systeme vor. In dieser Arbeit wird eine neue Methode für die Fehlererkennung vorgeschlagen, basierend auf der Logischen Ergänzung und der Verwendung von Berger-Codes und dem 1-aus-3 Code. Die neue Fehlererkennungsmethode der Logischen Ergänzung gestattet einen hohen Optimierungsgrad der benötigten Realisationsfläche der konstruierten Fehlererkennungsschaltungen. Außerdem ist eins der wichtigen in dieser Dissertation gelösten Probleme die Synthese vollständig selbstprüfender Schalt

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50

Dickinson, Alex. "Complexity management and modelling of VLSI systems." Title page, contents and abstract only, 1988. http://web4.library.adelaide.edu.au/theses/09PH/09phd553.pdf.

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