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Journal articles on the topic 'Logic circuits – Data processing'

Author: Grafiati

Published: 4 June 2021

Last updated: 5 February 2022

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1

Khitun, Alexander. "Multi-frequency magnonic logic circuits for parallel data processing." Journal of Applied Physics 111, no. 5 (2012): 054307. http://dx.doi.org/10.1063/1.3689011.

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Kumagai, Masaaki, and Takashi Emura. "Development of a Universal Interface Board and its Application to Robot Controllers and Signal Processors." Journal of Robotics and Mechatronics 16, no. 2 (2004): 200–207. http://dx.doi.org/10.20965/jrm.2004.p0200.

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Multipurpose digital interface boards for the PCI bus were designed for robot controllers. They used a programmable logic device reconfigured for internal circuits. The user plugs the board in, then downloads circuit data to obtain various interfaces. Optional modules such as analog front ends and support software also were developed. The board enables rapid prototyping and flexible use of high-speed digital circuits. Three applications of the board — robot interfaces of DC servomotors for a walking robot, high-speed digital signal processing for a motion capture system, and pipelined image pr

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Shi, Weiwei, Jinyong Zhang, Zhiguo Zhang, Lizhi Hu, and Yongqian Su. "An introduction and review on innovative silicon implementations of implantable/scalp EEG chips for data acquisition, seizure/behavior detection, and brain stimulation." Brain Science Advances 6, no. 3 (2020): 242–54. http://dx.doi.org/10.26599/bsa.2020.9050024.

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Technological advances in the semiconductor industry and the increasing demand and development of wearable medical systems have enabled the development of dedicated chips for complex electroencephalogram (EEG) signal processing with smart functions and artificial intelligence‐based detections/classifications. Around 10 million transistors are integrated into a 1 mm2 silicon wafer surface in the dedicated chip, making wearable EEG systems a powerful dedicated processor instead of a wireless raw data transceiver. The reduction of amplifiers and analog‐digital converters on the silicon surface ma

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Devnath, Bappy Chandra, and Satyendra N. Biswas. "Low Power Full Adder Design Using PTM Transistor Model." Carpathian Journal of Electronic and Computer Engineering 12, no. 2 (2019): 15–20. http://dx.doi.org/10.2478/cjece-2019-0011.

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Abstract At present the processing power of the digital electronic chip is enormous and that has been possible because of the continuous improvement of the design methodology and fabrication technology. So, the data processing capability of the chip is increased significantly. Data processing in the electronic chip means the arithmetic operation on that data. For that reason, ALU is present in any processor. Full adder is one of the critical components of arithmetic unit. Improvement of the full adder is necessary for improving the computational performance of a chip. In order to design an eff

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Shibata, Tadashi, and Tadahiro Ohmi. "Implementing Intelligence in Silicon Integrated Circuits Using Neuron-Like High-Functionality Transistors." Journal of Robotics and Mechatronics 8, no. 6 (1996): 508–15. http://dx.doi.org/10.20965/jrm.1996.p0508.

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The primary objective of this article is not to present integrated circuit implementation of neural networks in the sense that neurophysiological models are constructed in electronic circuits, but to describe new-architecture intelligent electronic circuits built using a neuron-like high-functionality transistor as a basic circuit element. This has greatly reduced the VLSI hardware/software burden in carrying out intelligent data processing and would find promising applications in robotics. The transistor is a multiple-input-gate thresholding device called a neuron MOSFET (neuMOS or νMOS) due

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Ilijin, Sandra, and Predrag Petkovic. "Implementation of control logic in the scoreboard of tennis." Serbian Journal of Electrical Engineering 12, no. 2 (2015): 219–36. http://dx.doi.org/10.2298/sjee1502219i.

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This paper presents one original solution of control logic for scoreboard in tennis match. The main goal is to simplify the process of recording points. Instead of using six buttons the chair umpire (referee) will use only two control buttons or a joystick to assign a point to a player. The proposed system takes care of all other data processing. The system is designed in Application Specific Integrated Circuits (ASIC) and Standard Application Specific Integrated Circuits (SASIC) technology to demonstrate similarities and differences between two design technologies. Finally it is realized on F

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CHATTOPADHYAY, TANAY, GOUTAM KUMAR MAITY, and JITENDRA NATH ROY. "DESIGNING OF ALL-OPTICAL TRI-STATE LOGIC SYSTEM WITH THE HELP OF OPTICAL NONLINEAR MATERIAL." Journal of Nonlinear Optical Physics & Materials 17, no. 03 (2008): 315–28. http://dx.doi.org/10.1142/s0218863508004159.

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Nonlinear optics has been of increased interest for all-optical signal, data and image processing in high speed photonic networks. The application of multi-valued (nonbinary) digital signals can provide considerable relief in transmission, storage and processing of a large amount of information in digital signal processing. Here, we propose the design of an all-optical system for some basic tri-state logic operations (trinary OR, trinary AND, trinary XOR, Inverter, Truth detector, False detector) which exploits the polarization properties of light. Nonlinear material based optical switch can p

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Bogdanov, D. R., and O. V. Darintsev. "Multiprocessor systems based on FPGA for receiving and processing data from the position sensors of the manipulator elements with controlled bending." Proceedings of the Mavlyutov Institute of Mechanics 11, no. 1 (2016): 100–106. http://dx.doi.org/10.21662/uim2016.1.015.

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Key moments of technique of reception and processing of information from the MEMS position sensors in the information system of the manipulator built on the basis units with controlled bend is discussed in detail. The differences in the procedure for construction of multiprocessor information systems based on the new programmable logic integrated circuits large capacity which provide the use of soft-core processors is presented too. The results of qualitative comparison of the solutions obtained by use state machine circuits and schemes based on soft-processors is shown. As an example, conside

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Ochi, Atsuhiko, Toru Tanimori, Yuji Nishi, Shunsuke Aoki, and Yasuro Nishi. "Development of an ultra-fast data-acquisition system for a two-dimensional microstrip gas chamber." Journal of Synchrotron Radiation 5, no. 3 (1998): 1119–22. http://dx.doi.org/10.1107/s0909049597019018.

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A high-performance data-acquisition system has been developed in order to obtain time-resolved sequential images from a two-dimensional microstrip gas chamber (MSGC). This was achieved using fully digital processing with a synchronized pipeline method. Complex logical circuits for processing large numbers of signals are mounted on a small number of complex programmable logic devices. The system is operated with a 10 MHz synchronous clock, and has the capability of handling more than 3 × 106 counts s−1 for asynchronous events. The system was examined using a 5 × 5 cm MSGC and the recently devel

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Goldsworthy, Victoria, Geneva LaForce, Seth Abels, and Emil Khisamutdinov. "Fluorogenic RNA Aptamers: A Nano-platform for Fabrication of Simple and Combinatorial Logic Gates." Nanomaterials 8, no. 12 (2018): 984. http://dx.doi.org/10.3390/nano8120984.

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RNA aptamers that bind non-fluorescent dyes and activate their fluorescence are highly sensitive, nonperturbing, and convenient probes in the field of synthetic biology. These RNA molecules, referred to as light-up aptamers, operate as molecular nanoswitches that alter folding and fluorescence function in response to ligand binding, which is important in biosensing and molecular computing. Herein, we demonstrate a conceptually new generation of smart RNA nano-devices based on malachite green (MG)-binding RNA aptamer, which fluorescence output controlled by addition of short DNA oligonucleotide

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Ou, Qiao-Feng, Bang-Shu Xiong, Lei Yu, Jing Wen, Lei Wang, and Yi Tong. "In-Memory Logic Operations and Neuromorphic Computing in Non-Volatile Random Access Memory." Materials 13, no. 16 (2020): 3532. http://dx.doi.org/10.3390/ma13163532.

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Recent progress in the development of artificial intelligence technologies, aided by deep learning algorithms, has led to an unprecedented revolution in neuromorphic circuits, bringing us ever closer to brain-like computers. However, the vast majority of advanced algorithms still have to run on conventional computers. Thus, their capacities are limited by what is known as the von-Neumann bottleneck, where the central processing unit for data computation and the main memory for data storage are separated. Emerging forms of non-volatile random access memory, such as ferroelectric random access m

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Pischel, Uwe. "Digital Operations with Molecules - Advances, Challenges, and Perspectives." Australian Journal of Chemistry 63, no. 2 (2010): 148. http://dx.doi.org/10.1071/ch09460.

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This Review gives a short introduction into molecular logic and focusses then on the latest advances in the field. With regard to complex logic circuits and functions, molecular devices for arithmetic processing (adders and subtractors), multiplexers/demultiplexers, and encoders/decoders are discussed. Further on, the concept of memory for data storage and sequential logic is considered together with the latest results on molecular keypad locks. Molecular logic has been often connected to the future aim of molecular computing. However, albeit the herein described approaches constitute a starti

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Пирогов, А. А., Ю. А. Пирогова, С. А. Гвозденко, Д. В. Шардаков, and Б. И. Жилин. "DEVELOPMENT OF RECONFIGURABLE DEVICES BASED ON PROGRAMMABLE LOGIC INTEGRATED CIRCUITS." ВЕСТНИК ВОРОНЕЖСКОГО ГОСУДАРСТВЕННОГО ТЕХНИЧЕСКОГО УНИВЕРСИТЕТА, no. 6 (January 10, 2021): 90–97. http://dx.doi.org/10.36622/vstu.2020.16.6.013.

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Цифровая фильтрация распознаваемых сигналов является непременной процедурой при обнаружении и распознавании сообщений. Под фильтрацией понимают любое преобразование сигналов, при котором во входной последовательности обрабатываемых данных целенаправленно изменяются определенные соотношения между различными параметрами сигналов. Системы, избирательно меняющие форму сигналов, устраняющие или уменьшающие помехи, извлекающие из сигналов определенную информацию и т.п., называют фильтрами. Соответственно, фильтры с любым целевым назначением являются частным случаем систем преобразования сигналов. Пр

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Zhao, Zeng Rong. "How to Improve the Data Processing Speed by FPGA." Applied Mechanics and Materials 48-49 (February 2011): 584–88. http://dx.doi.org/10.4028/www.scientific.net/amm.48-49.584.

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With the data acquisition speed and data-width constantly increasing, how to improve the data processing ability is important in real system. So a high speed system is designed based on FPGA, which is the core logic control device. Each circuit model is discussed in detail, which is designed by VHDL or LPM. And their simulation result is gived in the integration circumstance of MAX+plusⅡ.Compared with DSP, the FPGA data processing system is simpler, more effective and lower cost .

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15

Sandhie, Zarin Tasnim, Jill Arvindbhai Patel, Farid Uddin Ahmed, and Masud H. Chowdhury. "Investigation of Multiple-valued Logic Technologies for Beyond-binary Era." ACM Computing Surveys 54, no. 1 (2021): 1–30. http://dx.doi.org/10.1145/3431230.

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Computing technologies are currently based on the binary logic/number system, which is dependent on the simple on and off switching mechanism of the prevailing transistors. With the exponential increase of data processing and storage needs, there is a strong push to move to a higher radix logic/number system that can eradicate or lessen many limitations of the binary system. Anticipated saturation of Moore’s law and the necessity to increase information density and processing speed in the future micro and nanoelectronic circuits and systems provide a strong background and motivation for the be

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Yanushkevich, Svetlana, Hong Tran, Golam Tangim, Vladimir Shmerko, Elena Zaitseva, and Vitaly Levashenko. "The EXOR gate under uncertainty: A case study." Facta universitatis - series: Electronics and Energetics 24, no. 3 (2011): 451–82. http://dx.doi.org/10.2298/fuee1103451y.

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Probabilistic AND/EXOR networks have been defined, in the past, as a class of Reed-Muller circuits, which operate on random signals. In contemporary logic network design, it is classified as behavioral notation of probabilistic logic gates and networks. In this paper, we introduce additional notations of probabilistic AND/EXOR networks: belief propagation, stochastic, decision diagram, neuromorphic models, and Markov random field model. Probabilistic logic networks, and, in particular, probabilistic AND/EXOR networks, known as turbo-decoders (used in cell phones and iPhone) are in demand in th

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17

Zhang, Li, Hualian Tang, Beilei Xu, Yiqi Zhuang, and Junlin Bao. "A High Reliability Sense Amplifier for Computing In-Memory with STT-MRAM." SPIN 10, no. 02 (2020): 2040001. http://dx.doi.org/10.1142/s2010324720400019.

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In the era of big data, massive data requires processing efficiently. However, the limited data bandwidth between the memory and the processor in conventional computer systems could not meet the requirement of data transferring. Computing in-memory has been considered an effective solution to address this problem. In this paper, based on the spin transfer torque-magnetic random access memory (STT-MRAM), a computing in-memory architecture with as few peripheral circuits as possible is proposed. This computing in-memory architecture gives the specific reference cell so that two rows in one array

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He, Wei, Jinguo Huang, Tengxiao Wang, et al. "A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification." Sensors 20, no. 17 (2020): 4715. http://dx.doi.org/10.3390/s20174715.

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This paper proposes a high-speed low-cost VLSI system capable of on-chip online learning for classifying address-event representation (AER) streams from dynamic vision sensor (DVS) retina chips. The proposed system executes a lightweight statistic algorithm based on simple binary features extracted from AER streams and a Random Ferns classifier to classify these features. The proposed system’s characteristics of multi-level pipelines and parallel processing circuits achieves a high throughput up to 1 spike event per clock cycle for AER data processing. Thanks to the nature of the lightweight a

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Hosseininia, Nayereh, Soudabeh Boroumand, and Majid Haghparast. "Novel Nanometric Reversible Low Power Bidirectional Universal Logarithmic Barrel Shifter with Overflow and Zero Flags." Journal of Circuits, Systems and Computers 24, no. 04 (2015): 1550049. http://dx.doi.org/10.1142/s0218126615500498.

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One of the most important issues in designing VLSI circuits is power consumption. Reversible logic which is widely utilized in quantum computing, low power CMOS design, optical information processing, bioinformatics and nanotechnology-based systems decreases power loss. A reversible circuit has zero internal power dissipation because it does not lose information. Reversible barrel shifters are required to construct reversible embedded digital signal and general-purpose processors. Data shifting is often used in high-speed/low-power error-control applications, floating point normalization, addr

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Viamontes, G. F., I. L. Markov, and J. P. Hayes. "Graph-based simulation of quantum computation in the density matrix representation." Quantum Information and Computation 5, no. 2 (2005): 113–30. http://dx.doi.org/10.26421/qic5.2-3.

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Quantum-mechanical phenomena are playing an increasing role in information processing, as transistor sizes approach the nanometer level, and quantum circuits and data encoding methods appear in the securest forms of communication. Simulating such phenomena efficiently is exceedingly difficult because of the vast size of the quantum state space involved. A major complication is caused by errors (noise) due to unwanted interactions between the quantum states and the environment. Consequently, simulating quantum circuits and their associated errors using the density matrix representation is poten

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Атамась, Артем Іванович, Ірина Андріївна Сліпухіна, Ігор Станіславович Чернецький, and Юрій Сергійович Шиховцев. "IMPLEMENTATION OF THE EQUIVALENT CIRCUIT METHOD IN INSTRUMENTAL DIGITAL DIDACTICS." Information Technologies and Learning Tools 82, no. 2 (2021): 1–17. http://dx.doi.org/10.33407/itlt.v82i2.4069.

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Instrumental digital didactics is based on the use of various digital means of obtaining, processing, and interpreting empirical data in accordance with the logic of scientific method and engineering design. Appropriate teaching techniques reflect the STEM approach to teaching natural science and engineering subjects. The use of the equivalent circuit created on the NI Multisim platform to investigate the characteristics of electric circuits’ components creates favorable didactic conditions. The methodological approaches proposed by the authors are demonstrated by the examples of determining t

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Zhu, Saike, Lidan Wang, Zhekang Dong, and Shukai Duan. "Convolution Kernel Operations on a Two-Dimensional Spin Memristor Cross Array." Sensors 20, no. 21 (2020): 6229. http://dx.doi.org/10.3390/s20216229.

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In recent years, convolution operations often consume a lot of time and energy in deep learning algorithms, and convolution is usually used to remove noise or extract the edges of an image. However, under data-intensive conditions, frequent operations of the above algorithms will cause a significant memory/communication burden to the computing system. This paper proposes a circuit based on spin memristor cross array to solve the problems mentioned above. First, a logic switch based on spin memristors is proposed, which realizes the control of the memristor cross array. Secondly, a new type of

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Reuben, John. "Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing." Journal of Low Power Electronics and Applications 10, no. 3 (2020): 28. http://dx.doi.org/10.3390/jlpea10030028.

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As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient log

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Sverdlov, Viktor, and Siegfried Selberherr. "Demands for spin-based nonvolatility in emerging digital logic and memory devices for low power computing." Facta universitatis - series: Electronics and Energetics 31, no. 4 (2018): 529–45. http://dx.doi.org/10.2298/fuee1804529s.

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Miniaturization of semiconductor devices is the main driving force to achieve an outstanding performance of modern integrated circuits. As the industry is focusing on the development of the 3nm technology node, it is apparent that transistor scaling shows signs of saturation. At the same time, the critically high power consumption becomes incompatible with the global demands of sustaining and accelerating the vital industrial growth, prompting an introduction of new solutions for energy efficient computations. Probably the only radically new option to reduce power consumption in novel integrat

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Kumar, Vinay, Ankit Singh, Shubham Upadhyay, and Binod Kumar. "Power–Delay-Error-Efficient Approximate Adder for Error-Resilient Applications." Journal of Circuits, Systems and Computers 28, no. 10 (2019): 1950171. http://dx.doi.org/10.1142/s0218126619501718.

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Power dissipation has been the prime concern for CMOS circuits. Approximate computing is a potential solution for addressing this concern as it reduces power consumption resulting in improved performance in terms of power–delay product (PDP). Decrease of power consumption in approximate computing is achieved by approximating the demand of accuracy as per the error tolerance of the system. This paper presents a new approach for designing approximate adder by introducing inexactness in the existing logic gate(s). Approximated logic gates provide flexibility in designing low power error-resilient

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Tripathi, Devendra Kr. "Investigations with Reversible Feynman Gate and Irreversible Logic Schematics." Journal of Optical Communications 40, no. 4 (2019): 385–92. http://dx.doi.org/10.1515/joc-2017-0106.

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Abstract In the contemporary world there is enormous hike in communication engineering applications, outcome with massive heat dissipation from the processing nodes. So energy efficient information network is one of paramount issue nowadays. For that optical reversible computing could be a landmark with base as optical logic gate. Reduction in power dissipation, consumption could be accomplished through a blend of reversible and irreversible optical processing and the nodes may recuperate the data. Accordingly, in this article two designs with semiconductor optical amplifier, used as Mach–Zehn

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Lin, Hai Yan, Hai Liu, and Yin Zhao Wang. "Design of Hardware Based on Control Circuit of APF." Applied Mechanics and Materials 148-149 (December 2011): 353–56. http://dx.doi.org/10.4028/www.scientific.net/amm.148-149.353.

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In this paper, we focus on the hardware design of control circuit based on shunt active power filter (APF). It described the AD transformation module, DSP data processing module, CPLD logic control module, man-machine interaction module and asynchronous communication module. As the core controller, TMS320C5416 digital signal processor (DSP) controls this peripheral assistant circuit to complete data acquisition, harmonic detection and output of control signal. Finally, we design the layout and routing of the control circuit.

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28

Soref, Richard. "Reconfigurable Integrated Optoelectronics." Advances in OptoElectronics 2011 (May 4, 2011): 1–15. http://dx.doi.org/10.1155/2011/627802.

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Integrated optics today is based upon chips of Si and InP. The future of this chip industry is probably contained in the thrust towards optoelectronic integrated circuits (OEICs) and photonic integrated circuits (PICs) manufactured in a high-volume foundry. We believe that reconfigurable OEICs and PICs, known as ROEICs and RPICs, constitute the ultimate embodiment of integrated photonics. This paper shows that any ROEIC-on-a-chip can be decomposed into photonic modules, some of them fixed and some of them changeable in function. Reconfiguration is provided by electrical control signals to the

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Grübl, Andreas, Sebastian Billaudelle, Benjamin Cramer, Vitali Karasenko, and Johannes Schemmel. "Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System." Journal of Signal Processing Systems 92, no. 11 (2020): 1277–92. http://dx.doi.org/10.1007/s11265-020-01558-7.

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Abstract This paper presents verification and implementation methods that have been developed for the design of the BrainScaleS-2 65 nm ASICs. The 2nd generation BrainScaleS chips are mixed-signal devices with tight coupling between full-custom analog neuromorphic circuits and two general purpose microprocessors (PPU) with SIMD extension for on-chip learning and plasticity. Simulation methods for automated analysis and pre-tapeout calibration of the highly parameterizable analog neuron and synapse circuits and for hardware-software co-development of the digital logic and software stack are pre

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Pinto, Felipe, and Ioannis Vourkas. "Robust Circuit and System Design for General-Purpose Computational Resistive Memories." Electronics 10, no. 9 (2021): 1074. http://dx.doi.org/10.3390/electronics10091074.

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Resistive switching devices (memristors) constitute a promising device technology that has emerged for the development of future energy-efficient general-purpose computational memories. Research has been done both at device and circuit level for the realization of primitive logic operations with memristors. Likewise, important efforts are placed on the development of logic synthesis algorithms for resistive RAM (ReRAM)-based computing. However, system-level design of computational memories has not been given significant consideration, and developing arithmetic logic unit (ALU) functionality en

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Yu, Wen Wei, and Zhi Wen Chen. "The Study on Evolvable Electrical Circuit Design Based on FPGA." Advanced Materials Research 433-440 (January 2012): 5494–99. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.5494.

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The traditional evolutionary algorithm needs a lot of storage and handling ability in embedded logic project. Candidate’s solutions through the population, rather than the probability of vector of save memory and bite string processing. Concise evolutionary algorithm (CEA) is a probability vector based evolutionary algorithm is proposed. This paper proposes a method of realizing the standard FPGA concise evolutionary algorithm with a few changes to improve search powers. A data flow and a block diagram design, this paper describes the show. Experimental results show that the requirements (logi

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Wang, Xin Chun, Yue Hong Peng, Man Cheng, and Kai Hua Yue. "Design and Realization of High-Speed and Real-Time Signal Processing System Based on FPGA." Applied Mechanics and Materials 128-129 (October 2011): 1382–85. http://dx.doi.org/10.4028/www.scientific.net/amm.128-129.1382.

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We usually adopt DSP and ARM to perform signal collection and processing. However, functions of DSP and ARM largely depend on the software. Parameter modulation of the software must account for sampling time partly. Moreover, software can not control complex peripheral logic circuit very well. The above problems render DSP and ARM containing big flaws in high-speed data collection and processing. Field-programmable Gate Array (FPGA) possesses the characteristics of timeliness, controllability and rapid processing speed. The paper designed a new circuit based on FPGA to obtain high-speed signal

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Zhang, Geng, and Hao Xu. "Software Design Based on PLD High-Speed Data Acquisition System." Advanced Materials Research 798-799 (September 2013): 647–50. http://dx.doi.org/10.4028/www.scientific.net/amr.798-799.647.

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Data collection in the important position of modern industrial production and scientific research is increasingly outstanding, as well as the real-time collection, real-time transmission and real-time processing of high speed data acquisition requirements are constantly improve. In addition, for different occasions, the data acquisition system of data sampling parameters are different. PLD as a universal integrated circuit, its logic function according to user's programming on the device, this paper introduces the high-speed data acquisition system based on PLD, mainly expounds the software de

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Dai, Lan, та Chengying Chen. "A 69-dB SNR 89-μW AGC for Multifrequency Signal Processing Based on Peak-Statistical Algorithm and Judgment Logic". VLSI Design 2016 (29 грудня 2016): 1–7. http://dx.doi.org/10.1155/2016/6708253.

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A novel peak-statistical algorithm and judgment logic (PSJ) for multifrequency signal application of Autogain Control Loop (AGC) in hearing aid SoC is proposed in this paper. Under a condition of multifrequency signal, it tracks the amplitude change and makes statistical data of them. Finally, the judgment is decided and the circuit gain is controlled precisely. The AGC circuit is implemented with 0.13 μm 1P8M CMOS mixed-signal technology. Meanwhile, the low-power circuit topology and noise-optimizing technique are adopted to improve the signal-to-noise ratio (SNR) of our circuit. Under 1 V vo

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Lin, Guangfu, Zhenxing Yin, and Guo Feng. "Design and Implementation of Bipolar Digital Signal Acquisition and Processing System Based on FPGA and ACPL-224." International Journal of Advanced Pervasive and Ubiquitous Computing 3, no. 4 (2011): 1–5. http://dx.doi.org/10.4018/japuc.2011100101.

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This paper proposes new approaches for designing a bipolar DS acquisition system to reduce the harm of external factors on equipment, as well as fulfill system requirements at the veracity and reliability of the equipment to quickly connect. The design method chosen is ACPL-224 for chip of the interface about data acquisition on the FPGA device, including system principle, interface circuit logic, the method of data processing, and so forth. Now that this method has been applied, it has achieved good results, including extending the system’s adaptive range of external signal and enhancing the

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Kryukov, Oleg, Alexander Saushev, Olga Shergina, and Artem Butsanets. "Electromagnetic compatibility of multifunctional automation systems for electrical equipment using the example of electric drives." E3S Web of Conferences 244 (2021): 09007. http://dx.doi.org/10.1051/e3sconf/202124409007.

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The main factors of information compatibility of automatic control systems for energy-saving electric drives are proposed, built on the basis of multifunctional algorithms, when integrated into a single information space of an enterprise. The method for assessing compatibility allows one to purposefully vary the specific shares of data storage and processing processes in the software, as well as to solve the problems of computer modeling and the choice of identification and adaptation algorithms in the general cycle of work. The indicators of the systems operability are given – the coefficient

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Hameed, Ahmed Salah, and Marwa Jawad Kathem. "High speed modified carry save adder using a structure of multiplexers." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 2 (2021): 1591. http://dx.doi.org/10.11591/ijece.v11i2.pp1591-1598.

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Adders are the heart of data path circuits for any processor in digital computer and signal processing systems. Growth in technology keeps supporting efficient design of binary adders for high speed applications. In this paper, a fast and area-efficient modified carry save adder (CSA) is presented. A multiplexer based design of full adder is proposed to implement the structure of the CSA. The proposed design of full adder is employed in designing all stages of traditional CSA. By modifying the design of full adder in CSA, the complexity and area of the design can be reduced, resulting in reduc

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Mucha, Waldemar, and Wacław Kuś. "FPGA Support in Hybrid Simulation Using Finite Element Method." Solid State Phenomena 260 (July 2017): 105–12. http://dx.doi.org/10.4028/www.scientific.net/ssp.260.105.

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Hybrid simulation, or hybrid testing, is understood here as a numerical technique for investigating dynamic properties of mechanical systems with components that are difficult to model numerically. This technique can be also referred to as hardware-in-the-loop simulation.The idea of hybrid simulation is that the non-linear part of the system that is difficult to model numerically is tested experimentally and the rest of the system is modeled numerically. Therefore two models are created – the experimental model and the analytical model. During the simulation both models are in strict cooperati

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Yang, Shou Liang, and Ling Gang Zeng. "The Design of the Permanent Magnet Vacuum Circuit Breaker Control System Based on SOPC." Applied Mechanics and Materials 530-531 (February 2014): 1036–42. http://dx.doi.org/10.4028/www.scientific.net/amm.530-531.1036.

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This paper analyzes the instantaneous value of the three-phase circuit measurements of various parameters and the key issues to be addressed , to design a new type of intelligent SOPC based on a permanent magnet vacuum circuit breaker control system. FPGA-based NIOS II as the main processor , the more traditional micro-controller with a higher data processing speed and strong expansion capability to effectively meet the electricity system fast data processing capability and high real-time requirements . And with a powerful FPGA logic functions to achieve internal switch control section and the

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Gnoli, Luca, Fabrizio Riente, Marco Vacca, Massimo Ruo Roch, and Mariagrazia Graziano. "Skyrmion Logic-In-Memory Architecture for Maximum/Minimum Search." Electronics 10, no. 2 (2021): 155. http://dx.doi.org/10.3390/electronics10020155.

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In modern computing systems there is the need to utilize a large amount of data in maintaining high efficiency. Limited memory bandwidth, coupled with the performance gap between memory and logic, impacts heavily on algorithms performance, increasing the overall time and energy required for computation. A possible approach to overcome such limitations is Logic-In-Memory (LIM). In this paper, we propose a LIM architecture based on a non-volatile skyrmion-based recetrack memory. The architecture can be used as a memory or can perform advanced logic functions on the stored data, for example searc

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D’Addato, Matteo, Alessia M. Elgani, Luca Perilli, et al. "A Gated Oscillator Clock and Data Recovery Circuit for Nanowatt Wake-Up and Data Receivers." Electronics 10, no. 7 (2021): 780. http://dx.doi.org/10.3390/electronics10070780.

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This article presents a data-startable baseband logic featuring a gated oscillator clock and data recovery (GO-CDR) circuit for nanowatt wake-up and data receivers (WuRxs). At each data transition, the phase misalignment between the data coming from the analog front-end (AFE) and the clock is cleared by the GO-CDR circuit, thus allowing the reception of long data streams. Any free-running frequency mismatch between the GO and the bitrate does not limit the number of receivable bits, but only the maximum number of equal consecutive bits (Nm). To overcome this limitation, the proposed system inc

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Грановский and E. Granovskiy. "Technical Regulation of Safety of Industrial Facilities: Analyses and Risk Quantitative Assessment." Safety in Technosphere 5, no. 5 (2016): 54–63. http://dx.doi.org/10.12737/24152.

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The methods of quantitative risk assessment based on results of hazard analysis using both expert estimates and systematic analysis of a dangerous object are discussed. It is shown that when the experts are measuring the risk factors, quantitative assessment risk without statistical processing of expert opinions and evaluation of the reliability of the result is not adequate. The basic methods of system analysis for quantitative risk assessment are considered. It is shown that the frequency of emergency depressurization for certain types of equipment given in the normative documents, received

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Ruchkin, Daniel S., Jordan Grafman, Katherine Cameron, and Rita S. Berndt. "Working memory: Unemployed but still doing day labor." Behavioral and Brain Sciences 26, no. 6 (2003): 760–69. http://dx.doi.org/10.1017/s0140525x03550166.

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The goal of our target article is to establish that electrophysiological data constrain models of short-term memory retention operations to schemes in which activated long-term memory is its representational basis. The temporary stores correspond to neural circuits involved in the perception and subsequent processing of the relevant information, and do not involve specialized neural circuits dedicated to the temporary holding of information outside of those embedded in long-term memory. The commentaries ranged from general agreement with the view that short-term memory stores correspond to act

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Tian, Tian, Peng Li, Huiqun Huang, Yilin Pu, and Bin Wu. "A Low Spur and Low Jitter Quadrature LO-Generator Using CML Inductive Peaking Technique for WLAN Transceiver." Electronics 10, no. 15 (2021): 1869. http://dx.doi.org/10.3390/electronics10151869.

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The demand for a local oscillator (LO) signal of high quality and integrity in local area network (WLAN) communication is growing with the increasing date rate. The LO signals for high data rate WLAN applications are desired to not only have proper shape waveforms and adequate voltage amplitude but also to achieve relatively stable and clean outputs with low phase noise and low spur. Fractional-N frequency planning is critical for a quadrature LO-generator, which is achieved by a single-sideband (SSB) mixer and multiple dividers since it can avoid the frequency pulling and alleviate the self-m

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Mandal, Dhoumendra, Sumana Mandal, Mrinal Kanti Mandal, and Sisir Kumar Garai. "Alternative Approach of Developing Optical Binary Adder Using Reversible Peres Gates." International Journal of Optics 2018 (2018): 1–13. http://dx.doi.org/10.1155/2018/8541371.

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All-optical devices will play a very significant and crucial role in the modern all-optical network by eliminating the bottleneck of opto-electro-opto- (O-E-O-) conversion. Unfortunately, the conventional logic gates lose information at the output, and the states of the outputs cannot give any credible impressions of the states of the inputs. In this article, at first, the authors have proposed a method of designing an optical three-input-three-output reversible Peres gate. Authors have deployed polarization switching characteristic of Semiconductor Optical Amplifier (SOA) for designing this c

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Liu, Sheng Hu, and Ya Min Xing. "Application of Digital Phase Sensitive Detection for Electromagnetic Propagation Logging while Drilling." Advanced Materials Research 468-471 (February 2012): 546–49. http://dx.doi.org/10.4028/www.scientific.net/amr.468-471.546.

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Intense electromagnetic interference while drilling prevents traditional analog phase sensitive detection (APSD) from correctly acquiring electromagnetic wave signal of logging while drilling (LWD). A digital phase sensitive detection (DPSD) utilizes high-performance floating-point DSP and FPGA to separately process real part and imaginary part of the acquired logging signal, changes traditional calculating method, improves processing speed and calculating precision. The programmable technique used can fully utilize logging information, simplify control logic, improve precision of timing contr

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Hatirnaz, İ., F. K. Gürkaynak, and Y. Leblebici. "A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic." VLSI Design 11, no. 2 (2000): 115–28. http://dx.doi.org/10.1155/2000/98945.

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We present a new scalable architecture for the realization of fully programmable rank order filters (ROF). Capacitive Threshold Logic (CTL) gates are utilized for the implementation of the multi-input programmable majority (voting) functions required in the architecture. The CTL-based realization of the majority gates used in the ROF architecture allows the filter rank as well as the window size to be user-programmable, using a much smaller silicon area, compared to conventional realizations of digital median filters. The proposed filter architecture is completely modular and scalable, and the

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Pfänder, O. A., H. J. Pfleiderer, and S. W. Lachowicz. "Configurable multiplier modules for an adaptive computing system." Advances in Radio Science 4 (September 6, 2006): 231–36. http://dx.doi.org/10.5194/ars-4-231-2006.

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Abstract. The importance of reconfigurable hardware is increasing steadily. For example, the primary approach of using adaptive systems based on programmable gate arrays and configurable routing resources has gone mainstream and high-performance programmable logic devices are rivaling traditional application-specific hardwired integrated circuits. Also, the idea of moving from the 2-D domain into a 3-D design which stacks several active layers above each other is gaining momentum in research and industry, to cope with the demand for smaller devices with a higher scale of integration. However,

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Atamas, A. I., I. A. Slipukhina, I. S. Chernetckyi, and Y. S. Shykhovtsev. "Virtual environments for the design of electronic devices as a means of instrumental digital didactics." Scientific Notes of Junior Academy of Sciences of Ukraine, no. 2(18) (2020): 57–67. http://dx.doi.org/10.51707/2618-0529-2020-18-06.

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Instrumental digital didactics reflects the application to education of various digital means of obtaining, processing and interpreting experimental data in accordance with the logic of the scientific method and engineering design. An important component of a modern STEM-oriented educational environment are innovative software products for modelling and simulation of electronic circuits. In educational research projects on their basis, the parameters of the components of electrical circuits created in virtual environments are compared with the technical characteristics of similar devices avail

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Xue, Yan Lin, and Bin Wei Chen. "A Research about Acquisition and Transmission of the Water Meter's Image Based on STM32." Advanced Materials Research 1037 (October 2014): 187–90. http://dx.doi.org/10.4028/www.scientific.net/amr.1037.187.

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This paper introduces the hardware and programming involved in collecting the image of the digital code wheel by microprocessor STM32 directly driving camera chip OV7670 and the transmission of collected image. This design simplifies the hardware structure to the greatest extent and minimizes cost. Our design has three advantages. Fist, direct driving saves the intermediary register chip, simplifies the circuit and also reduces the amount of elements used. Second, by using the CMOS digital image sensor with windowing function—OV7670 to capture the image of code wheel we simplify the hardware s

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