Relevant bibliographies by topics / Logic circuits Design and construction

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Logic circuits Design and construction'

Author: Grafiati
Published: 4 June 2021
Last updated: 11 February 2022

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Journal articles on the topic "Logic circuits Design and construction"

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Avdeev, N. A., and P. N. Bibilo. "Design of Digital Operational Units with Low Power Consumption." Programmnaya Ingeneria 12, no. 2 (March 16, 2021): 63–73. http://dx.doi.org/10.17587/prin.12.63-73.

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The lowering of power consumption in CMOS VLSI digital systems is one of the most important problems that appear now for developers of CAD systems. One of the effective approaches to lowering the dynamic power consumption is creation of an algorithmic description of the VHDL project, which provides for the deactivation of some functional blocks which are not necessary in particular moments. Contemporary synthesizers fulfill the high level synthesis of logic circuits by substitution of description of each VHDL construction with functionally structural description of a proper logic subcircuit. The results of digital logic circuit synthesis (the number of logic elements and power consumption) depend significantly on initial VHDL code. During initial VHDL code development it is possible to use different approaches to improve some parameters of synthesized logic circuit. At the algorithmic level of the digital design, it is necessary to provide for disconnection of the units, which cause the higher power consumption. In this paper such methods of algorithmic VHDL description of logic circuit are studied. The efficiency of the proposed methods is compared with the traditional method of VHDL-description which does not take the aspect of power con­sumption into account and is oriented only to the correct functionality of the developed logic circuit. To estimate the power consumption of logic circuits the approach is used which allows applying high-speed logical VHDL-simulation of structural descriptions (netlists) of logic circuits instead of slow SPICE simulation. The main conclusion of the provided study is the following: the clock gating and the storage of operand values for complex operations as well as zero value setting for simple ones are effective methods for the VHDL description of operational units with low power consumption implemented in the CMOS basis.
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Maity, Heranmoy, Sudipta Banerjee, Arindam Biswas, Anita Pal, and Anup Kumar Bhattacharjee. "Design of Reversible Shift Register Using Reduced Number of Logic Gates." Micro and Nanosystems 12, no. 1 (January 21, 2020): 33–37. http://dx.doi.org/10.2174/1876402911666190617112734.

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Background: Over the last few decades, reversible logic system/circuits have received considerable attention in the diversified fields such as nanotechnology, quantum computing, cryptography, optical computing and low power design of VLSI circuits due to their low power dissipation characteristics. Methods: In this paper, we proposed the design of reversible shift register (SR) i.e. serial-in-serial out (SISO), serial-in-parallel out (SIPO), parallel-in-serial out (PISO) and parallel-in-parallel out (PIPO) SR using a reduced number of reversible logic gates and garbage output. Results: As compared to previously reported results, the improvement in our proposed model of SISO, SIPO, PISO and PIPO was found to be 50 – 66.66 %, 42.85 – 66.66 %, 12.5 – 53.33 % and 50 – 66.66 % respectively, in terms of the number of reversible logic gates.
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Jóźwiak, Lech. "General Decomposition and Its Use in Digital Circuit Synthesis." VLSI Design 3, no. 3-4 (January 1, 1995): 225–48. http://dx.doi.org/10.1155/1995/16259.

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Modem microelectronic technology.gives opportunities to build digital circuits of huge complexity and provides a wide diversity of logic building blocks. Although logic designers have been building circuits for many years, they have realized that advances in microelectronic technology are outstripping their abilities to make use of the created opportunities. In this paper, we present the fundamentals of a logic design methodology which meets the requirements of today's complex circuits and modem building blocks. The methodology is based on the theory of general full-decompositions which constitutes the theory of digital circuit structures at the highest abstraction level. The paper explains the theory and shows how it can be used for digital circuit synthesis. The decomposition methodology that is presented ensures “correctness by construction” and enables very effective and efficient post-factum validation. It makes possible extensive examination of the structural features of the required information processing in relation to a given set of objectives and constraints.
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Abdulnabi, Saif, and Mohammed Abbas. "Design an All-Optical Combinational Logic Circuits Based on Nano-Ring Insulator-Metal-Insulator Plasmonic Waveguides." Photonics 6, no. 1 (March 19, 2019): 30. http://dx.doi.org/10.3390/photonics6010030.

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In this paper, we propose, analyze and simulate a new configuration to simulate all-optical combinational logic functions based on Nano-rings insulator-metal-insulator (IMI) plasmonic waveguides. We used Finite Element Method (FEM) to analyze the proposed plasmonic combinational logic functions. The analyzed combinational logic functions are Half-Adder, Full-Adder, Half-Subtractor, and Comparator One-Bit. The operation principle of these combinational logic functions is based on the constructive and destructive interferences between the input signal(s) and control signal. Numerical simulations show that a transmission threshold exists (0.25) which allows all proposed four plasmonic combinational logic functions to be achieved in one structure. As a result, the transmission threshold value measures the performance of the proposed plasmonic combinational logic functions. We use the same structure with the same dimensions at 1550 nm wavelength for all proposed plasmonic combinational logic functions. The proposed all-optical combinational logic functions structure contributes significantly to photonic integrated circuits construction and all-optical signal processing nano-circuits.
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Zaitseva, Elena, Vitaly Levashenko, Igor Lukyanchuk, Jan Rabcan, Miroslav Kvassay, and Patrik Rusnak. "Application of Generalized Reed–Muller Expression for Development of Non-Binary Circuits." Electronics 9, no. 1 (December 21, 2019): 12. http://dx.doi.org/10.3390/electronics9010012.

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Semiconductor devices and binary information technology reach their limits set by the atomic size of miniaturization, calculation speed, and the fundamental principle of energy dissipation per bit processing. Therefore, new technologies in logic design and mathematical approaches must be investigated. Application of multiple-valued logic (MVL) in logic design allows developing gates and circuits with more than two stable states. This enables packing an unprecedented high-density of information. Based on this idea, a new technique of the programmable logic arrays (PLA) construction based on MVL units is considered. The unique aspect of this technique is the application of recurrent generalized Reed–Muller expression (GRME) for MVL function representation. The recurrent procedure for this expression’s construction is considered and applied in the PLA development. The proposed structure of PLA consists of two blocks that are memory and logic block. In this paper, we also consider the possibility to use the ferroelectrics for the implementation of cells of the memory block of PLA. The development of gates with multi-stable states is possible by the ferroelectrics ability to pin the polarization as a sequence of stable states.
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Melnyk, Oleksandr, and Viktoriia Kozarevych. "SIMULATION OF PROGRAMMABLE SINGLE-ELECTRON NANOCIRCUITS." Bulletin of the National Technical University "KhPI". Series: Mathematical modeling in engineering and technologies, no. 1 (March 5, 2021): 64–68. http://dx.doi.org/10.20998/2222-0631.2020.01.05.

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The speed and specializations of large-scale integrated circuits always contradict their versatility, which expands their range and causes the rise in price of electronic devices. It is possible to eliminate the contradictions between universality and specialization by developing programmable nanoelectronic devices, the algorithms of which are changed at the request of computer hardware developers, i.e. by creating arithmetic circuits with programmable characteristics. The development of issues of theory and practice of the majority principle is now an urgent problem, since the nanoelectronic execution of computer systems with programmable structures will significantly reduce their cost and significantly simplify the design stage of automated systems. Today there is an important problem of developing principles for building reliable computer equipment. The use of mathematical and circuit modeling along with computer-aided design systems (CAD) can significantly increase the reliability of the designed devices. The authors prove the advantages of creating programmable nanodevices to overcome the physical limitations of micro-rominiatization. This continuity contributes to the accelerated introduction of mathematical modeling based on programmable nanoelectronics devices. The simulation and computer-aided design of reliable programmable nanoelectronic devices based on the technology of quantum automata is described. While constructing single-electron nanocircuits of combinational and sequential types the theory of majority logic is used. The order of construction and programming of various types of arithmetic-logic units is analyzed.
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Waheed, Sajjad, Sharmin Aktar, and Ali Newaz Bahar. "A Novel Design and Implementation of New Double Feynman and Six-correction logic (DFSCL) gates in Quantum-dot Cellular Automata (QCA)." European Scientific Journal, ESJ 13, no. 15 (May 31, 2017): 265. http://dx.doi.org/10.19044/esj.2017.v13n15p265.

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In recent years, quantum cellular automata (QCA) have been used widely to digital circuits and systems. QCA technology is a promising alternative to CMOS technology. It is attractive due to its fast speed, small area and low power consumption. The QCA offers a novel electronics paradigm for information processing and communication. It has the potential for attractive features such as faster speed, higher scale integration, higher switching frequency, smaller size and low power consumption than transistor based technology. In this paper, Double Feynman and Six-correction logic gate (DFSCL) is proposed based on QCA logic gates: MV gate and Inverter gate. The proposed circuit is a promising future in constructing of nano-scale low power consumption information processing system and can stimulate higher digital applications in QCA.
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Jóźwiak, Lech, Aleksander Ślusarczyk, and Marek Perkowski. "Term Trees in Application to an Effective and Efficient ATPG for AND–EXOR and AND–OR Circuits." VLSI Design 14, no. 1 (January 1, 2002): 107–22. http://dx.doi.org/10.1080/10655140290009837.

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A compact data representation, in which the typically required operations are performed rapidly, and effective and efficient algorithms that work on these representations are the essential elements of a successful CAD tool. The objective of this paper is to present a new data representation—term trees (TTs)—and to discuss its application for an effective and efficient structural automatic test-pattern generation (ATPG). Term trees are decision diagrams similar to BDDs that are particularly suitable for structure representation of AND–OR and AND–EXOR circuits. In the paper, a flexible algorithm for minimum term-tree construction is discussed and an effective and efficient algorithm for ATPG for AND–EXOR and AND–OR circuits is proposed. The term trees can be used for many other purposes in logic design and in other areas—for all purposes where compact representation and efficient manipulation of term sets is important. The presented experimental results show that term trees are indeed a compact data representation allowing fast manipulations. They form a good base for algorithms considering the function's and circuit's term structures.
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Mozyrsky, Dima, Vladimir Privman, and Steven P. Hotaling. "Design of Gates for Quantum Computation: The NOT Gate." International Journal of Modern Physics B 11, no. 18 (July 20, 1997): 2207–15. http://dx.doi.org/10.1142/s0217979297001143.

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We offer an alternative to the conventional network formulation of quantum computing. We advance the analog approach to quantum logic gate/circuit construction. As an illustration, we consider the spatially extended NOT gate as the first step in the development of this approach. We derive an explicit form of the interaction Hamiltonian corresponding to this gate and analyze its properties. We also discuss general extensions to the case of certain time-dependent interactions which may be useful for practical realization of quantum logic gates.
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Атамась, Артем Іванович, Ірина Андріївна Сліпухіна, Ігор Станіславович Чернецький, and Юрій Сергійович Шиховцев. "IMPLEMENTATION OF THE EQUIVALENT CIRCUIT METHOD IN INSTRUMENTAL DIGITAL DIDACTICS." Information Technologies and Learning Tools 82, no. 2 (April 25, 2021): 1–17. http://dx.doi.org/10.33407/itlt.v82i2.4069.

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Instrumental digital didactics is based on the use of various digital means of obtaining, processing, and interpreting empirical data in accordance with the logic of scientific method and engineering design. Appropriate teaching techniques reflect the STEM approach to teaching natural science and engineering subjects. The use of the equivalent circuit created on the NI Multisim platform to investigate the characteristics of electric circuits’ components creates favorable didactic conditions. The methodological approaches proposed by the authors are demonstrated by the examples of determining the parameters of technologically advanced devices - photoelectric converter (for example, determining its maximum power point, as well as Fill Factor) and supercapacitor (for example, designating changes in charging and discharging characteristics depending on the type of construction). In such educational projects the parameters of the circuit components obtained by the equivalent circuit method are compared with the specifications of commercial devices available on the market. This approach, on the one hand, demonstrates statistical errors of results to the students, and on the other hand, it is a source of sufficient data for constructing an equivalent circuit of devices without prior experimental research. It is shown that the use of equivalent circuits in a computer simulation environment to replace real electronic and electrical devices, measuring systems and equipment with their virtual counterparts expands the didactic possibilities. Techniques based on the versatile use of digital didactic tools are being actively developed and implemented in the MANLab STEM-laboratory of the National Centre “Junior Academy of Sciences of Ukraine”.
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Dissertations / Theses on the topic "Logic circuits Design and construction"

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Nguyen, Loc Bao. "Logic design using programmable logic devices." PDXScholar, 1988. https://pdxscholar.library.pdx.edu/open_access_etds/4103.

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The Programmable Logic Devices, PLO, have caused a major impact in logic design of digital systems in this decade. For instance, a twenty pin PLO device can replace from three hundreds to six hundreds Transistor Transistor Logic gates, which people have designed with since the 60s. Therefore, by using PLD devices, designers can squeeze more features, reduce chip counts, reduce power consumption, and enhance the reliability of the digital systems. This thesis covers the most important aspects of logic design using PLD devices. They are Logic Minimization and State Assignment. In addition, the thesis also covers a seldomly used but very useful design style, Self-Synchronized Circuits. The thesis introduces a new method to minimize Two-Level Boolean Functions using Graph Coloring Algorithms and the result is very encouraging. The raw speed of the coloring algorithms is as fast as the Espresso, the industry standard minimizer from Berkeley, and the solution is equally good. The thesis also introduces a rule-based state assignment method which gives equal or better solutions than STASH (an Intel Automatic CAD tool) by as much as twenty percent. One of the problems with Self-Synchronized circuits is that it takes many extra components to implement the circuit. The thesis shows how it can be designed using PLD devices and also suggests the idea of a Clock Chip to reduce the chip count to make the design style more attractive.
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Zhou, Jing 1959. "LOVERD--a logic design verification and diagnosis system via test generation." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/291686.

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The development of cost-effective circuits is primarily a matter of economy. To achieve it, design errors and circuit flaws must be eliminated during the design process. To this end, considerable effort must be put into all phases of the design cycle. Effective CAD tools are essential for the production of high-performance digital systems. This thesis describes a CAD tool called LOVERD, which consists of ATPG, fault simulation, design verification and diagnosis. It uses test patterns, developed to detect single stuck-at faults in the gate-level implementation, to compare the results of the functional level description and its gate-level implementation. Whenever an error is detected, the logic diagnosis tool can be used to provide useful information to designers. It is shown that certain types of design errors in combinational logic circuits can be detected and allocated by LOVERD efficiently.
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Sah, Puja. "Implementing Digital Logic Design Concepts Using Paper Electronics." Thesis, University of North Texas, 2018. https://digital.library.unt.edu/ark:/67531/metadc1157633/.

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This thesis presents the implementation of some of the basic concepts of digital logic design in a fun and creative way with the help of paper electronics. This involves circuit building on paper using conductive tape or conductive ink and circuit components as electronics craft materials. Paper electronics toolkit called circuit sticker microcontroller which is deployed by a company named Chibitronics and AT89C51 microcontroller were used for the computational functioning of the circuits built on paper. This can be used to teach the fundamentals of digital logic design to the students in their early stage of studies in an attractive way and can help them them gain a better understanding. This thesis can also be helpful in grabbing the attention of high school students and motivate them towards choosing the engineering discipline for their higher studies.
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Orr, Marc Stewart. "A Logic Formulation for the QCA Cell Arrangement Problem." PDXScholar, 2010. https://pdxscholar.library.pdx.edu/open_access_etds/438.

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Some people believe that IC densities are approaching the fundamental limits inherent to semiconductor technologies. One alternative to semiconductors is Quantum-dot Cellular Automata (QCA); QCA is a nanotechnology that offers the potential to build denser IC's that switch at higher frequencies and run on lower power. QCA's most basic building block, the QCA cell, is inherently binary; digital circuits are implemented by arranging these QCA cells in pre-defined configurations on a two dimensional plane. This paper proposes a logic formulation that describes arranging QCA cells on a two dimensional plane; it is presented as a set of rules that can be implemented with basic Boolean variables and operators. This Boolean formulation is general and can be applied to any given specification. In addition, an optimization constraint is defined so that the logic formulation will only validate the most efficient QCA cell arrangements. The correctness of the logic formulation has been empirically verified by testing it with a SAT solver. The effectiveness of the minimization constraint in conjunction with the logic formulation has been tested with a Pseudo-Boolean ILP solver.
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Bhavnagarwala, Azeez Jenúddin. "Voltage scaling constraints for static CMOS logic and memory cirucits." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15401.

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Battina, Brahmasree. "An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design." Thesis, University of North Texas, 2014. https://digital.library.unt.edu/ark:/67531/metadc799495/.

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Integrated Circuits (ICs) have a broad range of applications in healthcare, military, consumer electronics etc. The acronym VLSI stands for Very Large Scale Integration and is a process of making ICs by placing millions of transistors on a single chip. Because of advancements in VLSI design technologies, ICs are getting smaller, faster in speed and more efficient, making personal devices handy, and with more features. In this thesis work an interactive framework is designed in which the fundamental concepts of digital logic design and VLSI design such as logic gates, MOS transistors, combinational and sequential logic circuits, and memory are presented in a simple, interactive and user friendly way to create interest in students towards engineering fields, especially Electrical Engineering and Computer Engineering. Most of the concepts are explained in this framework by taking the examples which we see in our daily lives. Some of the critical design concerns such as power and performance are presented in an interactive way to make sure that students can understand these significant concepts in an easy and user friendly way.
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Ho, Philip. "Investigation of Solution Space of Trees and DAGs for Realization of Combinational Logic in AT 6000 series FPGAs." PDXScholar, 1993. https://pdxscholar.library.pdx.edu/open_access_etds/4586.

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Various tree and Directed Acyclic Graph structures have been used for representation and manipulation of switching functions. Among these structures the Binary Decision DiagramJilave been the most widely used in logic synthesis. A BDD is a binary tree graph that represents the recursive execution of Shannon's expansion. A FDD is a directed function graph that represents the recursive execution of Reed Muller expansion. A family of decision diagrams for representation of Boolean function is introduced in this thesis. This family of Kronecker Functional Decision Diagrams (KFDD) includes the Binary Decision Diagrams (BDD) and Functional Decision Diagrams (FDD) as subsets. Due to this property, KFDDs can provide a more compact representation of the functions than either of the two above-mentioned decision diagrams. The new notion of permuted KFDD is introduced to generate a compact circuit in FPGAs to represent a switching function. A permuted tree search is a free search method which is not limited by the order of variable and the expansion tree as in the cases of KFDD, BDD and FDD. A family of decision diagrams and the theory developed for them are presented in this thesis. The family of permuted Kronecker Functional Decision Diagrams includes BODs and FDDs as subsets is incorporated into program RESPER. Due to this property, permuted KFDD can provide a more compact circuit realization in the multilevel circuit. The circuit obtained can be realized directly with FPGAs like AT 6000 series from Atmel. This algorithm is implemented on several MCNC benchmarks, the results compared with previous programs, TECHMAP and REMIT, are very encouraging. The main achievement of this thesis is the creation of the algorithm which applies a permuted tree search method combined with Davio Expansion and generates Directed Acyclic Graph which is next mapped to a compact circuit realization.
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Shin, Eung Seo. "Automated Generation of Round-robin Arbitration and Crossbar Switch Logic." Diss., Available online, Georgia Institute of Technology, (2003), 2003. http://etd.gatech.edu/theses/available/etd-11232003-150424/.

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Roumeliotis, Emmanuel. "Multi-processor logic simulation at the chip level." Diss., Virginia Polytechnic Institute and State University, 1986. http://hdl.handle.net/10919/71180.

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This dissertation presents the design and development of a multi-processor logic simulator. After an introduction to parallel processing, the concept of distributed simulation is described as well as the possibility of deadlock in a distributed system. It is proven that the proposed system does not deadlock. Next, the modeling techniques are discussed along with the timing mechanisms used for logic simulation. A new approach, namely process oriented simulation is studied in depth. It is shown that modeling for this kind of simulation is more efficient regarding modeling ease, computer memory and simulation time, than existing simulation methods. The hardware design of the multi-processor system and the algorithms for synchronization and signal interchange between the processors are presented next. An algorithm for an efficient partitioning of the digital network to be simulated among the processors of the system is also described. Apart from the simulation of a single digital network, the simulator can also be used for fault simulation and design verification. Regarding fault simulation, the fault injection and fault detection techniques are presented. The experimental results obtained by running the multi-processor simulator are compared with the theoretical estimates as well as with results obtained by other multi-processor systems. The comparison shows that the proposed simulator exhibits the estimated performance. Finally, the design of a common bus interface is given. This interface will connect the processors of the system directly without the intervention of a hard disk which was used for the development and testing of the system.
Ph. D.
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Moon, Gyo Sik. "An Algorithm for the PLA Equivalence Problem." Thesis, University of North Texas, 1995. https://digital.library.unt.edu/ark:/67531/metadc278922/.

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The Programmable Logic Array (PLA) has been widely used in the design of VLSI circuits and systems because of its regularity, flexibility, and simplicity. The equivalence problem is typically to verify that the final description of a circuit is functionally equivalent to its initial description. Verifying the functional equivalence of two descriptions is equivalent to proving their logical equivalence. This problem of pure logic is essential to circuit design. The most widely used technique to solve the problem is based on Binary Decision Diagram or BDD, proposed by Bryant in 1986. Unfortunately, BDD requires too much time and space to represent moderately large circuits for equivalence testing. We design and implement a new algorithm called the Cover-Merge Algorithm for the equivalence problem based on a divide-and-conquer strategy using the concept of cover and a derivational method. We prove that the algorithm is sound and complete. Because of the NP-completeness of the problem, we emphasize simplifications to reduce the search space or to avoid redundant computations. Simplification techniques are incorporated into the algorithm as an essential part to speed up the the derivation process. Two different sets of heuristics are developed for two opposite goals: one for the proof of equivalence and the other for its disproof. Experiments on a large scale of data have shown that big speed-ups can be achieved by prioritizing the heuristics and by choosing the most favorable one at each iteration of the Algorithm. Results are compared with those for BDD on standard benchmark problems as well as on random PLAs to perform an unbiased way of testing algorithms. It has been shown that the Cover-Merge Algorithm outperforms BDD in nearly all problem instances in terms of time and space. The algorithm has demonstrated fairly stabilized and practical performances especially for big PLAs under a wide range of conditions, while BDD shows poor performance because of its memory greedy representation scheme without adequate simplification.
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Books on the topic "Logic circuits Design and construction"

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Logic circuit design. Fort Worth: Saunders Coll.Pub., 1993.

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Logic circuit design. Fort Worth: Saunders College Pub., 1993.

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Yarbrough, John M. Digital logic: Applications and design. Minneapolis/St. Paul: West Pub. Co., 1997.

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Sandige, Richard S. Modern digital design. New York: McGraw-Hill, 1990.

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Modern digital design. New York: McGraw-Hill, 1990.

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CMOS logic circuit design. Boston: Kluwer Academic Publishers, 1999.

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Uyemura, John P. CMOS logic circuit design. Boston: Kluwer Academic Publishers, 1999.

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Vingron, Shimon Peter. Logic circuit design: Selected methods. Heidelberg: Springer, 2012.

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Logic design for array-based circuits: A structured design methodology. San Diego: Academic Press, 1992.

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Rafiquzzaman, Mohamed. Fundamentals of digital logic and microcomputer design. San Dimas, Calif: Rafi Systems, Inc., 1998.

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Book chapters on the topic "Logic circuits Design and construction"

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Nixon, Mark S. "Logic Circuits." In Introductory Digital Design, 49–84. London: Macmillan Education UK, 1995. http://dx.doi.org/10.1007/978-1-349-13508-0_3.

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Lewin, D., and D. Protheroe. "Sequential circuits." In Design of Logic Systems, 200–251. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4899-6856-2_6.

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Uyemura, John P. "Static Logic Circuits." In Circuit Design for CMOS VLSI, 115–66. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3620-8_4.

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Baig, Hasan, and Jan Madsen. "Genetic Circuits Logic Analysis." In Genetic Design Automation, 61–80. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52355-8_5.

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Lewin, D., and D. Protheroe. "Design of combinational circuits." In Design of Logic Systems, 58–108. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4899-6856-2_3.

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Lewin, D., and D. Protheroe. "Design of asynchronous circuits." In Design of Logic Systems, 298–367. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4899-6856-2_8.

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LaMeres, Brock J. "Arithmetic Circuits." In Introduction to Logic Circuits & Logic Design with Verilog, 397–426. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-13605-5_12.

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LaMeres, Brock J. "Arithmetic Circuits." In Introduction to Logic Circuits & Logic Design with VHDL, 407–37. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-12489-2_12.

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LaMeres, Brock J. "Arithmetic Circuits." In Introduction to Logic Circuits & Logic Design with Verilog, 373–402. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-53883-9_12.

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LaMeres, Brock J. "Arithmetic Circuits." In Introduction to Logic Circuits & Logic Design with VHDL, 385–415. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-34195-8_12.

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Conference papers on the topic "Logic circuits Design and construction"

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Wilson, Ronald, Rabin Y. Acharya, Domenic Forte, Navid Asadizanjani, and Damon Woodard. "A Novel Approach to Unsupervised Automated Extraction of Standard Cell Library for Reverse Engineering and Hardware Assurance." In ISTFA 2019. ASM International, 2019. http://dx.doi.org/10.31399/asm.cp.istfa2019p0249.

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Abstract Reverse engineering today is supported by several tools, such as ICWorks, that assist in the processing and extraction of logic elements from high definition layer by layer images of integrated circuits. To the best of our knowledge, they all work under the assumption that the standard cell library used in the design process of the integrated circuit is available. However, in situations where reverse engineering is done on commercial off-the-shelf components, this information is not available thereby, rendering the assumption invalid. Until now, this problem has not been addressed. In this paper, we introduce a novel approach for the extraction of standard cell library using the contact layer from these images. The approach is completely automated and does not require any prior knowledge on the construction or layout of the target semiconductor integrated circuit. The performance of the approach is evaluated on two AES designs with 10,000 cells compiled from standard libraries with 32nm and 90nm node technologies having 350 and 340 standard cells respectively. We were able to successfully extract 94% and 60% of the standard cells from the 32nm and 90nm AES designs using the proposed approach. We also perform a case study using a realworld sample extracted from a smartcard. Finally, we also investigate the various challenges involved in the extraction of standard cells from images and the steps involved in resolving them.
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Vijayashree, R., P. ChellaPandi, K. Natesan, S. Jalaldeen, S. C. Chetal, and Baldev Raj. "Design and Development of Diverse Safety Rod and Its Drive Mechanism for PFBR." In 17th International Conference on Nuclear Engineering. ASMEDC, 2009. http://dx.doi.org/10.1115/icone17-75851.

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Prototype Fast Breeder Reactor (PFBR) is U-PuO2 fuelled sodium cooled Pool type Fast Reactor and it is currently under advanced stage of construction at Kalpakkam, India. The Fast Breeder Test Reactor (FBTR) which is the only fast reactor currently operational in India is having only one shutdown system. However the IAEA and Atomic Energy Regulatory Board (AERB) Guide Lines call for two independent fast acting diverse shutdown systems for the present generation reactors. Hence PFBR is equipped with two independent, fast acting and diverse shutdown systems. A shutdown system comprises of sensors, logic circuits, drive mechanisms and neutron absorbing rods. The two shutdown systems of PFBR are capable of bringing down the reactor to cold shutdown state independent of the other. The absorber rods of the second shutdown system of PFBR are called as Diverse Safety rods (DSR) and their drive mechanisms are called as Diverse Safety Rod Drive Mechanisms (DSRDM). DSR are normally parked above active core by DSRDM. On receiving scram signal, Electromagnet of DSRDM is de-energised and it facilitates fast shutdown of the reactor by dropping the DSR in to the active core. This paper presents chronological design and development of the prototype DSR and DSRDM starting from the design specifications. Salient design specifications for both DSRDM and DSR are listed initially. The conceptual & detailed design features are explained with the help of figures. Various important design options considered in the initial design stage, choice of final design along with brief explanation for the particular choice are also given for some of the important components. Details on material of construction are given at appropriate places. Details on various analysis such as large displacement analysis for buckling, bending analysis for determining reactive forces and friction in the mechanism, thermal stress analysis of electromagnet during scram, flow induced vibration analysis of DSRDM and DSR and hydraulic analysis for estimating the pressure drop and drop time of DSR are also given. Test plans for design verification, manufacturing and shop testing experience of prototype systems, and criteria for endurance testing in sodium for qualification of DSRDM and DSR for operation in reactor are also briefed.
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Vudadha, Chetan Kumar, and MB Srinivas. "Design Methodologies for Ternary Logic Circuits." In 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL). IEEE, 2018. http://dx.doi.org/10.1109/ismvl.2018.00041.

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Palit, Indranil, X. Sharon Hu, Joshep Nahas, and Michael Niemier. "Systematic Design of Nanomagnet Logic Circuits." In Design Automation and Test in Europe. New Jersey: IEEE Conference Publications, 2013. http://dx.doi.org/10.7873/date.2013.360.

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Mandal, Sarojini, Jayee Sinha, and Amlan Chakraborty. "Design of Memristor – CMOS based logic gates and logic circuits." In 2019 2nd International Conference on Innovations in Electronics, Signal Processing and Communication (IESC). IEEE, 2019. http://dx.doi.org/10.1109/iespc.2019.8902355.

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Baig, Hasan, and Jan Madsen. "Logic analysis and verification of n-input genetic logic circuits." In 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2017. http://dx.doi.org/10.23919/date.2017.7927070.

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Xiao, Ran, and Chunhong Chen. "Power optimization design for probabilistic logic circuits." In 2015 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2015. http://dx.doi.org/10.1109/iscas.2015.7169216.

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Das, Debaprasad, Anirban Banerjee, and Vikash Prasad. "Design of ternary logic circuits using CNTFET." In 2018 International Symposium on Devices, Circuits and Systems (ISDCS). IEEE, 2018. http://dx.doi.org/10.1109/isdcs.2018.8379661.

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Saidutt, P. Viswa, V. Srinivas, P. Sai Phaneendra, and N. Moorthy Muthukrishnan. "Design of encoder for ternary logic circuits." In 2012 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PRIMEASIA). IEEE, 2012. http://dx.doi.org/10.1109/primeasia.2012.6458632.

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Marks, Renan A., Daniel K. S. Vieira, Marcos V. Guterres, Poliana A. C. Oliveira, and Omar P. Vilela Neto. "DNAr-logic." In Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design. New York, New York, USA: ACM Press, 2019. http://dx.doi.org/10.1145/3338852.3339854.

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Reports on the topic "Logic circuits Design and construction"

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Onneweer, Siep, Hans Kerkhoff, and Jon Butler. Structural Computer-Aided Design of Current-Mode CMOS Logic Circuits. Fort Belvoir, VA: Defense Technical Information Center, January 1988. http://dx.doi.org/10.21236/ada608071.

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Richter, Schachar E. Construction and Operation of Three-Dimensional Memory and Logic Molecular Devices and Circuits. Fort Belvoir, VA: Defense Technical Information Center, July 2013. http://dx.doi.org/10.21236/ada587368.

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Lala, P. K., and H. L. Martin. Application of Error Correcting Codes in Fault-Tolerant Logic Design for VLSI Circuits. Fort Belvoir, VA: Defense Technical Information Center, May 1990. http://dx.doi.org/10.21236/ada228840.

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Schueller, Kriss A., and Jon T. Butler. Complexity Analysis of the Cost-Table Approach to the Design of Multiple-Valued Logic Circuits. Fort Belvoir, VA: Defense Technical Information Center, October 1995. http://dx.doi.org/10.21236/ada605390.

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