Journal articles: 'Logic circuits Design and construction'

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Avdeev, N. A., and P. N. Bibilo. "Design of Digital Operational Units with Low Power Consumption." Programmnaya Ingeneria 12, no. 2 (March 16, 2021): 63–73. http://dx.doi.org/10.17587/prin.12.63-73.

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The lowering of power consumption in CMOS VLSI digital systems is one of the most important problems that appear now for developers of CAD systems. One of the effective approaches to lowering the dynamic power consumption is creation of an algorithmic description of the VHDL project, which provides for the deactivation of some functional blocks which are not necessary in particular moments. Contemporary synthesizers fulfill the high level synthesis of logic circuits by substitution of description of each VHDL construction with functionally structural description of a proper logic subcircuit. The results of digital logic circuit synthesis (the number of logic elements and power consumption) depend significantly on initial VHDL code. During initial VHDL code development it is possible to use different approaches to improve some parameters of synthesized logic circuit. At the algorithmic level of the digital design, it is necessary to provide for disconnection of the units, which cause the higher power consumption. In this paper such methods of algorithmic VHDL description of logic circuit are studied. The efficiency of the proposed methods is compared with the traditional method of VHDL-description which does not take the aspect of power consumption into account and is oriented only to the correct functionality of the developed logic circuit. To estimate the power consumption of logic circuits the approach is used which allows applying high-speed logical VHDL-simulation of structural descriptions (netlists) of logic circuits instead of slow SPICE simulation. The main conclusion of the provided study is the following: the clock gating and the storage of operand values for complex operations as well as zero value setting for simple ones are effective methods for the VHDL description of operational units with low power consumption implemented in the CMOS basis.

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Maity, Heranmoy, Sudipta Banerjee, Arindam Biswas, Anita Pal, and Anup Kumar Bhattacharjee. "Design of Reversible Shift Register Using Reduced Number of Logic Gates." Micro and Nanosystems 12, no. 1 (January 21, 2020): 33–37. http://dx.doi.org/10.2174/1876402911666190617112734.

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Background: Over the last few decades, reversible logic system/circuits have received considerable attention in the diversified fields such as nanotechnology, quantum computing, cryptography, optical computing and low power design of VLSI circuits due to their low power dissipation characteristics. Methods: In this paper, we proposed the design of reversible shift register (SR) i.e. serial-in-serial out (SISO), serial-in-parallel out (SIPO), parallel-in-serial out (PISO) and parallel-in-parallel out (PIPO) SR using a reduced number of reversible logic gates and garbage output. Results: As compared to previously reported results, the improvement in our proposed model of SISO, SIPO, PISO and PIPO was found to be 50 – 66.66 %, 42.85 – 66.66 %, 12.5 – 53.33 % and 50 – 66.66 % respectively, in terms of the number of reversible logic gates.

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Jóźwiak, Lech. "General Decomposition and Its Use in Digital Circuit Synthesis." VLSI Design 3, no. 3-4 (January 1, 1995): 225–48. http://dx.doi.org/10.1155/1995/16259.

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Modem microelectronic technology.gives opportunities to build digital circuits of huge complexity and provides a wide diversity of logic building blocks. Although logic designers have been building circuits for many years, they have realized that advances in microelectronic technology are outstripping their abilities to make use of the created opportunities. In this paper, we present the fundamentals of a logic design methodology which meets the requirements of today's complex circuits and modem building blocks. The methodology is based on the theory of general full-decompositions which constitutes the theory of digital circuit structures at the highest abstraction level. The paper explains the theory and shows how it can be used for digital circuit synthesis. The decomposition methodology that is presented ensures “correctness by construction” and enables very effective and efficient post-factum validation. It makes possible extensive examination of the structural features of the required information processing in relation to a given set of objectives and constraints.

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Abdulnabi, Saif, and Mohammed Abbas. "Design an All-Optical Combinational Logic Circuits Based on Nano-Ring Insulator-Metal-Insulator Plasmonic Waveguides." Photonics 6, no. 1 (March 19, 2019): 30. http://dx.doi.org/10.3390/photonics6010030.

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In this paper, we propose, analyze and simulate a new configuration to simulate all-optical combinational logic functions based on Nano-rings insulator-metal-insulator (IMI) plasmonic waveguides. We used Finite Element Method (FEM) to analyze the proposed plasmonic combinational logic functions. The analyzed combinational logic functions are Half-Adder, Full-Adder, Half-Subtractor, and Comparator One-Bit. The operation principle of these combinational logic functions is based on the constructive and destructive interferences between the input signal(s) and control signal. Numerical simulations show that a transmission threshold exists (0.25) which allows all proposed four plasmonic combinational logic functions to be achieved in one structure. As a result, the transmission threshold value measures the performance of the proposed plasmonic combinational logic functions. We use the same structure with the same dimensions at 1550 nm wavelength for all proposed plasmonic combinational logic functions. The proposed all-optical combinational logic functions structure contributes significantly to photonic integrated circuits construction and all-optical signal processing nano-circuits.

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Zaitseva, Elena, Vitaly Levashenko, Igor Lukyanchuk, Jan Rabcan, Miroslav Kvassay, and Patrik Rusnak. "Application of Generalized Reed–Muller Expression for Development of Non-Binary Circuits." Electronics 9, no. 1 (December 21, 2019): 12. http://dx.doi.org/10.3390/electronics9010012.

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Semiconductor devices and binary information technology reach their limits set by the atomic size of miniaturization, calculation speed, and the fundamental principle of energy dissipation per bit processing. Therefore, new technologies in logic design and mathematical approaches must be investigated. Application of multiple-valued logic (MVL) in logic design allows developing gates and circuits with more than two stable states. This enables packing an unprecedented high-density of information. Based on this idea, a new technique of the programmable logic arrays (PLA) construction based on MVL units is considered. The unique aspect of this technique is the application of recurrent generalized Reed–Muller expression (GRME) for MVL function representation. The recurrent procedure for this expression’s construction is considered and applied in the PLA development. The proposed structure of PLA consists of two blocks that are memory and logic block. In this paper, we also consider the possibility to use the ferroelectrics for the implementation of cells of the memory block of PLA. The development of gates with multi-stable states is possible by the ferroelectrics ability to pin the polarization as a sequence of stable states.

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Melnyk, Oleksandr, and Viktoriia Kozarevych. "SIMULATION OF PROGRAMMABLE SINGLE-ELECTRON NANOCIRCUITS." Bulletin of the National Technical University "KhPI". Series: Mathematical modeling in engineering and technologies, no. 1 (March 5, 2021): 64–68. http://dx.doi.org/10.20998/2222-0631.2020.01.05.

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The speed and specializations of large-scale integrated circuits always contradict their versatility, which expands their range and causes the rise in price of electronic devices. It is possible to eliminate the contradictions between universality and specialization by developing programmable nanoelectronic devices, the algorithms of which are changed at the request of computer hardware developers, i.e. by creating arithmetic circuits with programmable characteristics. The development of issues of theory and practice of the majority principle is now an urgent problem, since the nanoelectronic execution of computer systems with programmable structures will significantly reduce their cost and significantly simplify the design stage of automated systems. Today there is an important problem of developing principles for building reliable computer equipment. The use of mathematical and circuit modeling along with computer-aided design systems (CAD) can significantly increase the reliability of the designed devices. The authors prove the advantages of creating programmable nanodevices to overcome the physical limitations of micro-rominiatization. This continuity contributes to the accelerated introduction of mathematical modeling based on programmable nanoelectronics devices. The simulation and computer-aided design of reliable programmable nanoelectronic devices based on the technology of quantum automata is described. While constructing single-electron nanocircuits of combinational and sequential types the theory of majority logic is used. The order of construction and programming of various types of arithmetic-logic units is analyzed.

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Waheed, Sajjad, Sharmin Aktar, and Ali Newaz Bahar. "A Novel Design and Implementation of New Double Feynman and Six-correction logic (DFSCL) gates in Quantum-dot Cellular Automata (QCA)." European Scientific Journal, ESJ 13, no. 15 (May 31, 2017): 265. http://dx.doi.org/10.19044/esj.2017.v13n15p265.

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In recent years, quantum cellular automata (QCA) have been used widely to digital circuits and systems. QCA technology is a promising alternative to CMOS technology. It is attractive due to its fast speed, small area and low power consumption. The QCA offers a novel electronics paradigm for information processing and communication. It has the potential for attractive features such as faster speed, higher scale integration, higher switching frequency, smaller size and low power consumption than transistor based technology. In this paper, Double Feynman and Six-correction logic gate (DFSCL) is proposed based on QCA logic gates: MV gate and Inverter gate. The proposed circuit is a promising future in constructing of nano-scale low power consumption information processing system and can stimulate higher digital applications in QCA.

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Jóźwiak, Lech, Aleksander Ślusarczyk, and Marek Perkowski. "Term Trees in Application to an Effective and Efficient ATPG for AND–EXOR and AND–OR Circuits." VLSI Design 14, no. 1 (January 1, 2002): 107–22. http://dx.doi.org/10.1080/10655140290009837.

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A compact data representation, in which the typically required operations are performed rapidly, and effective and efficient algorithms that work on these representations are the essential elements of a successful CAD tool. The objective of this paper is to present a new data representation—term trees (TTs)—and to discuss its application for an effective and efficient structural automatic test-pattern generation (ATPG). Term trees are decision diagrams similar to BDDs that are particularly suitable for structure representation of AND–OR and AND–EXOR circuits. In the paper, a flexible algorithm for minimum term-tree construction is discussed and an effective and efficient algorithm for ATPG for AND–EXOR and AND–OR circuits is proposed. The term trees can be used for many other purposes in logic design and in other areas—for all purposes where compact representation and efficient manipulation of term sets is important. The presented experimental results show that term trees are indeed a compact data representation allowing fast manipulations. They form a good base for algorithms considering the function's and circuit's term structures.

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Mozyrsky, Dima, Vladimir Privman, and Steven P. Hotaling. "Design of Gates for Quantum Computation: The NOT Gate." International Journal of Modern Physics B 11, no. 18 (July 20, 1997): 2207–15. http://dx.doi.org/10.1142/s0217979297001143.

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We offer an alternative to the conventional network formulation of quantum computing. We advance the analog approach to quantum logic gate/circuit construction. As an illustration, we consider the spatially extended NOT gate as the first step in the development of this approach. We derive an explicit form of the interaction Hamiltonian corresponding to this gate and analyze its properties. We also discuss general extensions to the case of certain time-dependent interactions which may be useful for practical realization of quantum logic gates.

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Атамась, Артем Іванович, Ірина Андріївна Сліпухіна, Ігор Станіславович Чернецький, and Юрій Сергійович Шиховцев. "IMPLEMENTATION OF THE EQUIVALENT CIRCUIT METHOD IN INSTRUMENTAL DIGITAL DIDACTICS." Information Technologies and Learning Tools 82, no. 2 (April 25, 2021): 1–17. http://dx.doi.org/10.33407/itlt.v82i2.4069.

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Instrumental digital didactics is based on the use of various digital means of obtaining, processing, and interpreting empirical data in accordance with the logic of scientific method and engineering design. Appropriate teaching techniques reflect the STEM approach to teaching natural science and engineering subjects. The use of the equivalent circuit created on the NI Multisim platform to investigate the characteristics of electric circuits’ components creates favorable didactic conditions. The methodological approaches proposed by the authors are demonstrated by the examples of determining the parameters of technologically advanced devices - photoelectric converter (for example, determining its maximum power point, as well as Fill Factor) and supercapacitor (for example, designating changes in charging and discharging characteristics depending on the type of construction). In such educational projects the parameters of the circuit components obtained by the equivalent circuit method are compared with the specifications of commercial devices available on the market. This approach, on the one hand, demonstrates statistical errors of results to the students, and on the other hand, it is a source of sufficient data for constructing an equivalent circuit of devices without prior experimental research. It is shown that the use of equivalent circuits in a computer simulation environment to replace real electronic and electrical devices, measuring systems and equipment with their virtual counterparts expands the didactic possibilities. Techniques based on the versatile use of digital didactic tools are being actively developed and implemented in the MANLab STEM-laboratory of the National Centre “Junior Academy of Sciences of Ukraine”.

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Le Guernic, Paul, Jean-Pierre Talpin, and Jean-Christophe Le Lann. "POLYCHRONY for System Design." Journal of Circuits, Systems and Computers 12, no. 03 (June 2003): 261–303. http://dx.doi.org/10.1142/s0218126603000763.

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Rising complexities and performances of integrated circuits and systems, shortening time-to-market demands for electronic equipments, growing installed bases of intellectual property (IP), requirements for adapting existing IP blocks with new services, all stress high-level design as a prominent research topic and call for the development of appropriate methodological solutions. In this aim, system design based on the so-called "synchronous hypothesis" consists of abstracting the nonfunctional implementation details of a system and lets one benefit from a focused reasoning on the logics behind the instants at which the system functionalities should be secured. With this point of view, synchronous design models and languages provide intuitive (ontological) models for integrated circuits. This affinity explains the ease of generating synchronous circuits and verify their functionalities using compilers and related tools that implement this approach. In the relational mathematical model behind the design language SIGNAL, this affinity goes beyond the domain of purely synchronous circuits, and embraces the context of complex architectures consisting of synchronous circuits and desynchronization protocols: globally asynchronous and locally synchronous architectures (GALS). The unique features of the relational model behind SIGNAL are to provide the notion of polychrony: the capability to describe circuits and systems with several clocks; and to support refinement: the ability to assist and support system design from the early stages of requirement specification, to the later stages of synthesis and deployment. The SIGNAL model provides a design methodology that forms a continuum from synchrony to asynchrony, from specification to implementation, from abstraction to concretization, from interfaces to implementations. SIGNAL gives the opportunity to seamlessly model circuits and devices at multiple levels of abstractions, by implementing mechanisms found in many hardware simulators, while reasoning within a simple and formally defined mathematical model. In the same manner, the flexibility inherent to the abstract notion of signal, handled in the synchronous-desynchronized design model of SIGNAL, invites and favors the design of correct by construction systems by means of well-defined transformations of system specifications (morphisms) that preserve the intended semantics and stated properties of the architecture under design. The aim of the present article is to review and summarize these formal, correct-by-construction, design transformations. Most of them are implemented in the POLYCHRONY tool-set, allowing for a mixed bottom–up and top–down design of an embedded hardware–software system using the SIGNAL design language.

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Beneš, David, Petr Sosík, and Alfonso Rodríguez-Patón. "An Autonomous In Vivo Dual Selection Protocol for Boolean Genetic Circuits." Artificial Life 21, no. 2 (May 2015): 247–60. http://dx.doi.org/10.1162/artl_a_00160.

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Success in synthetic biology depends on the efficient construction of robust genetic circuitry. However, even the direct engineering of the simplest genetic elements (switches, logic gates) is a challenge and involves intense lab work. As the complexity of biological circuits grows, it becomes more complicated and less fruitful to rely on the rational design paradigm, because it demands many time-consuming trial-and-error cycles. One of the reasons is the context-dependent behavior of small assembly parts (like BioBricks), which in a complex environment often interact in an unpredictable way. Therefore, the idea of evolutionary engineering (artificial directed in vivo evolution) based on screening and selection of randomized combinatorial genetic circuit libraries became popular. In this article we build on the so-called dual selection technique. We propose a plasmid-based framework using toxin-antitoxin pairs together with the relaxase conjugative protein, enabling an efficient autonomous in vivo evolutionary selection of simple Boolean circuits in bacteria (E. coli was chosen for demonstration). Unlike previously reported protocols, both on and off selection steps can run simultaneously in various cells in the same environment without human intervention; and good circuits not only survive the selection process but are also horizontally transferred by conjugation to the neighbor cells to accelerate the convergence rate of the selection process. Our directed evolution strategy combines a new dual selection method with fluorescence-based screening to increase the robustness of the technique against mutations. As there are more orthogonal toxin-antitoxin pairs in E. coli, the approach is likely to be scalable to more complex functions. In silico experiments based on empirical data confirm the high search and selection capability of the protocol.

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Misra, Neeraj Kumar, Bibhash Sen, Subodh Wairya, and Bandan Bhoi. "Testable Novel Parity-Preserving Reversible Gate and Low-Cost Quantum Decoder Design in 1D Molecular-QCA." Journal of Circuits, Systems and Computers 26, no. 09 (April 24, 2017): 1750145. http://dx.doi.org/10.1142/s0218126617501456.

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In this era of emerging technology, reversible logic is applied for circuit design. Due to the deep submicron and scaling, a number of pitfalls are faced by the CMOS technology. So a lot of constraints related to CMOS are stated with the QCA technology. The aim of this paper is the efficient conservative reversible decoder circuit design with optimal reversible metrics. It aims at furnishing a proposed DC gate (DC stands for decoder comparator) to help the construction of these mentioned circuits. Finally, the DC is employed to construct the [Formula: see text]-bit reversible decoder. Moreover, a new concept of the quantum equivalent of combined reversible gates is presented by the algorithm. By the comparative outcomes, it is found that the proposed decoder had achieved 25% quantum cost, 66% gate count, and 50% garbage outputs as compared to the counterpart. Further, stuck-at-fault for the single- and multiple-bit input and output is applied to the DC gate for testability. Moreover, the DC gate in the physical foreground on QCADesigner achieved 0.63 μm2 area, 15 majority voter gates, and 451 cell complexities. It is observed that nanoelectronics has also made an inevitable contribution in the area of QCA.

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Saha, Aloke, Rahul Pal, and Jayanta Ghosh. "Novel Self-Pipelining Approach for Speed-Power Efficient Reliable Binary Multiplication." Micro and Nanosystems 12, no. 3 (December 1, 2020): 149–58. http://dx.doi.org/10.2174/1876402911666190916155445.

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Background: The present study explores a novel self-pipelining strategy that can enhance speed-power efficiency as well as the reliability of a binary multiplier as compared to state-of-art register and wavepipelining. Method: Proper synchronization with efficient clocking between the subsequent self-pipelining stages has been assured to design a self-pipelined multiplier. Each self-pipelining stage consists of self-latching leaf cells that are designed, optimized and evaluated by TSMC 0.18μm CMOS technology with 1.8V supply rail and at 25°C temperature. The T-Spice transient response and simulated results for the designed circuits are presented. The proposed idea has been applied to design 4-b×4-b self-pipelined Wallace- tree multiplier. The multiplier was validated for all possible test patterns and the transient response was evaluated. The circuit performance in terms of propagation delay, average power and Power-Delay- Product (PDP) is recorded. Next, the decomposition logic is applied to design a higher-order multiplier (i.e., 8-bit×8-bit and 16-bit×16-bit) based on the proposed strategy using 4-bit×4-bit self-pipelined multiplier. The designed multiplier was also validated through extensive TSpice simulation for all the required test patterns using W-Edit and the evaluated performance is presented. All the designs, optimizations and evaluations performed are based on BSIM3 device parameter of TSMC 0.18μm CMOS technology with 1.8V supply rail at 25°C temperature using S-Edit of Tanner EDA. Results: The reliability was investigated of the proposed 4-b×4-b multiplier in the temperature range - 40°C to 100°C for maximum PDP variation. Conclusion: A benchmarking analysis in terms of speed-power performance with recent competitive design reveals preeminence of the proposed technique.

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Lefebvre, Martin, and Cliff Liem. "Cell Generator-Based Technology Mapping by Constructive Tree-Matching and Dynamic Covering." VLSI Design 3, no. 1 (January 1, 1995): 1–12. http://dx.doi.org/10.1155/1995/18576.

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Technology mapping is the final step of logic synthesis which consists of mapping an optimized technology independent logic network representation into a circuit realization in a given technology. An important component of the technology mapping problem is the identification of feasible library cells for the realization of the logic operators in the logic tree. There are two main classes of such matching algorithms. Library-based matching algorithms [1–4] require that all available physical components be represented explicitly in a pattern library. Sections of the logic network are then matched against this pattern list for the identification of suitable components. In contrast, cell generator-based matching techniques [6–8] accept feasibility constraints on the complexity and quantity of physical components according to limits imposed by the target technology or the capabilities of the cell generator. Hence, individual patterns are not stored in a library and are instead generated as needed. In this paper, we present a new cell generator-based constructive matching algorithm. Because the algorithm builds matched patterns incrementally, very large cell families can be accommodated using time and space resources that are proportional to the size of the largest feasible cell pattern and not the size of the library of patterns as would be the case for library-based approaches. Also, whereas existing cell generator-based matching techniques combine the tasks of matching (identification) and covering (selection), constructive matching provides more flexibility by not restricting the covering phase. Empirical results demonstrate the increased quality of the technology-mapped circuits when larger cells are available.

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Venturi, Margherita, Vincenzo Balzani, Roberto Ballardini, Alberto Credi, and M. Teresa Gandolfi. "Towards molecular photochemionics." International Journal of Photoenergy 6, no. 1 (2004): 1–10. http://dx.doi.org/10.1155/s1110662x04000017.

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In the last few years there has been a great interest in developing electronics at a molecular level (molecular electronics), e.g. to construct miniaturized electric circuits that would be much smaller than the corresponding micron-scale digital logic circuits fabricated on conventional solid-state semiconductor chips. An alternative possibility to the use of electron fluxes as a means for information processing (electronics) is that of using optical beams (photonics), but up until now scarce attention has been devoted to the possibility of developing photonics at the molecular level. In this paper we review some recent achievements in the design and construction of molecular-level systems that are capable of transferring, switching, collecting, storing, and elaborating light signals. The combination of molecular photonics with chemionics can lead to a wealth of molecular-level devices capable of information processing.

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Haghparast, Majid, and Ali Bolhassani. "Optimized parity preserving quantum reversible full adder/subtractor." International Journal of Quantum Information 14, no. 03 (April 2016): 1650019. http://dx.doi.org/10.1142/s0219749916500192.

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Reversible logic is one of the indispensable aspects of emerging technologies for reducing physical entropy gain, since reversible circuits do not lose information in the form of internal heat during computation. This paper aimed to initiate constructing parity preserving reversible circuits. A novel parity preserving reversible block, HB is presented. Then a new design of a cost-effective parity preserving reversible full adder/subtractor (PPFA/S) is proposed. Next, we suggested a new parity preserving binary to BCD converter. Finally, we proposed new realization of parity preserving reversible BCD adder. The proposed designs are cost-effective in terms of quantum cost and delay. All the scales are in the NANO-metric area.

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Barger, Natalia, Phyana Litovco, Ximing Li, Mouna Habib, and Ramez Daniel. "Synthetic metabolic computation in a bioluminescence-sensing system." Nucleic Acids Research 47, no. 19 (September 23, 2019): 10464–74. http://dx.doi.org/10.1093/nar/gkz807.

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Abstract Bioluminescence is visible light produced and emitted by living cells using various biological systems (e.g. luxCDABE cassette). Today, this phenomenon is widely exploited in biological research, biotechnology and medical applications as a quantitative technique for the detection of biological signals. However, this technique has mostly been used to detect a single input only. In this work, we re-engineered the complex genetic structure of luxCDABE cassette to build a biological unit that can detect multi-inputs, process the cellular information and report the computation results. We first split the luxCDABE operon into several parts to create a genetic circuit that can compute a soft minimum in living cells. Then, we used the new design to implement an AND logic function with better performance as compared to AND logic functions based on protein-protein interactions. Furthermore, by controlling the reverse reaction of the luxCDABE cassette independently from the forward reaction, we built a comparator with a programmable detection threshold. Finally, we applied the redesigned cassette to build an incoherent feedforward loop that reduced the unwanted crosstalk between stress-responsive promoters (recA, katG). This work demonstrates the construction of genetic circuits that combine regulations of gene expression with metabolic pathways, for sensing and computing in living cells.

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Perkowski, Marek A., Malgorzata Chrzanowska-Jeske, Andisheh Sarabi, and Ingo Schäfer. "Multi-Level Logic Synthesis Based on Kronecker Decision Diagrams and Boolean Ternary Decision Diagrams for Incompletely Specified Functions." VLSI Design 3, no. 3-4 (January 1, 1995): 301–13. http://dx.doi.org/10.1155/1995/24594.

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This paper introduces several new families of decision diagrams for multi-output Boolean functions. The introduced families include several diagrams known from literature (BDDs, FDDs) as subsets. Due to this property, these diagrams can provide a more compact representation of functions than either of the two decision diagrams. Kronecker Decision Diagrams (KDDs) with negated edges are based on three orthogonal expansions (Shannon, Positive Davio, Negative Davio) and are created here for incompletely specified Boolean functions as well. An improved efficient algorithm for the construction of KDD is presented and applied in a mapping program to ATMEL 6000 fine-grain FPGAs. Four other new families of functional decision diagrams are also presented: Pseudo KDDs, Free KDDs, Boolean Ternary DDs, and Boolean Kronecker Ternary DDs. The last two families introduce nodes with three edges and require AND, OR and EXOR gates for circuit realization. There are two variants of each of the last two families: canonical and non-canonical. While the canonical diagrams can be used as efficient general-purpose Boolean function representations, the non-canonical variants are also applicable to incompletely specified functions and create don't cares in the process of the creation of the diagram.. They lead to even more compact circuits in logic synthesis and technology mapping.

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Maity, Heranmoy, Arindam Biswas, Arup K. Bhattacharjee, and Anita Pal. "The Quantum Cost Optimized Design of 2:4 Decoder Using the New Reversible Logic Block." Micro and Nanosystems 12, no. 3 (December 1, 2020): 146–48. http://dx.doi.org/10.2174/2213476x06666190916141330.

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Aim and Objective: This paper presents the quantum cost, garbage output, constant input and number of reversible gate optimized 2:4 decoder using 4×4 new reversible logic gate which is named as reversible decoder block or RD block. Method: The proposed block is implemented with a quantum circuit and quantum cost of the proposed RD block is 8. The proposed decoder can be designed using only one new proposed block. Results and Conclusion: The quantum cost, garbage output, constant input and gate number of the proposed 2:4 decoder is 9, 0, 2 and 1 which is better w.r.t previously reported work. The improvement % of quantum cost, garbage output, constant input and number of gates are 12.5 – 77.148 %, 100 %, 33.33 – 75 % and 0 – 85.71%.

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Boeing, Philipp, Miriam Leon, Darren Nesbeth, Anthony Finkelstein, and Chris Barnes. "Towards an Aspect-Oriented Design and Modelling Framework for Synthetic Biology." Processes 6, no. 9 (September 15, 2018): 167. http://dx.doi.org/10.3390/pr6090167.

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Work on synthetic biology has largely used a component-based metaphor for system construction. While this paradigm has been successful for the construction of numerous systems, the incorporation of contextual design issues—either compositional, host or environmental—will be key to realising more complex applications. Here, we present a design framework that radically steps away from a purely parts-based paradigm by using aspect-oriented software engineering concepts. We believe that the notion of concerns is a powerful and biologically credible way of thinking about system synthesis. By adopting this approach, we can separate core concerns, which represent modular aims of the design, from cross-cutting concerns, which represent system-wide attributes. The explicit handling of cross-cutting concerns allows for contextual information to enter the design process in a modular way. As a proof-of-principle, we implemented the aspect-oriented approach in the Python tool, SynBioWeaver, which enables the combination, or weaving, of core and cross-cutting concerns. The power and flexibility of this framework is demonstrated through a number of examples covering the inclusion of part context, combining circuit designs in a context dependent manner, and the generation of rule, logic and reaction models from synthetic circuit designs.

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Yu, Hsing Cheng, Chih Chiang Wang, Chau Shin Jang, Wen Yang Peng, and T. S. Liu. "Blowers of Vacuum Cleaners Utilizing Coreless and Sensorless Axial-Flux Motors with Edge-Wire Coils." Applied Mechanics and Materials 284-287 (January 2013): 1770–77. http://dx.doi.org/10.4028/www.scientific.net/amm.284-287.1770.

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Axial-flux motors (AFM) generally have higher torque and power densities, smaller volume and weight, larger diameter to length ratio, and compact construction for the same power level than radial-flux motors (RFM). Hence, AFM are attractive alternative to conventional RFM for applying in low torque and speed servo control systems. Additionally, magnetic Hall-effect sensors and commutation circuits are unsuitable for environment with high temperature and restricted space, so sensorless driving control method of AFM by detecting zero-crossing of back-EMF signals has been achieved. Furthermore, coreless design can reduce motor total weight, normal attractive force and torque pulsation and can increase efficiency of machines as compared with conventional design with cores. Thus, this study focuses on sensorless AFM design applying for blowers in vacuum cleaners to follow the concepts of axial-flux, edge-wire with high space-utilization factors, and stators without ferromagnetic cores. The closed-loop velocity controller designs by adopting proportional-integral-derivative (PID) and fuzzy logic control (FLC) algorithms have been demonstrated effectively for the design sensorless AFM of blowers in vacuum cleaners. As a result, the settling time of velocity closed-loop control methods can be converged within 1.0 second; i.e. the vacuum cleaners can switch and operate in various speeds with different operational environment rapidly. Therefore, the system characteristics and lifetime of the designed sensorless AFM have been enhanced and satisfied the demands of blowers to employ in vacuum cleaners.

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Perovic, S., E. H. Higham, and P. J. Unsworth. "Fault detection and flow regime identification based on analysis of signal noise from electromagnetic flowmeters." Proceedings of the Institution of Mechanical Engineers, Part E: Journal of Process Mechanical Engineering 215, no. 4 (November 1, 2001): 283–94. http://dx.doi.org/10.1177/095440890121500403.

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The signal conditioning and processing circuits of conventional electromagnetic flowmeters have been designed to provide an accurate average flowrate measurement signal, principally for the purpose of process control. One consequence of this is that the ‘noise’ and other low frequency components of the electrode signal are suppressed. Hitherto, the possibility that they may carry potentially useful information has been overlooked, but there are studies which show that information regarding the flow regime can be identified by spectral analysis of the higher frequency or ‘noise’ components of the sensor signals from some other types of flowmeters. If the entire electrode signal is analysed, using well-established signal analysis methods, diagnostic information regarding the flow regime in which the flowmeter is operating can be recovered and several distinctly different flow regimes can be identified, such as increased turbulence, swirling flow, flow pulsations and two-phase flow, all of which adversely affect the performance of the flowmeter. This paper presents the results of laboratory simulations of these flow regimes and describes a fuzzy logic method for identifying them. It also suggests a change to the conventional mode of operation and signal processing which would enable the additional functions to be implemented without involving any modification to the design or construction of the conventional flowtube. The potential benefits which arise from its application include the identification of flow regimes which adversely affect the performance of the flowmeter in its installed position and the ability to verify, on line, that the flowmeter is functioning correctly.

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Pfänder, O. A., H. J. Pfleiderer, and S. W. Lachowicz. "Configurable multiplier modules for an adaptive computing system." Advances in Radio Science 4 (September 6, 2006): 231–36. http://dx.doi.org/10.5194/ars-4-231-2006.

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Abstract. The importance of reconfigurable hardware is increasing steadily. For example, the primary approach of using adaptive systems based on programmable gate arrays and configurable routing resources has gone mainstream and high-performance programmable logic devices are rivaling traditional application-specific hardwired integrated circuits. Also, the idea of moving from the 2-D domain into a 3-D design which stacks several active layers above each other is gaining momentum in research and industry, to cope with the demand for smaller devices with a higher scale of integration. However, optimized arithmetic blocks in course-grain reconfigurable arrays as well as field-programmable architectures still play an important role. In countless digital systems and signal processing applications, the multiplication is one of the critical challenges, where in many cases a trade-off between area usage and data throughput has to be made. But the a priori choice of word-length and number representation can also be replaced by a dynamic choice at run-time, in order to improve flexibility, area efficiency and the level of parallelism in computation. In this contribution, we look at an adaptive computing system called 3-D-SoftChip to point out what parameters are crucial to implement flexible multiplier blocks into optimized elements for accelerated processing. The 3-D-SoftChip architecture uses a novel approach to 3-dimensional integration based on flip-chip bonding with indium bumps. The modular construction, the introduction of interfaces to realize the exchange of intermediate data, and the reconfigurable sign handling approach will be explained, as well as a beneficial way to handle and distribute the numerous required control signals.

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Guerrero-Rivera, Ruben, Abigail Morrison, Markus Diesmann, and Tim C. Pearce. "Programmable Logic Construction Kits for Hyper-Real-Time Neuronal Modeling." Neural Computation 18, no. 11 (November 2006): 2651–79. http://dx.doi.org/10.1162/neco.2006.18.11.2651.

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Programmable logic designs are presented that achieve exact integration of leaky integrate-and-fire soma and dynamical synapse neuronal models and incorporate spike-time dependent plasticity and axonal delays. Highly accurate numerical performance has been achieved by modifying simpler forward-Euler-based circuitry requiring minimal circuit allocation, which, as we show, behaves equivalently to exact integration. These designs have been implemented and simulated at the behavioral and physical device levels, demonstrating close agreement with both numerical and analytical results. By exploiting finely grained parallelism and single clock cycle numerical iteration, these designs achieve simulation speeds at least five orders of magnitude faster than the nervous system, termed here hyper-real-time operation, when deployed on commercially available field-programmable gate array (FPGA) devices. Taken together, our designs form a programmable logic construction kit of commonly used neuronal model elements that supports the building of large and complex architectures of spiking neuron networks for real-time neuromorphic implementation, neurophysiological interfacing, or efficient parameter space investigations.

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26

Taylor, G. E. "Design of Testable Logic Circuits." IEE Proceedings G (Electronic Circuits and Systems) 132, no. 3 (1985): 112. http://dx.doi.org/10.1049/ip-g-1.1985.0025.

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27

Bottorff, P. S. "Design of testable logic circuits." Proceedings of the IEEE 74, no. 1 (1986): 235. http://dx.doi.org/10.1109/proc.1986.13449.

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28

Williams, T. W. "Design of testable logic circuits." Proceedings of the IEEE 74, no. 3 (1986): 525. http://dx.doi.org/10.1109/proc.1986.13499.

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29

MacGugan, Douglas C., Eric C. Abbott, and J. Chris Milne. "230°C Accelerometer with Digitized Output for Directional Drilling." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000298–304. http://dx.doi.org/10.4071/hitec-tha14.

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Measurement-While-Drilling (MWD) technology for oil and gas, and geothermal directional drilling exploration is pushing into ever higher temperature environments - beyond 200°C. Orientation sensors supporting these high temperature environments need to provide highly accurate elevation and tool face measurements on the order of 0.1°. Honeywell has developed a new digital high temperature down-hole accelerometer, DHTA230, capable of providing the required accuracy at the elevated temperatures of 230°C, in the rugged MWD shock and vibration environment, with expected excellent reliability and life. The DHTA230 is designed for use in the downhole environment, but is based upon a mature Honeywell accelerometer using dual vibrating beam sensing elements. These sensing elements are configured as double-ended-tuning-forks in a push-pull orientation attached onto a pendulous proof mass. This push-pull configuration provides an acceleration signal proportional to the frequency difference of the vibrating beams, an easily captured digital signal through measurement of the two vibrating beam phases. The digitized accelerometer eliminates the need for A/D electronics in the high temperature drilling environment. The DHTA230 is 0.79” in diameter with a depth of .393” at the mount flange. The ruggedized configuration of the DHTA230 is expected to provide reliable orientation measurement in high temperature direction drilling applications up to 1000h. The DHTA230 electronics incorporate ceramic hybrids with chip and wire construction. Active die are based upon proven 300°C chips developed previously for the Enhanced Geothermal Systems OM300, fabricated using Honeywell HTSOI4 process. The electronics include power conditioning providing reliable operation using a single power supply between 7V and 15V. Dual oscillator electronic circuits provide the necessary function to drive and sense the dual vibrating beams, while providing a CMOS logic level signal of the frequency pulse train. The accelerometer provides precision output up to 15g acceleration inputs, and allows sensing of higher-g vibration levels. This paper contains information on the target application, electrical and mechanical component requirements, design, fabrication approach, and initial prototype testing. The DHTA230 is expected to enter production transition in 2015.

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ZHOU, RIGUI, YANG SHI, MANQUN ZHANG, and HUI'AN WANG. "A NOVEL REVERSIBLE ZS GATE AND ITS APPLICATION FOR OPTIMIZATION OF QUANTUM ADDER CIRCUITS." Journal of Circuits, Systems and Computers 20, no. 06 (October 2011): 1107–29. http://dx.doi.org/10.1142/s0218126611007797.

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The key of optimizing quantum reversible logic lies in automatically constructing quantum reversible logic circuits with the minimal quantum cost. This paper constructs a 4 × 4 reversible gate called ZS gate to build quantum full adder. At the same time, a novel reversible No-Wait-Carry adder (or carry skip adder) by using ZSCGPD based on ZS gate with the least cost is also designed. The adder circuit using the proposed ZSCGPD is much better and optimized than other researchers' counterparts both in terms of garbage outputs, number and kind of reversible gates, and quantum cost. In order to show the efficiency of the proposed designs, lower bounds of the reversible carry skip adder in terms of garbage outputs and quantum cost are proposed as well.

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Reis, Cecília, J. A. Tenreiro Machado, and J. Boaventura Cunha. "Evolutionary Design of Combinational Logic Circuits." Journal of Advanced Computational Intelligence and Intelligent Informatics 8, no. 5 (September 20, 2004): 507–13. http://dx.doi.org/10.20965/jaciii.2004.p0507.

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This paper proposes a genetic algorithm for designing combinational logic circuits and studies four different case examples: 2-to-1 multiplexer, one-bit full adder, four-bit parity checker and a two-bit multiplier. The objective of this work is to generate a functional circuit with the minimum number of gates.

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R. Korde, Rajashri, and Prof Dinesh Rotake. "Design Arithmetic Circuits Using Quaternary Logic." IOSR Journal of Electronics and Communication Engineering 9, no. 3 (2014): 38–43. http://dx.doi.org/10.9790/2834-09333843.

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Bundalo, Dusanka, Zlatko Bundalo, and Branimir Ðordjevic. "Design of quaternary logic systems and circuits." Facta universitatis - series: Electronics and Energetics 18, no. 1 (2005): 45–56. http://dx.doi.org/10.2298/fuee0501045b.

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The principles and possibilities of design of fully quaternary multiple valued combinational logic systems and circuits are described and proposed in the paper. Different ways of design of fully quaternary combinational logic systems and circuits are considered and described first. Then algorithm for automated computerized design of such systems and circuits is considered and proposed. The algorithm gives possibility for synthesis and optimization of quaternary logic systems and circuits. It is applied on design of CMOS quaternary multiple valued logic systems and circuits. The algorithm includes the most important aspects of design of quaternary logic circuits: logic circuit scheme synthesis and logic circuit optimization. Methods for synthesis of quaternary CMOS combinational logic circuits are proposed and described. Also, method for optimization of CMOS quaternary logic circuits, according to operation conditions and needed characteristics, is proposed and described. Design procedure is realized by personal computer using PSPICE for circuit simulation. Computer PSPICE simulation results confirming described methods and conclusions are given in the paper.

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Duncan, Philip N., Siavash Ahrar, and Elliot E. Hui. "Scaling of pneumatic digital logic circuits." Lab on a Chip 15, no. 5 (2015): 1360–65. http://dx.doi.org/10.1039/c4lc01048e.

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We present strategies for scaling pneumatic logic circuits to smaller dimensions. Our process achieves order-of-magnitude increases in both circuit density and speed, enabling the construction of a 12-bit counter.

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35

Yamashita, Shigeru, Yahiko Kambayashi, and Saburo Muroga. "Design of logic circuits with wired-logic utilizing transduction method." Systems and Computers in Japan 27, no. 11 (1996): 19–28. http://dx.doi.org/10.1002/scj.4690271102.

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36

Stojčev, M. "High-Performance System Design: Circuits and Logic." Microelectronics Journal 31, no. 6 (June 2000): 475. http://dx.doi.org/10.1016/s0026-2692(00)00018-5.

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37

Manoj, K. V., and M. Amarnath Reddy. "Design of Logic Circuits Using Reversible Gates." International Journal of Engineering Trends and Technology 16, no. 8 (October 25, 2014): 394–96. http://dx.doi.org/10.14445/22315381/ijett-v16p279.

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38

Kundu, S., S. M. Reddy, and N. K. Jha. "Design of robustly testable combinational logic circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10, no. 8 (1991): 1036–48. http://dx.doi.org/10.1109/43.85740.

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Osman, M. Y., and M. I. Elmasry. "Highly testable design of BiCMOS logic circuits." IEEE Journal of Solid-State Circuits 29, no. 6 (June 1994): 671–78. http://dx.doi.org/10.1109/4.293112.

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Turvani, Giovanna, Matteo Bollo, Marco Vacca, Fabrizio Cairo, Maurizio Zamboni, and Mariagrazia Graziano. "Design of MRAM-Based Magnetic Logic Circuits." IEEE Transactions on Nanotechnology 16, no. 5 (September 2017): 851–59. http://dx.doi.org/10.1109/tnano.2016.2641444.

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Shevelev, S. S. "RECONFIGURABLE COMPUTING MODULAR SYSTEM." Radio Electronics, Computer Science, Control 1, no. 1 (March 31, 2021): 194–207. http://dx.doi.org/10.15588/1607-3274-2021-1-19.

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Context. Modern general purpose computers are capable of implementing any algorithm, but when solving certain problems in terms of processing speed they cannot compete with specialized computing modules. Specialized devices have high performance, effectively solve the problems of processing arrays, artificial intelligence tasks, and are used as control devices. The use of specialized microprocessor modules that implement the processing of character strings, logical and numerical values, represented as integers and real numbers, makes it possible to increase the speed of performing arithmetic operations by using parallelism in data processing. Objective. To develop principles for constructing microprocessor modules for a modular computing system with a reconfigurable structure, an arithmetic-symbolic processor, specialized computing devices, switching systems capable of configuring microprocessors and specialized computing modules into a multi-pipeline structure to increase the speed of performing arithmetic and logical operations, high-speed design algorithms specialized processors-accelerators of symbol processing. To develop algorithms, structural and functional diagrams of specialized mathematical modules that perform arithmetic operations in direct codes on neural-like elements and systems for decentralized control of the operation of blocks. Method. An information graph of the computational process of a modular system with a reconstructed structure has been built. Structural and functional diagrams, algorithms that implement the construction of specialized modules for performing arithmetic and logical operations, search operations and functions for replacing occurrences in processed words have been developed. Software has been developed for simulating the operation of an arithmetic-symbolic processor, specialized computing modules, and switching systems. Results. A block diagram of a reconfigurable computing modular system has been developed, which consists of compatible functional modules, it is capable of static and dynamic reconfiguration, has a parallel structure for connecting the processor and computing modules through the use of interface channels. The system consists of an arithmetic-symbolic processor, specialized computing modules and switching systems, performs specific tasks of symbolic information processing, arithmetic and logical operations. Conclusions. The architecture of reconfigurable computing systems can change dynamically during their operation. It becomes possible to adapt the architecture of a computing system to the structure of the problem being solved, to create problem-oriented computers, the structure of which corresponds to the structure of the problem being solved. As the main computing element in reconfigurable computing systems, not universal microprocessors are used, but programmable logic integrated circuits, which are combined using high-speed interfaces into a single computing field. Reconfigurable multipipeline computing systems based on fields are an effective tool for solving streaming information processing and control problems.

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HOE, DAVID H. K., and C. ANDRE T. SALAMA. "DYNAMIC GaAs LOGIC CIRCUITS." International Journal of High Speed Electronics and Systems 02, no. 03 (September 1991): 163–83. http://dx.doi.org/10.1142/s0129156491000089.

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Because of their ratioless nature, dynamic logic has several advantages over conventional static techniques used in GaAs . The ability to implement complex gates with dynamic logic leads to circuits with increased speed and reduced power dissipation. Several dynamic configurations using GaAs MESFETs are reviewed. The main challenge is to overcome leakage currents associated with the Schottky gate junctions in order to allow reliable dynamic operation. The pipelining of GaAs dynamic circuits, which allows full use of the clock cycle and improves system throughput, is also discussed. The feasibility of using these dynamic designs in GaAs is illustrated through the design and implementation of complex functional blocks.

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TSAI, I.-MING, and SY-YEN KUO. "AN ALGORITHM FOR MINIMUM SPACE QUANTUM BOOLEAN CIRCUITS CONSTRUCTION." Journal of Circuits, Systems and Computers 15, no. 05 (October 2006): 719–38. http://dx.doi.org/10.1142/s0218126606003349.

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Implementing a quantum computer at the circuit level has emerged as an important field of research recently. An important topic of building a general-purpose quantum computer is to implement classical Boolean logic using quantum gates and devices. Since the Toffoli gate is universal in classical Boolean logic, any classical combinational circuit can be implemented by the straightforward replacement algorithm with auxiliary qubits as intermediate storage. However, this inefficient implementation causes a large number of auxiliary qubits to be used. In this paper, a systematic procedure is proposed to derive a minimum space quantum circuit for a given classical combinational logic. We first formulate the problem of transforming an m-to-n bit classical Boolean logic into a t-bit unitary quantum operation. The eligible solution set is then constructed such that a solution can be found simply by selecting any member from this set. Finally, we show that the algorithm is optimal in terms of the space consumption.

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Luo, Li, Zhekang Dong, Xiaofang Hu, Lidan Wang, and Shukai Duan. "MTL: Memristor Ternary Logic Design." International Journal of Bifurcation and Chaos 30, no. 15 (December 9, 2020): 2050222. http://dx.doi.org/10.1142/s0218127420502223.

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The nanoscale implementations of ternary logic circuits are particularly attractive because of high information density and operation speed that can be achieved by using emerging memristor technologies. Memristor is a nanoscale device with nonvolatility and adjustable multilevel states, which creates an intriguing opportunity for the implementation of ternary logic operations. This paper proposes a novel memristor-based design for stateful ternary logic, including AND, OR, NOT, NAND, NOR, and COPY operations. In the proposed memristor ternary logic (MTL) design, the resistance of memristor is the only logic state variable for representing the input and output. By sensing the value of the input memristors, the resistance of the output memristor changes accordingly. Furthermore, the MTL gates are not only capable of performing logic operations, but also storing logic values. To illustrate the potential of the methodology, a single-input-three-output ternary decoder is designed by using the proposed ternary logic circuits. Simulation results verify the effectiveness of the presented design.

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Hurst, S. L. "Logic design for array-based circuits: A structured design methodology." Microelectronics Journal 26, no. 5 (July 1995): xvii. http://dx.doi.org/10.1016/0026-2692(95)90046-2.

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Gavrilov, S. V., and D. V. Telpukhov. "Automated Evolutionary Design of Fault-Tolerant Logic Circuits." Problems of advanced micro- and nanoelectronic systems development, no. 1 (2019): 2–6. http://dx.doi.org/10.31114/2078-7707-2019-1-2-6.

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H., Rohini, and Rajashekar S. "Design of Reversible Logic based Basic Combinational Circuits." Communications on Applied Electronics 5, no. 9 (September 26, 2016): 38–43. http://dx.doi.org/10.5120/cae2016652372.

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Cavalcante, Tássio Côrtes, Richard McWilliam, and Alan Purvis. "The Design of Reliable Circuits Using Logic Redundancy." Procedia CIRP 22 (2014): 138–41. http://dx.doi.org/10.1016/j.procir.2014.07.017.

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Aoki, K., Y. Tazoh, and H. Yoshikiyo. "Low crosstalk packaging design for Josephson logic circuits." IEEE Transactions on Magnetics 21, no. 2 (March 1985): 741–44. http://dx.doi.org/10.1109/tmag.1985.1063705.

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Wu, S. F., and P. D. Fisher. "Automating the design of asynchronous sequential logic circuits." IEEE Journal of Solid-State Circuits 26, no. 3 (March 1991): 364–70. http://dx.doi.org/10.1109/4.75015.

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Journal articles on the topic 'Logic circuits Design and construction'

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