Academic literature on the topic 'Logic circuits – Design – Data processing'
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Journal articles on the topic "Logic circuits – Design – Data processing"
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Devnath, Bappy Chandra, and Satyendra N. Biswas. "Low Power Full Adder Design Using PTM Transistor Model." Carpathian Journal of Electronic and Computer Engineering 12, no. 2 (2019): 15–20. http://dx.doi.org/10.2478/cjece-2019-0011.
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Abstract At present the processing power of the digital electronic chip is enormous and that has been possible because of the continuous improvement of the design methodology and fabrication technology. So, the data processing capability of the chip is increased significantly. Data processing in the electronic chip means the arithmetic operation on that data. For that reason, ALU is present in any processor. Full adder is one of the critical components of arithmetic unit. Improvement of the full adder is necessary for improving the computational performance of a chip. In order to design an efficient full adder, designer should choose an appropriate logic style. In this research, two new model of full-adder circuits are designed and analyzed using Pass Transistor logic in order to reduce power consumption and increase operational speed. The first proposed adder consists of 8 transistors and the second one consists of 10 transistors. LTSPICE is employed for simulating the proposed circuits using16nm low power high-k strained silicon transistor model. The overall performance of the proposed adder circuits and comparative results demonstrate the superiority of the proposed model.
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CHATTOPADHYAY, TANAY, GOUTAM KUMAR MAITY, and JITENDRA NATH ROY. "DESIGNING OF ALL-OPTICAL TRI-STATE LOGIC SYSTEM WITH THE HELP OF OPTICAL NONLINEAR MATERIAL." Journal of Nonlinear Optical Physics & Materials 17, no. 03 (2008): 315–28. http://dx.doi.org/10.1142/s0218863508004159.
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Nonlinear optics has been of increased interest for all-optical signal, data and image processing in high speed photonic networks. The application of multi-valued (nonbinary) digital signals can provide considerable relief in transmission, storage and processing of a large amount of information in digital signal processing. Here, we propose the design of an all-optical system for some basic tri-state logic operations (trinary OR, trinary AND, trinary XOR, Inverter, Truth detector, False detector) which exploits the polarization properties of light. Nonlinear material based optical switch can play an important role. Tri-state logic can play a significant role towards carry and borrow free arithmetic operations. The principles and possibilities of the design of nonlinear material based tri-state logic circuits are proposed and described.
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Ilijin, Sandra, and Predrag Petkovic. "Implementation of control logic in the scoreboard of tennis." Serbian Journal of Electrical Engineering 12, no. 2 (2015): 219–36. http://dx.doi.org/10.2298/sjee1502219i.
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This paper presents one original solution of control logic for scoreboard in tennis match. The main goal is to simplify the process of recording points. Instead of using six buttons the chair umpire (referee) will use only two control buttons or a joystick to assign a point to a player. The proposed system takes care of all other data processing. The system is designed in Application Specific Integrated Circuits (ASIC) and Standard Application Specific Integrated Circuits (SASIC) technology to demonstrate similarities and differences between two design technologies. Finally it is realized on FPGA type EP2C35F672C6 from Cyclone II Altera?s family.
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Shi, Weiwei, Jinyong Zhang, Zhiguo Zhang, Lizhi Hu, and Yongqian Su. "An introduction and review on innovative silicon implementations of implantable/scalp EEG chips for data acquisition, seizure/behavior detection, and brain stimulation." Brain Science Advances 6, no. 3 (2020): 242–54. http://dx.doi.org/10.26599/bsa.2020.9050024.
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Technological advances in the semiconductor industry and the increasing demand and development of wearable medical systems have enabled the development of dedicated chips for complex electroencephalogram (EEG) signal processing with smart functions and artificial intelligence‐based detections/classifications. Around 10 million transistors are integrated into a 1 mm2 silicon wafer surface in the dedicated chip, making wearable EEG systems a powerful dedicated processor instead of a wireless raw data transceiver. The reduction of amplifiers and analog‐digital converters on the silicon surface makes it possible to place the analog front‐end circuits within a tiny packaged chip; therefore, enabling high‐count EEG acquisition channels. This article introduces and reviews the state‐of‐the‐art dedicated chip designs for EEG processing, particularly for wearable systems. Furthermore, the analog circuits and digital platforms are included, and the technical details of circuit topology and logic architecture are presented in detail.
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Goldsworthy, Victoria, Geneva LaForce, Seth Abels, and Emil Khisamutdinov. "Fluorogenic RNA Aptamers: A Nano-platform for Fabrication of Simple and Combinatorial Logic Gates." Nanomaterials 8, no. 12 (2018): 984. http://dx.doi.org/10.3390/nano8120984.
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RNA aptamers that bind non-fluorescent dyes and activate their fluorescence are highly sensitive, nonperturbing, and convenient probes in the field of synthetic biology. These RNA molecules, referred to as light-up aptamers, operate as molecular nanoswitches that alter folding and fluorescence function in response to ligand binding, which is important in biosensing and molecular computing. Herein, we demonstrate a conceptually new generation of smart RNA nano-devices based on malachite green (MG)-binding RNA aptamer, which fluorescence output controlled by addition of short DNA oligonucleotides inputs. Four types of RNA switches possessing AND, OR, NAND, and NOR Boolean logic functions were created in modular form, allowing MG dye binding affinity to be changed by altering 3D conformation of the RNA aptamer. It is essential to develop higher-level logic circuits for the production of multi-task nanodevices for data processing, typically requiring combinatorial logic gates. Therefore, we further designed and synthetized higher-level half adder logic circuit by “in parallel” integration of two logic gates XOR and AND within a single RNA nanoparticle. The design utilizes fluorescence emissions from two different RNA aptamers: MG-binding RNA aptamer (AND gate) and Broccoli RNA aptamer that binds DFHBI dye (XOR gate). All computationally designed RNA devices were synthesized and experimentally tested in vitro. The ability to design smart nanodevices based on RNA binding aptamers offers a new route to engineer “label-free” ligand-sensing regulatory circuits, nucleic acid detection systems, and gene control elements.
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Ou, Qiao-Feng, Bang-Shu Xiong, Lei Yu, Jing Wen, Lei Wang, and Yi Tong. "In-Memory Logic Operations and Neuromorphic Computing in Non-Volatile Random Access Memory." Materials 13, no. 16 (2020): 3532. http://dx.doi.org/10.3390/ma13163532.
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Recent progress in the development of artificial intelligence technologies, aided by deep learning algorithms, has led to an unprecedented revolution in neuromorphic circuits, bringing us ever closer to brain-like computers. However, the vast majority of advanced algorithms still have to run on conventional computers. Thus, their capacities are limited by what is known as the von-Neumann bottleneck, where the central processing unit for data computation and the main memory for data storage are separated. Emerging forms of non-volatile random access memory, such as ferroelectric random access memory, phase-change random access memory, magnetic random access memory, and resistive random access memory, are widely considered to offer the best prospect of circumventing the von-Neumann bottleneck. This is due to their ability to merge storage and computational operations, such as Boolean logic. This paper reviews the most common kinds of non-volatile random access memory and their physical principles, together with their relative pros and cons when compared with conventional CMOS-based circuits (Complementary Metal Oxide Semiconductor). Their potential application to Boolean logic computation is then considered in terms of their working mechanism, circuit design and performance metrics. The paper concludes by envisaging the prospects offered by non-volatile devices for future brain-inspired and neuromorphic computation.
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Пирогов, А. А., Ю. А. Пирогова, С. А. Гвозденко, Д. В. Шардаков, and Б. И. Жилин. "DEVELOPMENT OF RECONFIGURABLE DEVICES BASED ON PROGRAMMABLE LOGIC INTEGRATED CIRCUITS." ВЕСТНИК ВОРОНЕЖСКОГО ГОСУДАРСТВЕННОГО ТЕХНИЧЕСКОГО УНИВЕРСИТЕТА, no. 6 (January 10, 2021): 90–97. http://dx.doi.org/10.36622/vstu.2020.16.6.013.
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Цифровая фильтрация распознаваемых сигналов является непременной процедурой при обнаружении и распознавании сообщений. Под фильтрацией понимают любое преобразование сигналов, при котором во входной последовательности обрабатываемых данных целенаправленно изменяются определенные соотношения между различными параметрами сигналов. Системы, избирательно меняющие форму сигналов, устраняющие или уменьшающие помехи, извлекающие из сигналов определенную информацию и т.п., называют фильтрами. Соответственно, фильтры с любым целевым назначением являются частным случаем систем преобразования сигналов. Программируемые логические интегральные схемы (ПЛИС) представляют собой конфигурируемые интегральные схемы, логика работы которых определяется посредством их программирования. Применение ПЛИС для задач цифровой обработки сигналов позволяет получать устройства, способные менять конфигурацию, подстраиваться под определенную задачу за счет их гибко изменяемой, программируемой структуры. При разработке сложных устройств могут применяться в качестве компонентов для проектирования готовые блоки - IP-ядра или сложно-функциональные блоки (СФ-блоки). Использование программных СФ-блоков позволяет наиболее эффективно задействовать их в конечной структуре, в значительной степени сократить затраты на проектирование. Цель работы состоит в построении RTL модели СФ-блока цифровой обработки сигналов, его верификации как на логическом уровне, так и физическом Digital filtering of recognized signals is an indispensable procedure for the detection and recognition of messages. Filtering is understood as any transformation of signals in which certain relationships between different signal parameters are purposefully changed in the input sequence of the processed data. Systems that selectively change the shape of signals, eliminate or reduce interference, extract certain information from the signals, and so on, are called filters. Accordingly, filters with any purpose are a special case of signal conversion systems. Programmable logic integrated circuits (FPGAs) are configurable integrated circuits whose logic is defined through programming. The use of FPGAs for digital signal processing tasks makes it possible to obtain devices capable of changing the configuration, adapting to a specific task due to their flexibly changeable, programmable structure. When developing complex devices, ready-made blocks - IP-cores or complex-functional blocks (SF blocks) - can be used as components for design. The use of software SF-blocks allows them to be used most effectively in the final structure, to a significant extent to reduce design costs. The purpose of the work is to build an RTL model of the SF-block for digital signal processing, its verification both at the logical and physical levels
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Yanushkevich, Svetlana, Hong Tran, Golam Tangim, Vladimir Shmerko, Elena Zaitseva, and Vitaly Levashenko. "The EXOR gate under uncertainty: A case study." Facta universitatis - series: Electronics and Energetics 24, no. 3 (2011): 451–82. http://dx.doi.org/10.2298/fuee1103451y.
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Probabilistic AND/EXOR networks have been defined, in the past, as a class of Reed-Muller circuits, which operate on random signals. In contemporary logic network design, it is classified as behavioral notation of probabilistic logic gates and networks. In this paper, we introduce additional notations of probabilistic AND/EXOR networks: belief propagation, stochastic, decision diagram, neuromorphic models, and Markov random field model. Probabilistic logic networks, and, in particular, probabilistic AND/EXOR networks, known as turbo-decoders (used in cell phones and iPhone) are in demand in the coding theory. Another example is intelligent decision support in banking and security applications. We argue that there are two types of probabilistic networks: traditional logic networks assuming random signals, and belief propagation networks. We propose the taxonomy for this design, and provide the results of experimental study. In addition, we show that in forthcoming technologies, in particular, molecular electronics, probabilistic computing is the platform for developing the devices and systems for low-power low-precise data processing.
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Lin, Hai Yan, Hai Liu, and Yin Zhao Wang. "Design of Hardware Based on Control Circuit of APF." Applied Mechanics and Materials 148-149 (December 2011): 353–56. http://dx.doi.org/10.4028/www.scientific.net/amm.148-149.353.
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In this paper, we focus on the hardware design of control circuit based on shunt active power filter (APF). It described the AD transformation module, DSP data processing module, CPLD logic control module, man-machine interaction module and asynchronous communication module. As the core controller, TMS320C5416 digital signal processor (DSP) controls this peripheral assistant circuit to complete data acquisition, harmonic detection and output of control signal. Finally, we design the layout and routing of the control circuit.
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Tripathi, Devendra Kr. "Investigations with Reversible Feynman Gate and Irreversible Logic Schematics." Journal of Optical Communications 40, no. 4 (2019): 385–92. http://dx.doi.org/10.1515/joc-2017-0106.
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Abstract In the contemporary world there is enormous hike in communication engineering applications, outcome with massive heat dissipation from the processing nodes. So energy efficient information network is one of paramount issue nowadays. For that optical reversible computing could be a landmark with base as optical logic gate. Reduction in power dissipation, consumption could be accomplished through a blend of reversible and irreversible optical processing and the nodes may recuperate the data. Accordingly, in this article two designs with semiconductor optical amplifier, used as Mach–Zehnder interferometer based all optical reversible Feynman gate, irreversible AND logic gate within a single photonic circuit has been proposed. The output waveforms for AND logic operation, Feynman logic the P (data output identical to input), Q (A ⊕ B) has been verified at 100 Gbps data rate. The designs have been evaluated on the basis of key parameter extinction ratio factor. Numerical simulations have inferred excellent ER performance with design-2(ER>13 dB) in contrast to design-1(ER as 10.2 dB). Performance evaluations for significant deign parameters as pump current, length, width, carrier transport, confine and current injection factor yielded excellent performance. This evaluation could be an assist toward design of contemporary optical networks.
Dissertations / Theses on the topic "Logic circuits – Design – Data processing"
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Roumeliotis, Emmanuel. "Multi-processor logic simulation at the chip level." Diss., Virginia Polytechnic Institute and State University, 1986. http://hdl.handle.net/10919/71180.
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This dissertation presents the design and development of a multi-processor logic simulator. After an introduction to parallel processing, the concept of distributed simulation is described as well as the possibility of deadlock in a distributed system. It is proven that the proposed system does not deadlock. Next, the modeling techniques are discussed along with the timing mechanisms used for logic simulation. A new approach, namely process oriented simulation is studied in depth. It is shown that modeling for this kind of simulation is more efficient regarding modeling ease, computer memory and simulation time, than existing simulation methods. The hardware design of the multi-processor system and the algorithms for synchronization and signal interchange between the processors are presented next. An algorithm for an efficient partitioning of the digital network to be simulated among the processors of the system is also described. Apart from the simulation of a single digital network, the simulator can also be used for fault simulation and design verification. Regarding fault simulation, the fault injection and fault detection techniques are presented. The experimental results obtained by running the multi-processor simulator are compared with the theoretical estimates as well as with results obtained by other multi-processor systems. The comparison shows that the proposed simulator exhibits the estimated performance. Finally, the design of a common bus interface is given. This interface will connect the processors of the system directly without the intervention of a hard disk which was used for the development and testing of the system.<br>Ph. D.
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Rahman, Md Raqibur. "Online testing in ternary reversible logic." Thesis, Lethbridge, Alta. : University of Lethbridge, c2011, 2011. http://hdl.handle.net/10133/3208.
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In recent years ternary reversible logic has caught the attention of researchers because of its
enormous potential in different fields, in particular quantum computing. It is desirable that
any future reversible technology should be fault tolerant and have low power consumption;
hence developing testing techniques in this area is of great importance.
In this work we propose a design for an online testable ternary reversible circuit. The
proposed design can implement almost all of the ternary logic operations and is also capable
of testing the reversible ternary network in real time (online). The error detection unit is
also constructed in a reversible manner, which results in an overall circuit which meets
the requirements of reversible computing. We have also proposed an upgrade of the initial
design to make the design more optimized. Several ternary benchmark circuits have been
implemented using the proposed approaches. The number of gates required to implement
the benchmarks for each approach have also been compared. To our knowledge this is the
first such circuit in ternary with integrated online testability feature.<br>xii, 92 leaves : ill. ; 29 cm
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Kusalik, Anthony Joseph. "Logic programming as a formalism for specification and implementation of computer systems." Thesis, University of British Columbia, 1988. http://hdl.handle.net/2429/28848.
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The expressive power of logic-programming languages allows utilization of conventional constructs
in development of computer systems based on logic programming. However, logic-programming languages have many novel features and capabilities. This thesis investigates how advantage can be taken of these features in the development of a logic-based computer system. It demonstrates that innovative
approaches to software, hardware, and computer system design and implementation are feasible in a logic-programming context and often preferable to adaptation of conventional ones. The investigation
centers on three main ideas: executable specification, declarative I/O, and implementation through transformation and meta-interpretation. A particular class of languages supporting parallel computation, committed-choice logic-programming languages, are emphasized. One member of this class, Concurrent
Prolog, serves as the machine, specification, and implementation language.
The investigation has several facets. Hardware, software, and overall system models for a logic-based computer are determined and examined. The models are described by logic programs. The computer
system is represented as a goal for resolution. The clauses involved in the subsequent reduction steps constitute its specification. The same clauses also describe the manner in which the computer system
is initiated. Frameworks are given for developing models of peripheral devices whose actions and interactions can be declaratively expressed. Interactions do not rely on side-effects or destructive assignment, and are term-based. A methodology is presented for realizing (prototypic) implementations from device specifications. The methodology is based on source-to-source transformation and meta-interpretation. A magnetic disk memory is used as a representative example, resulting in an innovative approach to secondary storage in a logic-programming environment. Building on these accomplishments,
a file system for a logic-based computer system is developed. The file system follows a simple model and supports term-based, declarative I/O. Throughout the thesis, features of the logic-programming paradigm are demonstrated and exploited. Interesting and innovative concepts established include: device processes and device processors; restartable and perpetual devices and systems; peripheral
devices modelled as function computations or independent logical (inference) systems; unique, compact representations of terms; lazy term expansion; files systems as perpetual processes maintaining local states; and term- and unification-based file abstractions. Logic programs are the sole formalism for specifications and implementations.<br>Science, Faculty of<br>Computer Science, Department of<br>Graduate
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Wist, Dominic. "Attacking complexity in logic synthesis of asynchronous circuits." Phd thesis, Universität Potsdam, 2011. http://opus.kobv.de/ubp/volltexte/2012/5970/.
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Most of the microelectronic circuits fabricated today are synchronous, i.e. they are driven by one or several clock signals. Synchronous circuit design faces several fundamental challenges such as high-speed clock distribution, integration of multiple cores operating at different clock rates, reduction of power consumption and dealing with voltage, temperature, manufacturing and runtime variations. Asynchronous or clockless design plays a key role in alleviating these challenges, however the design and test of asynchronous circuits is much more difficult in comparison to their synchronous counterparts.
A driving force for a widespread use of asynchronous technology is the availability of mature EDA (Electronic Design Automation) tools which provide an entire automated design flow starting from an HDL (Hardware Description Language) specification yielding the final circuit layout. Even though there was much progress in developing such EDA tools for asynchronous circuit design during the last two decades, the maturity level as well as the acceptance of them is still not comparable with tools for synchronous circuit design. In particular, logic synthesis (which implies the application of Boolean minimisation techniques) for the entire system's control path can significantly improve the efficiency of the resulting asynchronous implementation, e.g. in terms of chip area and performance. However, logic synthesis, in particular for asynchronous circuits, suffers from complexity problems.
Signal Transitions Graphs (STGs) are labelled Petri nets which are a widely used to specify the interface behaviour of speed independent (SI) circuits - a robust subclass of asynchronous circuits.
STG decomposition is a promising approach to tackle complexity problems like state space explosion in logic synthesis of SI circuits. The (structural) decomposition of STGs is guided by a partition of the output signals and generates a usually much smaller component STG for each partition member, i.e. a component STG with a much smaller state space than the initial specification.
However, decomposition can result in component STGs that in isolation have so-called irreducible CSC conflicts (i.e. these components are not SI synthesisable anymore) even if the specification has none of them. A new approach is presented to avoid such conflicts by introducing internal communication between the components.
So far, STG decompositions are guided by the finest output partitions, i.e. one output per component. However, this might not yield optimal circuit implementations. Efficient heuristics are presented to determine coarser partitions leading to improved circuits in terms of chip area.
For the new algorithms correctness proofs are given and their implementations are incorporated into the decomposition tool DESIJ. The presented techniques are successfully applied to some benchmarks - including 'real-life' specifications arising in the context of control resynthesis - which delivered promising results.<br>Moderner Schaltungsentwurf fokussiert hauptsächlich synchrone Schaltungstechnik mit allen inhärenten Problemen. Asynchone (d.h. ungetaktete) Schaltungen zeichnen sich jedoch nicht nur durch das Fehlen der Taktversatzproblematik gegenüber ihren synchronen Pendents aus, sondern auch insbesondere durch geringeren Energieverbrauch, günstigere EMV-Eigenschaften, hohe Performance, Modularität und Robustheit gegenüber Schwankungen in der Spannungsversorgung, im Herstellungsprozess sowie Temperaturunterschieden. Diese Vorteile werden mit höherer Integration sowie höheren Taktraten signifikanter. Jedoch ist der Entwurf und auch der Test asynchroner Schaltungen erheblich schwieriger verglichen mit synchronen Schaltungen.
Entwurfswerkzeuge zur Synthese asynchroner Schaltungen aus Hochsprachen-Spezifikationen sind zwar inzwischen verfügbar, sie sind jedoch noch nicht so ausgereift und bei weitem noch nicht so akzeptiert in der Industrie, wie ihre Äquivalente für den synchronen Schaltungsentwurf. Insbesondere fehlt es an Werkzeugunterstützung im Bereich der Logiksynthese komplexer Steuerungen („Controller“), welche kritisch für die Effizienz – z.B. in Bezug auf Chipfläche und Geschwindigkeit – der resultierenden Schaltungen oder Systeme ist.
Zur Spezifikation von Steuerungen haben sich Signalflankengraphen („signal transition graphs“, STGs) bewährt, die auch als Entwurfseinstieg für eine Logiksynthese von SI-Schaltungen („speed independent“) verwendet werden. (SI-Schaltungen gelten als sehr robuste asynchrone Schaltungen.) Aus den STGs werden zwecks Logiksynthese Automaten abgeleitet werden, deren Zustandszahl aber oft prohibitiv groß werden kann. Durch sogenannte STG-Dekomposition wird die Logiksynthese einer komplexen Schaltung ermöglicht, was bislang aufgrund von Zustandsexplosion oft nicht möglich war. Dabei wird der Spezifikations-STG laut einer gegebenen Partition von Ausgangssignalen in viele kleinere Teilnetze dekomponiert, wobei zu jedem Partitionsblock ein Teilnetz – mit normalerweise signifikant kleinerem Zustandsraum im Vergleich zur Spezifikation – erzeugt wird. Zu jedem Teilnetz wird dann eine Teilschaltung (Komponente) mittels Logiksynthese generiert.
Durch die Anwendung von STG-Dekomposition können jedoch Teilnetze erzeugt werden, die sogenannte irreduzible CSC-Konflikte aufweisen (d.h. zu diesen Teilnetzen kann keine SI-Schaltung erzeugt werden), obwohl die Spezifikation keine solchen Konflikte hatte. Diese Arbeit präsentiert einen neuen Ansatz, welcher die Entstehung solcher irreduziblen Konflikte vermeidet, und zwar durch die Einführung interner Kommunikation zwischen den (zu den Teilnetzen gehörenden) Schaltungskomponenten.
Bisher werden STG-Dekompositionen total durchgeführt, d.h. pro resultierender Komponente wird ein Ausgangssignal erzeugt. Das führt gewöhnlich nicht zu optimalen Schaltungsimplementierungen. In dieser Arbeit werden Heuristiken zur Bestimmung gröberer Ausgabepartitionen (d.h. Partitionsblöcke mit mehreren Ausgangssignalen) vorgestellt, die zu kleineren Schaltungen führen.
Die vorgestellten Algorithmen werden formal abgesichert und wurden in das bereits vorhandene Dekompositionswerkzeug DESIJ integriert. An praxisrelevanten Beispielen konnten die vorgestellten Verfahren erfolgreich erprobt werden.
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Zhou, Lixin. "Testability Design and Testability Analysis of a Cube Calculus Machine." PDXScholar, 1995. https://pdxscholar.library.pdx.edu/open_access_etds/4911.
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Cube Calculus is an algebraic model popular used to process and minimize Boolean functions. Cube Calculus operations are widely used in logic optimization, logic synthesis, computer image processing and recognition, machine learning, and other newly developing applications which require massive logic operations. Cube calculus operations can be implemented on conventional general-purpose computers by using the appropriate "model" and software which manipulates this model. The price that we pay for this software based approach is severe speed degradation which has made the implementation of several high-level formal systems impractical. A cube calculus machine which has a special data path designed to execute multiplevalued input, and multiple-valued output cube calculus operations is presented in this thesis. This cube calculus machine can execute cube calculus operations 10-25 times faster than the software approach. For the purpose of ensuring the manufacturing testability of the cube calculus machine, emphasize has been put on the testability design of the cube calculus machine. Testability design and testability analysis of the iterative logic unit of the cube calculus machine was accomplished. Testability design and testability analysis methods of the cube calculus machine are weli discussed in this thesis. Full-scan testability design method was used in the testability design and analysis. Using the single stuck-at fault model, a 98.30% test coverage of the cube calculus machine was achieved. A Povel testability design and testability analysis approach is also presented in this thesis.
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馮潤開 and Yun-hoi Fung. "Linguistic fuzzy-logic control of autonomous vehicles." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1998. http://hub.hku.hk/bib/B29812690.
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Eben-Chaime, Moshe. "The physical design of printed circuit boards : a mathematical programming approach." Diss., Georgia Institute of Technology, 1989. http://hdl.handle.net/1853/25505.
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Dongier, François. "ND, a rule-based implementation of natural deduction : design of the theorem-prover and tutoring system." Thesis, McGill University, 1988. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63952.
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Bharath, Karthik. "The logic of information flow a graded approach /." Diss., Online access via UMI:, 2008.
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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2008.<br>Includes bibliographical references.
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Ismailoglu, Ayse Neslin. "Asynchronous Design Of Systolic Array Architectures In Cmos." Phd thesis, METU, 2008. http://etd.lib.metu.edu.tr/upload/12609443/index.pdf.
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In this study, delay-insensitive asynchronous circuit design style has been adopted to systolic array architectures to exploit the benefits of both techniques for improved throughput. A delay-insensitivity verification analysis method employing symbolic delays is proposed for bit-level pipelined asynchronous circuits. The proposed verification method allows datadependent early output evaluation to co-exist with robust delay-insensitive circuit behavior in pipelined architectures such as systolic arrays. Regardless of the length of the pipeline, delay-insensitivity verification of a systolic array with early output evaluation paths in onedimension is reduced to analysis of three adjacent systoles for eight possible early/late output evaluation scenarios. Analyzing both combinational and sequential parts
concurrently, delay-insensitivity violations are located and corrected at structural level, without diminishing the early output evaluation benefits. Since symbolic delays are used
without imposing any timing constraints on the environment<br>the method is technology independent and robust against all physical and environmental variations. To demonstrate
the verification method, adders are selected for being at the core of data processing systems. Two asynchronous adder topologies in the delay-insensitive dual-rail threshold logic style, having data-dependent early carry evaluation paths, are converted into bit-level pipelined systolic arrays. On these adders, data-dependent delay-insensitivity violations are detected and resolved using the proposed verification technique. The modified adders achieved the targeted O(log2n) average completion time and -as a result of bit-level pipelining- nearly constant throughput against increased bit-length. The delay-insensitivity verification method
could further be extended to handle more early output evaluation paths in multi-dimension.
Books on the topic "Logic circuits – Design – Data processing"
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Logic design for array-based circuits: A structured design methodology. Academic Press, 1992.
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Gaetano, Borriello, ed. Contemporary logic design. 2nd ed. Pearson Prentice Hall, 2005.
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Edwards, Martyn D. Automatic logic synthesis techniques for digital systems. McGraw-Hill, 1992.
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Taher, Abbasi, ed. Logic synthesis using Synopsys. Kluwer Academic Publishers, 1995.
Find full textBook chapters on the topic "Logic circuits – Design – Data processing"
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Mo, Dandan, Matthew R. Lakin, and Darko Stefanovic. "Scalable Design of Logic Circuits Using an Active Molecular Spider System." In Information Processing in Cells and Tissues. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-23108-2_2.
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Zhao, Shuguang, Mingying Zhao, Jin Li, and Change Wang. "CBR-Based Knowledge Discovery on Results of Evolutionary Design of Logic Circuits." In Advanced Data Mining and Applications. Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11811305_96.
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Li, Chengdong, Li Wang, Zixiang Ding, and Guiqing Zhang. "Data-Driven Design of Type-2 Fuzzy Logic System by Merging Type-1 Fuzzy Logic Systems." In Neural Information Processing. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-46675-0_32.
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Lin, Guangfu, Zhenxing Yin, and Guo Feng. "Design and Implementation of Bipolar Digital Signal Acquisition and Processing System based on FPGA and ACPL-224." In Global Applications of Pervasive and Ubiquitous Computing. IGI Global, 2013. http://dx.doi.org/10.4018/978-1-4666-2645-4.ch022.
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This paper proposes new approaches for designing a bipolar DS acquisition system to reduce the harm of external factors on equipment, as well as fulfill system requirements at the veracity and reliability of the equipment to quickly connect. The design method chosen is ACPL-224 for chip of the interface about data acquisition on the FPGA device, including system principle, interface circuit logic, the method of data processing, and so forth. Now that this method has been applied, it has achieved good results, including extending the system’s adaptive range of external signal and enhancing the efficiency of the interface to quickly connect.
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Plerou, Antonia, and Panayiotis Vlamos. "Evaluation of Mathematical Cognitive Functions with the Use of EEG Brain Imaging." In Advances in Multimedia and Interactive Technologies. IGI Global, 2016. http://dx.doi.org/10.4018/978-1-4666-8659-5.ch014.
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During the last decades, the interest displayed in neurocognitive and brain science research is relatively high. In this chapter, the cognitive neuroscience field approach focuses in the aspect of the way that cognitive functions are produced by neural circuits in the brain. Within this frame, the effects of impairment to the brain and subsequent changes in the thought processes due to changes in neural circuitry resulting from the ensued damage are analyzed and evaluated. All cognitive functions result from the integration of many simple processing mechanisms, distributed throughout the brain. Brain cortex structures, linked with cognitive disorders, are located in several parts like the frontal, the parietal, the temporal, the occipital lobe and more are analyzed and specified. A critical topic of this chapter in the evaluation of brain operations is mapping regions that control cognitive and mathematical concepts functions. Dyscalculia, in this chapter, is described as a specific disorder of managing and conceiving mathematical concepts. Dyscalculia could be identified by difficulties in visual perception, in spatial number organization, in basic mathematical operations and in mathematical induction logic. Moreover, people who deal with dyscalculia present problems, in Euclidean and Non-Euclidean Geometry concepts perception, in Calculus aspects as well as in solving algorithmic problems where the design, the description and the application of algorithmic steps are required. In order to enhance cognitive brain functions perception, the use of EEG brain imaging is proposed measuring cerebral activity and event-related potentials. The procedure described in this chapter is about the comparison and contrasts EEG brain imaging patterns of healthy volunteers to EEG samples taken of adults considered being at risk of mathematics learning disabilities such as Dyscalculia and algorithmic thinking difficulties. EEG interpretation analysis is to follow where the deviation of a normal and an abnormal range of wave's frequency are defined. Several visualized EEG patterns in relevance with specific abnormalities are presented while several neurocognitive generated disorders could be identified with the use of EEG Brain-imaging technique. The electroencephalogram EEG brain imaging procedure, in order to evaluate problems associated with brain function, is to be further analyzed in this chapter as well. The EEG is the depiction of the electrical activity occurring at the surface of the brain. The recorded waveforms reflect the cortical electrical activity and they are generally classified according to their frequency (Delta, Theta, Beta, Alpha, Beta, and Gamma) amplitude, and shape. EEG Implementation with the use of 10/20 system of the standardized position of scalp electrodes placement for a classical EEG recording is described as well. The EEG implementation objective is to identify, classify and evaluate those frequencies and regions in the brain that best characterize brain activity associated with mathematical learning disabilities. Mapping the brain with non-invasive techniques based on trigger and sensing/evaluation experimental multimedia methods similar to those used in computer games and applications are expected to provide relevant results in order to enhance and confirm theoretical cognitive aspects. At that point, a cognitive and mathematical perception evaluation is to follow and specifically the assessment of the relation of difficulties in mathematics with particular parts of the human brain. EEG wave data visualization is contacted with the use of Acknowledge an interactive, intuitive program which provides data analysis instantly. At the end of this chapter EEG computational evaluation with the use of pattern recognition methods as well as the intuition of author's future work in relevance with the use of experimental multimedia technologies to enhance the dynamic recognition and evaluation of user cognitive responses during EEG implementation are noted.
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Davis, Jon, and Elizabeth Chang. "Variant Logic for Model Driven Applications." In Application Development and Design. IGI Global, 2018. http://dx.doi.org/10.4018/978-1-5225-3422-8.ch043.
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Customizing Enterprise Information Systems (EIS) scale applications can be very expensive, also incurring additional costs during their lifecycle when customizations may need to be re-engineered to suit each EIS upgrade. The ongoing development of a temporal meta-data framework for EIS applications seeks to overcome these issues, with the application logic model supporting the capability for end users to define their own supplemental or replacement application logic meta-data, as what the authors term Variant Logic, to become a variation of the core application logic. Variant Logic can be applied to any defined model object whether visual objects, logical processing objects, or data structures objects. Variant Logic can be defined by any authorized user, through modeling rather than coding, executed by any user as an alternative to the original application logic, and is available for immediate execution by the framework runtime engine. Variant Logic is also preserved during automated meta-data application updates.
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Davis, Jon, and Elizabeth Chang. "Optimized and Distributed Variant Logic for Model-Driven Applications." In Application Development and Design. IGI Global, 2018. http://dx.doi.org/10.4018/978-1-5225-3422-8.ch044.
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The customization of Enterprise Information Systems (EIS) is expensive throughout its lifecycle, especially across an enterprise-wide distributed application environment. The authors' ongoing development of a temporal meta-data framework for EIS applications seeks to minimize these issues with the application model supporting the capability for end users to define their own supplemental or alternate application logic as what they term Variant Logic (VL). VL can be applied to any existing model object, defined by any authorized user, through modeling rather than coding, then executed by any user as an alternative to the original application logic. VL is also preserved during automated application updates and can also interoperate directly between similar model-based execution instances within a distributed execution environment, readily sharing the alternate logic segments. The authors also present an enhanced pre-processing architecture that optimizes the execution of Logic Variants to the same execution order of single path model logic.
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Lagerlund, Terrence D. "Digital Signal Processing." In Clinical Neurophysiology. Oxford University Press, 2016. http://dx.doi.org/10.1093/med/9780190259631.003.0015.
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Digital computers can perform types of signal processing not readily available with analog devices, such as ordinary electrical circuits. This includes making the process of obtaining, storing, retrieving, and viewing clinical neurophysiology data easier; aiding in extracting information from waveforms that is not readily obtainable with visual analysis alone; and improving quantification of key features of waveforms. These processes are useful in accurate clinical diagnosis of electroencephalographic (EEG), electromyographic (EMG), and evoked potential studies, and it also lend themselves to serial comparisons between studies performed on the same subject at different times or between two groups of subjects in scientific investigations. Digital computers may also partially automate the interpretation of clinical neurophysiology studies. This chapter reviews the principles of digitization, the design of digitally based instruments for clinical neurophysiology, and several common uses of digital processing, including averaging, digital filtering, and some types of time-domain and frequency-domain analysis.
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Aydi, Y., M. Baklouti, Ph Marquet, M. Abid, and J. L. Dekeyser. "A Design Methodology of MIN-Based Network for MPPSoC on Reconfigurable Architecture." In Reconfigurable Embedded Control Systems. IGI Global, 2011. http://dx.doi.org/10.4018/978-1-60960-086-0.ch009.
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Massive parallel processing systems, particularly Single Instruction Multiple Data architectures, play a crucial role in the field of data intensive parallel applications. One of the primary goals in using these systems is their scalability and their linear increase in processing power by increasing the number of processing units. However, communication networks are the big challenging issue facing researchers. One of the most important networks on chip for parallel systems is the multistage interconnection network. In this paper, we propose a design methodology of multistage interconnection networks for massively parallel systems on chip. The framework covers the design step from algorithm level to RTL. We first develop a functional formalization of MIN-based on-chip network at a high level of abstraction. The specification and the validation of the model have been defined in the logic of ACL2 proving system. The main objective in this step is to provide a formal description of the network that integrates architectural parameters which have a huge impact on design costs. After validating the functional model, step 2 consists in the design and the implementation of the Delta multistage networks on chip dedicated to parallel multi-cores architectures on reconfigurable platforms FPGA. In the last step, we propose an evaluation methodology based on performance and cost metrics to evaluate different topologies of dynamic network through data parallel applications with different number of cores. We also show in the proposed framework that multistage interconnection networks are cost-effective high performance networks for parallel SOCs.
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Devi, Jutika, and Pranayee Datta. "Nanoelectronics." In Handbook of Research on 5G Networks and Advancements in Computing, Electronics, and Electrical Engineering. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-6992-4.ch002.
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The passive circuit elements resistor, inductor, and capacitor, which are the basic building blocks of an electronic circuit, need to be scaled down for application in fifth-generation wireless communication networks. Due to the growing demands in memory and computational capacities of integrated circuits along with high processing and transmission data speed for next-generation, microelectronics will be replaced by nanoelectronics in the future. The concept of nanoscale network on chip system is expected to play an important role in the field of communication systems for designing new devices of ultra-high speed for long and short-range communication links, power efficient computing devices, high-density memory and logic, and ultrafast interconnects. This chapter focuses on the mechanism of tailoring, patterning, and manipulating optical signals using nanometer-scale structures that may play the role of lumped nanocircuit elements at optical domain when selected properly with tremendous promise for application for fifth-generation communication systems.
Conference papers on the topic "Logic circuits – Design – Data processing"
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Min Li and M. S. Hsiao. "RAG: An efficient reliability analysis of logic circuits on graphics processing units." In 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012). IEEE, 2012. http://dx.doi.org/10.1109/date.2012.6176487.
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Lu, Jiaming, Kairen Chen, Lei Zhao, Jiajun Qin, Shubin Liu, and Qi An. "Design of the Time Measurement Circuit, Single Data Frame Sorting, and Packaging Logic of a TOF PET System." In 2020 6th International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP). IEEE, 2020. http://dx.doi.org/10.1109/ebccsp51266.2020.9291352.
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Xu, Zhiqiang, Quan Liu, and Zhengying Li. "Design of Hardware TCP/IP Stack for Sensing Systems Intended for Monitoring of Mechanical Equipment." In ASME 2017 12th International Manufacturing Science and Engineering Conference collocated with the JSME/ASME 2017 6th International Conference on Materials and Processing. American Society of Mechanical Engineers, 2017. http://dx.doi.org/10.1115/msec2017-2641.
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Fiber Bragg grating (FBG) sensors have been widely used in monitoring of the mechanic equipment. However, for measuring high-speed dynamic signal of a large mechanical equipment, the demodulation rate of the interrogator should be very high, while the number of sensors could be tens or hundreds, thus, a large amount of sensing data could be generated. Nonetheless, a network throughput of the interrogator based on the software stack is relatively low and a large amount of data cannot be transmitted simultaneously, which becomes the bottleneck of the sensing system. In order to promote the network throughput, a hardware TCP/IP stack based on the field programmable gate array (FPGA) is proposed. In contrast to the existing hardware stacks, this stack is designed with a new module structure that is divided according to functions instead of protocol types. It can realize both UDP and TCP transmissions with less logic elements than similar designs. Unlike ASIC TCP/IP stack, the entire system can be realized on a single FPGA chip and upgraded without changing of the original hardware circuit. The proposed design has two key features. Firstly, the hardware stack can be connected directly to the data acquisition logic part without software operations thus the data throughput from the signal acquisition to the network transmission can maintain a relatively high speed. Therefore, the system can demodulate data from hundreds of sensors at high speed and transmit them in real time. Secondly, the module structure is clear and independent of specific FPGA platform. Consequently, it can be transplanted or upgraded easily in order to meet different practical demands. The proposed design embodies the characteristics and advantages of the system on a programmable chip (SOPC). In order to validate the proposed design, all logic modules were simulated and the design was tested on the circuit board. Performance test results have shown that UDP and TCP throughputs of the proposed hardware stack are up to 80Mbps in the case of 100Mbps Ethernet controller chip, which is about eight times higher than throughput of software design. Finally the design was verified by monitoring of the oil pipeline platform. The obtained results have shown that proposed design can detect the vibration frequencies of the oil pipeline that are around 600Hz and it can sample 288 FBG sensors and transmit sensor data correctly. Thus the proposed design is suitable for a large sensing system intended for the dynamic monitoring of the mechanical equipment.
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Chen, Hung-Che, Yung-Hua Kao, Paul C. P. Chao, and Chin-Long Wey. "A New Automatic Readout Circuit for a Gas Sensor With Organic Vertical Nano-Junctions." In ASME 2016 Conference on Information Storage and Processing Systems. American Society of Mechanical Engineers, 2016. http://dx.doi.org/10.1115/isps2016-9582.
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The design of the proposed readout circuit provides benefits of detection speed, portability, low-cost and less human operational errors compared with the measurement by traditional instruments. Thus the added value is brought for biosensors and applied in home care. A novel readout circuit for a gas sensor based on an organic diode with vertical nano-junctions (VNJ) is proposed in this study. There are seven parts included in the readout system. First part is a preamplifier, second part is a peak-detect-and-hold circuit, third part is a divider, fourth part is the saturation detector, fifth part is the auto-reset circuit, sixth part is a logic gate and a buffer, seventh part is a micro-processor control unit (MCU). STM32 is the CPU of proposed MCU by ALIENTEK. The ADC of MCU is used to transform the output data of readout circuit. The designed circuit is accomplished by Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 μm 2P4M 3.3 V mixed signal CMOS process, the area of chip is 0.74×0.75 mm2. Finally, the differences between experimental results with post-simulation results in 10 ppb ∼ 3 ppm of ammonia, the differences are within 7.24%. The sensing system is able to detect minimum ammonia concentration of 10 ppb, while the maximum one reaches around 3 ppm.
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Mandal, Sarojini, Jayee Sinha, and Amlan Chakraborty. "Design of Memristor – CMOS based logic gates and logic circuits." In 2019 2nd International Conference on Innovations in Electronics, Signal Processing and Communication (IESC). IEEE, 2019. http://dx.doi.org/10.1109/iespc.2019.8902355.
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Bokare, Ulka M., and Y. A. Gaidhani. "Design of CMOS dynamic logic circuits to improve noise immunity." In 2017 International Conference on Communication and Signal Processing (ICCSP). IEEE, 2017. http://dx.doi.org/10.1109/iccsp.2017.8286740.
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de Bakker, P., A. Delaruelle, and B. de Loore. "Design of a PLU (Programmable Logic Unit), a new block for signal processing." In Fourteenth European Solid-State Circuits Conference. IEEE, 1988. http://dx.doi.org/10.1109/esscirc.1988.5468447.
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Yang, Kai, Robert Karam, and Swarup Bhunia. "Interleaved logic-in-memory architecture for energy-efficient fine-grained data processing." In 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2017. http://dx.doi.org/10.1109/mwscas.2017.8052947.
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Alaybeyoglu, Aysegul, and Berat Can Senel. "A design of fuzzy logic based android application for safe driving." In 2017 International Artificial Intelligence and Data Processing Symposium (IDAP). IEEE, 2017. http://dx.doi.org/10.1109/idap.2017.8090192.
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Wang, Qi. "Architecture Design of Mass Data Processing Mode." In 2011 Third Pacific-Asia Conference on Circuits, Communications and System (PACCS). IEEE, 2011. http://dx.doi.org/10.1109/paccs.2011.5990096.
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