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Dissertations / Theses on the topic 'Logic circuits'
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Parameswaran, Nair Ravi Sankar. "Delay-insensitive ternary logic (DITL)." Diss., Rolla, Mo. : University of Missouri-Rolla, 2007. http://scholarsmine.umr.edu/thesis/pdf/Parameswaran_Nair_09007dcc803bc548.pdf.
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Thesis (M.S.)--University of Missouri--Rolla, 2007.Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 27, 2007) Includes bibliographical references (p. 55-56).
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Silva, Augusto Neutzling. "Syhthesis of thereshold logic based circuits." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/119435.
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Circuitos baseados em portas lógicas de limiar (threshold logic gates – TLG) vem sendo estudados como uma alternativa promissora em relação ao tradicional estilo lógico CMOS, baseado no operadores AND e OR, na construção de circuitos integrados digitais. TLGs são capazes de implementar funções Booleanas mais complexas em uma única porta lógica. Diversos novos dispositivos, candidatos a substituir o transistor MOS, não se comportam como chaves lógicas e são intrinsicamente mais adequados à implementação de TLGs. Exemplos desses dispositivos são os memristores, spintronica, diodos de tunelamento ressonante (RTD), autômatos celulares quânticos (QCA) e dispositivos de tunelamento de elétron único (SET). Para o desenvolvimento de um fluxo de projeto de circuitos integrados baseados em lógica threshold, duas etapas são fundamentais: (1) identificar se uma dada função Booleana corresponde a uma função lógica threshold (TLF), isto é, pode ser implementada em um único TLG e computar os pesos desse TLG; (2) se uma função não é identificada como TLF, outro método de síntese lógica deve construir uma rede de TLGs otimizada que implemente a função. Este trabalho propõe métodos para atacar cada um desses dois problemas, e os resultados superam os métodos do estado-da-arte. O método proposto para realizar a identificação de TLFs é o primeiro método heurístico capaz de identificar todas as funções de cinco e seis variáveis, além de identificar mais funções que os demais métodos existentes quando o número de variáveis aumenta. O método de síntese de redes de TLGs é capaz de sintetizar circuitos reduzindo o número de portas TLG utilizadas, bem como a profundidade lógica e o número de interconexões. Essa redução é demonstrada através da síntese dos circuitos de avaliação da MCNC em comparação com os métodos já propostos na literatura. Tais resultados devem impactar diretamente na área e desempenho do circuito.In this work, a novel method to synthesize digital integrated circuits (ICs) based on threshold logic gates (TLG) is proposed. Synthesis considering TLGs is quite relevant, since threshold logic has been revisited as a promising alternative to conventional CMOS IC design due to its suitability to emerging technologies, such as resonant tunneling diodes, memristors and spintronics devices. Identification and synthesis of threshold logic functions (TLF) are fundamental steps for the development of an IC design flow based on threshold logic. The first contribution is a heuristic algorithm to identify if a function can be implemented as a single TLG. Furthermore, if a function is not detected as a TLF, the method uses the functional composition approach to generate an optimized TLG network that implements the target function. The identification method is able to assign optimal variable weights and optimal threshold value to implement the function. It is the first heuristic algorithm that is not based on integer linear programming (ILP) that is able to identify all threshold functions with up to six variables. Moreover, it also identifies more functions than other related heuristic methods when the number of variables is more than six. Differently from ILP based approaches, the proposed algorithm is scalable. The average execution time is less than 1 ms per function. The second major contribution is the constructive process applied to generate optimized TLG networks taking into account multiple goals and design costs, like gate count, logic depth and number of interconnections. Experiments carried out over MCNC benchmark circuits show an average gate count reduction of 32%, reaching up to 54% of reduction in some cases, when compared to related approaches.
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Chu, Kan Man. "Cascode voltage switch logic circuits." Thesis, University of British Columbia, 1986. http://hdl.handle.net/2429/26283.
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Cascode voltage switch (CVS) logic is a CMOS circuit technique which has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation and logic flexibility. This thesis presents two new procedures for constructing differential CVS circuits to perform random logic functions. The first procedure makes use of a Karnaugh map and the second procedure is a tabular method based on the Quine-McCluskey approach. Both static and dynamic circuit techniques employing the CVS logic concept are discussed. Some wiring and layout methods based on theoretical graph models are presented to ensure the wirability of CVS circuits. An 8x8 NORA CVS multiplier has been designed using the 3μm CMOS technology of Northern Telecom. The chip measures 4mm by 4mm and simulations indicate that it can be run at a throughput rate of 50MHz.Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
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Thulasi, Raman Sudheer Ram. "Logic Encryption of Sequential Circuits." University of Cincinnati / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1553251689992143.
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Ramirez, Ortiz Rolando. "Circuit design rules for mixed static and dynamic CMOS logic circuits." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp03/NQ37076.pdf.
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Ramirez, Ortiz Rolando Carleton University Dissertation Engineering Electronics. "Circuit design rules for mixed static and dynamics CMOS logic circuits." Ottawa, 1999.
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Sandireddy, Raja Kiran Kumar Reddy Agrawal Vishwani D. "Hierarchical fault collapsing for logic circuits." Auburn, Ala., 2005. http://repo.lib.auburn.edu/EtdRoot/2005/SPRING/Electrical_and_Computer_Engineering/Thesis/SANDIREDDY_RAJA-KIRAN-KUMAR_48.pdf.
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Bystrov, Alexandre. "Optimal testing of multilevel logic circuits." Thesis, Edinburgh Napier University, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.300327.
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Stone, Nicholas Jim. "Single electron memory and logic circuits." Thesis, University of Cambridge, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.621922.
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Blakely, Scott. "Probabilistic Analysis for Reliable Logic Circuits." PDXScholar, 2014. https://pdxscholar.library.pdx.edu/open_access_etds/1860.
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Continued aggressive scaling of electronic technology poses obstacles for maintaining circuit reliability. To this end, analysis of reliability is of increasing importance. Large scale number of inputs and gates or correlations of failures render such analysis computationally complex. This paper presents an accurate framework for reliability analysis of logic circuits, while inherently handling reconvergent fan-out without additional complexity. Combinational circuits are modeled stochastically as Discrete-Time Markov Chains, where propagation of node logic levels and error probability distributions through circuitry are used to determine error probabilities at nodes in the circuit. Model construction is scalable, as it is done so on a gate-by-gate basis.
The stochastic nature of the model lends itself to allow various properties of the circuit to be formally analyzed by means of steady-state properties. Formal verifying the properties against the model can circumvent strenuous simulations while exhaustively checking all possible scenarios for given properties. Small combinational circuits are used to explain model construction, properties are presented for analysis of the system, more example circuits are demonstrated, and the accuracy of the method is verified against an existing simulation method.
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Chiu, Ping-kuen Peter. "Primitive interval labelled net model for logic simulation /." [Hong Kong : University of Hong Kong], 1991. http://sunzi.lib.hku.hk/hkuto/record.jsp?B13177357.
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Kasarabada, Yasaswy V. "Efficient Logic Encryption Techniques for Sequential Circuits." University of Cincinnati / OhioLINK, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1613752483402656.
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Eckhardt, James P. "An investigation of high-performance logic circuitry in BiCMOS." Diss., Georgia Institute of Technology, 1990. http://hdl.handle.net/1853/15759.
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Mallepalli, Samarsen Reddy. "Generic algorithms and NULL Convention Logic hardware implementation for unsigned and signed quad-rail multiplication." Diss., Rolla, Mo. : University of Missouri-Rolla, 2007. http://scholarsmine.umr.edu/thesis/pdf/Mallepalli_09007dcc803c4eec.pdf.
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Thesis (M.S.)--University of Missouri--Rolla, 2007.Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 27, 2007) Includes bibliographical references (p. 66-67).
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Sharratt, A. A. "The design of high-speed bipolar current-switched logic gates." Thesis, University of Huddersfield, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.234781.
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Gaubatz, Donald Almo. "Logic programming analysis of asynchronous digital circuits." Thesis, University of Cambridge, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.386062.
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Williams, Ryan Daniel. "Photonic integrated circuits for optical logic applications." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/42025.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references.
The optical logic unit cell is the photonic analog to transistor-transistor logic in electronic devices. Active devices such as InP-based semiconductor optical amplifiers (SOA) emitting at 1550 nm are vertically integrated with passive waveguides using the asymmetric twin waveguide technique and the SOAs are placed in a Mach-Zehnder interferometer (MZI) configuration. By sending in high-intensity pulses, the gain characteristics, phase-shifting, and refractive indices of the SOA can be altered, creating constructive or deconstructive interference at the MZI output. Boolean logic and wavelength conversion can be achieved using this technique, building blocks for optical switching and signal regeneration. The fabrication of these devices is complex and the fabrication of two generations of devices is described in this thesis, including optimization of the mask design, photolithography, etching, and backside processing techniques. Testing and characterization of the active and passive components is also reported, confirming gain and emission at 1550 nm for the SOAs, as well as verifying evanescent coupling between the active and passive waveguides. In addition to the vertical integration of photonic waveguides, Esaki tunnel junctions are investigated for vertical electronic integration. Quantum dot formation and growth via molecular beam epitaxy is investigated for emission at the technologically important wavelength of 1310 nm. The effect of indium incorporation on tunnel junctions is investigated. The tunnel junctions are used to epitaxially link multiple quantum dot active regions in series and lasers are designed, fabricated, and tested.
by Ryan Daniel Williams.
Ph.D.
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Bhasin, Inderpreet. "Recognition of logic blocks in CMOS circuits." Thesis, Virginia Polytechnic Institute and State University, 1988. http://hdl.handle.net/10919/80044.
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A Prolog based approach towards the recognition of logic functional blocks in CMOS circuits is described in this thesis. A transistor level description of the circuit is assumed to be available. Predefined gates and logic blocks are extracted from such a description. This recognition procedure is a step towards raising the level of description of a network. An extracted block level description can be used to verify the correctness of the implemented logic. The approach described here uses a circuit partitioning technique to divide a given circuit into smaller subcircuits. This is followed by the extraction of logic expressions at the output nodes of subcircuits. From these logic expressions, gates are recognized. Functional blocks in the circuit are recognized based on rules which define such blocks in terms of their structural configuration.Master of Science
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Liu, Tai-hung. "Logic synthesis for high-performance digital circuits /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
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Zejda, Jindrich. "Bounding of switching activity in logic circuits." Thèse, [Montréal] : Université of Montreal, 1999. http://wwwlib.umi.com/dissertations/fullcit/NQ43744.
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Thèse (Ph. D.)--Université de Montréal, 1999.Titre de la p. de t. additionnelle: Détermination des bornes de l'activité de commutation des circuits logiques. Résumé aussi en français. "Thèse présentée à la Faculté des études supérieures en vue de l'obtention du grade de Philosophiae Doctor (Ph. D.) en Informatique"--P. de t. additionnelle. Version électronique également disponible sur Internet.
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Kalganova, Tatiana. "Evolvable hardware design of combinational logic circuits." Thesis, Edinburgh Napier University, 2000. http://researchrepository.napier.ac.uk/Output/4341.
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Evolvable Hardware (EHW), as an alternative method for logic design, became more attractive recently, because of its algebra-independent techniques for generating selfadaptive self-reconfigurable hardware. This thesis investigates and relates both evaluation and evolutionary processes, emphasizing the need to address problems arising from data complexity. Evaluation processes, capable of evolving cost-optimised fully functional circuits are investigated. The need for an extrinsic EHW approach (software models) independent of the concerns of any implementation technologies is emphasized. It is also shown how the function description may be adapted for use in the EHW approach. A number of issues of evaluation process are addressed: these include choice of optimisation criteria, multi-objective optimisation tedmiques in EHW and probabilistic analysis of evolutionary processes. The concept of self-adaptive extrinsic EHW method is developed. This approach emphasizes the circuit layout evolution together with circuit functionality. A chromosome representation for such system is introduced, and a number of genetic operators and evolutionary algorithms in support of this approach are presented. The genetic operators change the genetic material at the different levels of chromosome representation. Furthermore, a chromosome representation is adapted to the function-level EHW approach. As a result, the modularised systems are evolved using multi-output building blocks. This chromosome representation overcomes the problem of long string chromosome. Together, these techniques facilitate the construction of systems to evolve logic functions of large number of variables. A method for achieving this using bidirectional incremental evolution is documented. It is demonstrated that the integration of a dynamic evaluation process and self-adaptive function-level EHW approach allows the bidirectional incremental evolution to successfully evolve more complex systems than traditionally evolved before. Thereby it provides a firm foundation for the evolution of complex systems. Finally, the universality of these techniques is proved by applying them to multivalued combinational logic design. Empirical study of this application shows that there is no fundamental difference in approach for both binary and multi-valued logic design problems.
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PALANISWAMY, ASHOK KUMAR. "SYNTHESIS AND TESTING OF THRESHOLD LOGIC CIRCUITS." OpenSIUC, 2014. https://opensiuc.lib.siu.edu/dissertations/963.
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Threshold logic gates gaining more importance in recent years due to the significant development in the switching devices. This renewed the interest in synthesis and testing of circuits with threshold logic gates. Two important synthesis considerations of threshold logic circuits are addressed namely, threshold logic function identification and reducing the total number of threshold logic gates required to represent the given boolean circuit description. A fast method to identify the given Boolean function as a threshold logic function with weight assignment is introduced. It characterizes the threshold logic function based on the modified chows parameters which results in drastic reduction in time and complexity. Experiment results shown that the proposed method is at least 10 times faster for each input and around 20 times faster for 7 and 8 input, when comparing with the algorithmic based methods. Similarly, it is 100 times faster for 8 input, when comparing with asummable method. Existing threshold logic synthesis methods decompose the larger input functions into smaller input functions and perform synthesis for them. This results in increase in the number of threshold logic gates required to represent the given circuit description. The proposed implicit synthesis methods increase the size of the functions that can be handled by the synthesis algorithm, thus the number of threshold logic gates required to implement very large input function decreases. Experiment results shown that the reduction in the TLG count is 24% in the best case and 18% on average. An automatic test pattern generation approach for transition faults on a circuit consisting of current mode threshold logic gates is introduced. The generated pattern for each fault excites the maximum propagation delay at the gate (the fault site). This is a high quality ATPG. Since current mode threshold logic gate circuits are pipelined and the combinational depth at each pipeline stage is practically one. It is experimentally shown that the fault coverage for all benchmark circuits is approximately 97%. It is also shown that the proposed method is time efficient.
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Ramakrishnan, Lakshmi Narasimhan. "SDMLp - Secure Differential Multiplexer Logic : Logic Design for DPA-Resistant Cryptographic Circuits." University of Cincinnati / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1311691925.
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Young, Fung Yu. "Algorithms for the design of VLSI floorplans and logic modules /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
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Wood, Kenneth Robert. "Parallel logic simulation and applied formal methods." Thesis, University of Oxford, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.315774.
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Gittings, Christopher Jeremy John. "Parallel demand - driven simulation of logic networks." Thesis, University of Liverpool, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.316981.
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Duncan, Austin H. "Logic Gates Using the Digilent Basys3." Digital Commons @ East Tennessee State University, 2015. https://dc.etsu.edu/honors/311.
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ENTC 3370 teaches students the basics of digital circuits. Until recently the students were taught using an analog device called a Protoboard. With the acquisition of the Digilent Basys3, a digital device, the class will begin to be taught using digital modeling techniques. This is a collection of lab activities designed to be used with the Basys3 within the class. The activities were designed in a way so that students with little programming knowledge could complete the tasks.
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Wist, Dominic. "Attacking complexity in logic synthesis of asynchronous circuits." Phd thesis, Universität Potsdam, 2011. http://opus.kobv.de/ubp/volltexte/2012/5970/.
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Most of the microelectronic circuits fabricated today are synchronous, i.e. they are driven by one or several clock signals. Synchronous circuit design faces several fundamental challenges such as high-speed clock distribution, integration of multiple cores operating at different clock rates, reduction of power consumption and dealing with voltage, temperature, manufacturing and runtime variations. Asynchronous or clockless design plays a key role in alleviating these challenges, however the design and test of asynchronous circuits is much more difficult in comparison to their synchronous counterparts.
A driving force for a widespread use of asynchronous technology is the availability of mature EDA (Electronic Design Automation) tools which provide an entire automated design flow starting from an HDL (Hardware Description Language) specification yielding the final circuit layout. Even though there was much progress in developing such EDA tools for asynchronous circuit design during the last two decades, the maturity level as well as the acceptance of them is still not comparable with tools for synchronous circuit design. In particular, logic synthesis (which implies the application of Boolean minimisation techniques) for the entire system's control path can significantly improve the efficiency of the resulting asynchronous implementation, e.g. in terms of chip area and performance. However, logic synthesis, in particular for asynchronous circuits, suffers from complexity problems.
Signal Transitions Graphs (STGs) are labelled Petri nets which are a widely used to specify the interface behaviour of speed independent (SI) circuits - a robust subclass of asynchronous circuits.
STG decomposition is a promising approach to tackle complexity problems like state space explosion in logic synthesis of SI circuits. The (structural) decomposition of STGs is guided by a partition of the output signals and generates a usually much smaller component STG for each partition member, i.e. a component STG with a much smaller state space than the initial specification.
However, decomposition can result in component STGs that in isolation have so-called irreducible CSC conflicts (i.e. these components are not SI synthesisable anymore) even if the specification has none of them. A new approach is presented to avoid such conflicts by introducing internal communication between the components.
So far, STG decompositions are guided by the finest output partitions, i.e. one output per component. However, this might not yield optimal circuit implementations. Efficient heuristics are presented to determine coarser partitions leading to improved circuits in terms of chip area.
For the new algorithms correctness proofs are given and their implementations are incorporated into the decomposition tool DESIJ. The presented techniques are successfully applied to some benchmarks - including 'real-life' specifications arising in the context of control resynthesis - which delivered promising results.Moderner Schaltungsentwurf fokussiert hauptsächlich synchrone Schaltungstechnik mit allen inhärenten Problemen. Asynchone (d.h. ungetaktete) Schaltungen zeichnen sich jedoch nicht nur durch das Fehlen der Taktversatzproblematik gegenüber ihren synchronen Pendents aus, sondern auch insbesondere durch geringeren Energieverbrauch, günstigere EMV-Eigenschaften, hohe Performance, Modularität und Robustheit gegenüber Schwankungen in der Spannungsversorgung, im Herstellungsprozess sowie Temperaturunterschieden. Diese Vorteile werden mit höherer Integration sowie höheren Taktraten signifikanter. Jedoch ist der Entwurf und auch der Test asynchroner Schaltungen erheblich schwieriger verglichen mit synchronen Schaltungen. Entwurfswerkzeuge zur Synthese asynchroner Schaltungen aus Hochsprachen-Spezifikationen sind zwar inzwischen verfügbar, sie sind jedoch noch nicht so ausgereift und bei weitem noch nicht so akzeptiert in der Industrie, wie ihre Äquivalente für den synchronen Schaltungsentwurf. Insbesondere fehlt es an Werkzeugunterstützung im Bereich der Logiksynthese komplexer Steuerungen („Controller“), welche kritisch für die Effizienz – z.B. in Bezug auf Chipfläche und Geschwindigkeit – der resultierenden Schaltungen oder Systeme ist. Zur Spezifikation von Steuerungen haben sich Signalflankengraphen („signal transition graphs“, STGs) bewährt, die auch als Entwurfseinstieg für eine Logiksynthese von SI-Schaltungen („speed independent“) verwendet werden. (SI-Schaltungen gelten als sehr robuste asynchrone Schaltungen.) Aus den STGs werden zwecks Logiksynthese Automaten abgeleitet werden, deren Zustandszahl aber oft prohibitiv groß werden kann. Durch sogenannte STG-Dekomposition wird die Logiksynthese einer komplexen Schaltung ermöglicht, was bislang aufgrund von Zustandsexplosion oft nicht möglich war. Dabei wird der Spezifikations-STG laut einer gegebenen Partition von Ausgangssignalen in viele kleinere Teilnetze dekomponiert, wobei zu jedem Partitionsblock ein Teilnetz – mit normalerweise signifikant kleinerem Zustandsraum im Vergleich zur Spezifikation – erzeugt wird. Zu jedem Teilnetz wird dann eine Teilschaltung (Komponente) mittels Logiksynthese generiert. Durch die Anwendung von STG-Dekomposition können jedoch Teilnetze erzeugt werden, die sogenannte irreduzible CSC-Konflikte aufweisen (d.h. zu diesen Teilnetzen kann keine SI-Schaltung erzeugt werden), obwohl die Spezifikation keine solchen Konflikte hatte. Diese Arbeit präsentiert einen neuen Ansatz, welcher die Entstehung solcher irreduziblen Konflikte vermeidet, und zwar durch die Einführung interner Kommunikation zwischen den (zu den Teilnetzen gehörenden) Schaltungskomponenten. Bisher werden STG-Dekompositionen total durchgeführt, d.h. pro resultierender Komponente wird ein Ausgangssignal erzeugt. Das führt gewöhnlich nicht zu optimalen Schaltungsimplementierungen. In dieser Arbeit werden Heuristiken zur Bestimmung gröberer Ausgabepartitionen (d.h. Partitionsblöcke mit mehreren Ausgangssignalen) vorgestellt, die zu kleineren Schaltungen führen. Die vorgestellten Algorithmen werden formal abgesichert und wurden in das bereits vorhandene Dekompositionswerkzeug DESIJ integriert. An praxisrelevanten Beispielen konnten die vorgestellten Verfahren erfolgreich erprobt werden.
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Robinson, David. "Simulation and control of dynamically reconfigurable logic circuits." Thesis, University of Strathclyde, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.273380.
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Ma, Albert. "Circuits for high-performance low-power VLSI logic." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37906.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 85-88).
The demands of future computing, as well as the challenges of nanometer-era VLSI design, require new digital logic techniques and styles that are simultaneously high performance, energy efficient, and robust to noise and variation. We propose a new family of logic styles called Preset Skewed Static Logic (PSSL). PSSL bridges the gap between the two main logic styles, static CMOS logic and domino logic, occupying an intermediate region in the energy-delay-robustness space between the two. PSSL is better than domino in terms of energy and robustness, and is better than static CMOS in terms of delay. PSSL works by partially overlapping the execution of consecutive iterations through speculative evaluation. This is accomplished by presetting nodes at register boundaries before input arrival.
by Albert Ma.
Ph.D.
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Le, Son Ngoc. "Formal Verification Methodologies for NULL Convention Logic Circuits." Diss., North Dakota State University, 2020. https://hdl.handle.net/10365/31875.
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NULL Convention Logic (NCL) is a Quasi-Delay Insensitive (QDI) asynchronous design paradigm that aims to tackle some of the major problems synchronous designs are facing as the industry trend of increased clock rates and decreased feature size continues. The clock in synchronous designs is becoming increasingly difficult to manage and causing more power consumption than ever before. NCL circuits address some of these issues by requiring less power, producing less noise and electro-magnetic interference, and being more robust to Process, Voltage, and Temperature (PVT) variations. With the increase in popularity of asynchronous designs, a formal verification methodology is crucial for ensuring these circuits operate correctly. Four automated formal verification methodologies have been developed, three to ensure delay-insensitivity of an NCL circuit (i.e., prove Input-Completeness, Observability, and Completion-Completeness properties), and one to aid in proving functional equivalence between an NCL circuit and its synchronous counterpart. Note that an NCL circuit can be functionally correct and still not be input-complete, observable, or completion-complete, which could cause the circuit to operate correctly under normal conditions, but malfunction when circuit timing drastically changes (e.g., significantly reduced supply voltage, extreme temperatures). Since NCL circuits are implemented using dual-rail logic (i.e., 2 wires, rail0 and rail1, represent one bit of data), part of the functional equivalence verification involves ensuring that the NCL rail0 logic is the inverse of its rail1 logic. Equivalence verification optimizations and alternative invariant checking methods were investigated and proved to decrease verification times of identical circuits substantially. This work will be a major step toward NCL circuits being utilized more frequently in industry, since it provides an automated verification method to prove correctness of an NCL implementation and equivalence to its synchronous specification, which is the industry standard.
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Modi, Manish Harsukh. "Susceptibility evaluation of combational logic in VLSI circuits." Thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/42221.
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A number of errors occur in digital systems operating in a harsh radiation environment. These errors are due to transient faults which may cause a temporary change in the state of the system without any permanent damage. These transient faults are referred to as Single Event Upsets (SEUs). Because of their random and non-recurring nature, such faults are very difficult to detect and hence are of source of great concern.
This thesis examines the logical response of combinational logic circuits to SEUs. Time domain analyses of a large number of circuits attempts to determine the affect of an SEU on a flip-flop which might lay at the end of a chain of combinational logic gates. In this way, the concept of an upset window, as it pertains to different types of logic gates is introduced. The results of the simulations carried out on various blocks of combinational logic are discussed. A program called SUPER (SUsceptibility PrEdiction pRogram) is developed. SUPER predicts the probability of a circuit fault occurring given that a cosmic ray with certain energy characteristics impinges on an arbitrary point within an IC. IC. The input variables to SUPER include the radiation level, the duration of the radiation, the types of gates the radiation affects, the signal path, the type of voltage pulse that the radiation produces (rising or falling) and the time (with respect to the clock pulse) that the radiation is incident on the circuit. The output of SUPER consists of a prediction as to whether or not the incident radiation causes a change in the output of a flip-flop.Master of Science
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Shi, Ming Yu. "Organic logic circuits : fabrication process and device optimisation." Thesis, University of Manchester, 2012. https://www.research.manchester.ac.uk/portal/en/theses/organic-logic-circuits-fabrication-process-and-device-optimisation(6dee3a75-f681-4493-9a06-68462bd58fe9).html.
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Initial research in the field of organic electronics focused primarily on the improvements in material performance. Significant progress has been achieved in the case of organic field effect transistors, where reported mobility values are now over 5 orders of magnitude higher than those of early devices. As a consequence, the use of organic transistors is now being considered for real-world applications in the form of integrated logic circuits. This in turn presents many new challenges, as the logic circuit requirements are more demanding on the transistor characteristics and corresponding fabrication processes. This thesis investigates the feasibility of organic technology for its potential use in future low-cost, high-volume electronic applications. The research objectives were accomplished by practical evaluation of an organic logic circuit fabrication process. First, recent advances in the fabrication of organic circuits in terms of transistor structure, material usage and fabrication techniques are reviewed. Next, a lithographic logic circuit fabrication process using PVP gate dielectric and TIPS-pentacene organic semiconductor adapted from state of the art fabrication process is presented. The logic circuit design decisions and the methodology for the fabrication process are thoroughly documented. Using this process, zero-Vgs and diode-load inverter circuits were successfully fabricated. However, the process is in need of further refinement for more complex circuit designs, as the fabrication of a comparator circuit consisting of 11 transistors was unsuccessful. Two optimisation techniques that are compatible with the logic circuit fabrication process were also explored in this work. To improve the capacitive coupling of the dielectric layer, the use of a polymer nanocomposite dielectric was investigated. The nanocomposite is prepared by blending PVP solution with a high-k inorganic nanoparticle filler, barium strontium titanate. Using the nanocomposite dielectric, both single transistors and integrated logic circuits were successfully fabricated. This is the first report on the use of PVP and barium strontium titanate nanocomposite dielectric with a lithographic based logic circuit fabrication process. The use of PFBT modified Au contacts for the fabrication process was investigated to improve theperformance of the contact electrode layer. Using PFBT, mobility increased by one order of magnitude over untreated Au electrodes for the PVP and TIPS-pentacene transistors.
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Ramirez, Ortiz Rolando Carleton University Dissertation Engineering Electrical. "Technology mapping algorithms for CMOS dynamic logic circuits." Ottawa, 1992.
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Wang, Lingli. "Automated synthesis and optimization of multilevel logic circuits." Thesis, Edinburgh Napier University, 2000. http://researchrepository.napier.ac.uk/Output/4342.
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With the increased complexity of Very Large Scaled Integrated (VLSI) circuits, multilevel logic synthesis plays an even more important role due to its flexibility and compactness. The history of symbolic logic and some typical techniques for multilevel logic synthesis are reviewed. These methods include algorithmic approach; Rule-Based approach; Binary Decision Diagram (BDD) approach; Field Programmable Gate Array(FPGA) approach and several perturbation applications. One new kind of don't cares (DCs), called functional DCs has been proposed for multilevel logic synthesis. The conventional two-level cubes are generalized to multilevel cubes. Then functional DCs are generated based on the properties of containment. The concept of containment is more general than unateness which leads to the generation of new DCs. A separate C program has been developed to utilize the functional DCs generated as a Boolean function is decomposed for both single output and multiple output functions. The program can produce better results than script.rugged of SIS, developed by UC Berkeley, both in area and speed in less CPU time for a number of testcases from MCNC and IWLS'93 benchmarks. In certain applications ANDjXOR (Reed-Muller) logic has shown some attractive advantages over the standard Boolean logic based on AND JOR operations. A bidirectional conversion algorithm between these two paradigms is presented based on the concept of polarity for sum-of-products (SOP) Boolean functions, multiple segment and multiple pointer facilities. Experimental results show that the algorithm is much faster than the previously published programs for any fixed polarity. Based on this algorithm, a new technique called redundancy-removal is applied to generalize the idea to very large multiple output Boolean functions. Results for benchmarks with up to 199 inputs and 99 outputs are presented. Applying the preceding conversion program, any Boolean functions can be expressed by fixed polarity Reed-Muller forms. There are 2n polarities for an n-variable function and the number of product terms depends on these polarities. The problem of exact polarity minimization is computationally extensive and current programs are only suitable when n :::; 15. Based on the comparison of the concepts of polarity in the standard Boolean logic and Reed-Muller logic, a fast algorithm is developed and implemented in C language which can find the best polarity for multiple output functions. Benchmark examples of up to 25 inputs and 29 outputs run on a personal computer are given. After the best polarity for a Boolean function is calculated, this function can be further simplified using mixed polarity methods by combining the adjacent product terms. Hence, an efficient program is developed based on decomposition strategy to implement mixed polarity minimization for both single output and very large multiple output Boolean functions. Experimental results show that the numbers of product terms are much less than the results produced by ESPRESSO for some categories of functions.
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Xia, Yinshui. "Low power design techniques for digital logic circuits." Thesis, Edinburgh Napier University, 2003. http://researchrepository.napier.ac.uk/Output/6887.
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With the rapid increase in the density and the size of chips and systems, area and power dissipation become critical concern in Very Large Scale Integrated (VLSI) circuit design. Low power design techniques are essential for today's VLSI industry. The history of symbolic logic and some typical techniques for finite state machine (FSM) logic synthesis are reviewed. The state assignment is used to optimize area and power dissipation for FSMs. Two cost functions, targeting area and power, are presented. The Genetic Algorithm (GA) is used to search for a good state assignment to minimize the cost functions. The algorithm has been implemented in C. The program can produce better results than NOVA, which is integrated into SIS by DC Berkeley, and other publications both in area and power tested by MCNC benchmarks. Flip-flops are the core components of FSMs. The reduction of power dissipation from flip-flops can save power for digital systems significantly. Three new kinds of flip-flops, called differential CMOS single edge-triggered flip-flop with clock gating, double edge-triggered and multiple valued flip-flops employing multiple valued clocks, are proposed. All circuits are simulated using PSpice. Most researchers have focused on developing low-power techniques in AND/OR or NAND & NOR based circuits. The low power techniques for AND /XOR based circuits are still in their early stage of development. To implement a complex function involving many inputs, a form of decomposition into smaller subfunctions is required such that the subfunctions fit into the primitive elements to be used in the implementation. Best polarity based XOR gate decomposition technique has been developed, which targets low power using Huffman algorithm. Compared to the published results, the proposed method shows considerable improvement in power dissipation. Further, Boolean functions can be expressed by Fixed Polarity Reed-Muller (FPRM) forms. Based on polarity transformation, an algorithm is developed and implemented in C language which can find the best polarity for power and area optimization. Benchmark examples of up to 21 inputs run on a personal computer are given.
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Evans, Richard J. "Detecting bridging faults in CMOS circuits." Thesis, University of Oxford, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.291084.
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趙炳權 and Ping-kuen Peter Chiu. "Primitive interval labelled net model for logic simulation." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1991. http://hub.hku.hk/bib/B31232541.
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Hacker, Charles Hilton, and n/a. "WinLogiLab - A Computer-Based Teaching Suite for Digital Logic Design." Griffith University. School of Engineering, 2001. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20050915.172404.
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This thesis presents an interactive computerised teaching suite developed for the design of combinatorial and sequential logic circuits. This suite fills a perceived gap in the currently available computer-based teaching software for digital logic design. Several existing digital logic educational software are available, however these existing programs were found to be unsuitable for our use in providing alternative mode subject delivery. This prompted the development of a Microsoft Windows TM tutorial suite, called WinLogiLab. WinLogiLab comprises of a set of tutorials that uses student provided input data, to perform the initial design steps for digital Combinatorial and Sequential logic circuits. The combinatorial tutorials are designed to show the link between Boolean Algebra and Digital Logic circuits, and follows the initial design steps: from Boolean algebra, truth tables, to Exact and the Heuristic minimisation techniques, to finally produce the combinatorial circuit. Similarly, the sequential tutorials can design simple State Machine Counters, and can model more complex Finite State Automata.
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Hacker, Charles. "WinLogiLab - A Computer-Based Teaching Suite for Digital Logic Design." Thesis, Griffith University, 2001. http://hdl.handle.net/10072/367209.
Full textAbstract:
This thesis presents an interactive computerised teaching suite developed for the design of combinatorial and sequential logic circuits. This suite fills a perceived gap in the currently available computer-based teaching software for digital logic design. Several existing digital logic educational software are available, however these existing programs were found to be unsuitable for our use in providing alternative mode subject delivery. This prompted the development of a Microsoft Windows TM tutorial suite, called WinLogiLab. WinLogiLab comprises of a set of tutorials that uses student provided input data, to perform the initial design steps for digital Combinatorial and Sequential logic circuits. The combinatorial tutorials are designed to show the link between Boolean Algebra and Digital Logic circuits, and follows the initial design steps: from Boolean algebra, truth tables, to Exact and the Heuristic minimisation techniques, to finally produce the combinatorial circuit. Similarly, the sequential tutorials can design simple State Machine Counters, and can model more complex Finite State Automata.Thesis (Masters)
Master of Philosophy (MPhil)
School of Engineering
Science, Environment, Engineering and Technology
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Roberts, M. W. "Logic circuit testability for reconvergent fan-out nodes." Thesis, University of York, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.374197.
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Saul, Jonathan. "Logic synthesis based on the Reed-Muller representation." Thesis, University of Bristol, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.357962.
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Chong, Kian Haur. "Self-calibrating differential output prediction logic /." Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/5985.
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Kim, Dongho. "Power estimation for combinational logic and low power design /." Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3008367.
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Yee, Gin Sun. "Dynamic logic design and synthesis using clock-delayed domino /." Thesis, Connect to this title online; UW restricted, 1999. http://hdl.handle.net/1773/6039.
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Nguyen, Loc Bao. "Logic design using programmable logic devices." PDXScholar, 1988. https://pdxscholar.library.pdx.edu/open_access_etds/4103.
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The Programmable Logic Devices, PLO, have caused a major impact in logic design of digital systems in this decade. For instance, a twenty pin PLO device can replace from three hundreds to six hundreds Transistor Transistor Logic gates, which people have designed with since the 60s. Therefore, by using PLD devices, designers can squeeze more features, reduce chip counts, reduce power consumption, and enhance the reliability of the digital systems.
This thesis covers the most important aspects of logic design using PLD devices. They are Logic Minimization and State Assignment. In addition, the thesis also covers a seldomly used but very useful design style, Self-Synchronized Circuits.
The thesis introduces a new method to minimize Two-Level Boolean Functions using Graph Coloring Algorithms and the result is very encouraging. The raw speed of the coloring algorithms is as fast as the Espresso, the industry standard minimizer from Berkeley, and the solution is equally good.
The thesis also introduces a rule-based state assignment method which gives equal or better solutions than STASH (an Intel Automatic CAD tool) by as much as twenty percent.
One of the problems with Self-Synchronized circuits is that it takes many extra components to implement the circuit. The thesis shows how it can be designed using PLD devices and also suggests the idea of a Clock Chip to reduce the chip count to make the design style more attractive.
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Lee, Hoon S. "A CAD tool for current-mode multiple-valued CMOS circuits." Thesis, Monterey, California. Naval Postgraduate School, 1988. http://hdl.handle.net/10945/22935.
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Approved for public release; distribution is unlimitedThe contribution of this thesis is the development of a CAD (computer aided design) tool for current mode multiple-valued logic (MVL) CMOS circuits. It is only the second known MVL CAD tool and the first CAD tool for MVL CMOS. The tool accepts a specification of the function to be realized by the user, produces a minimal or near-minimal realization (if such a realization is possible), and produces a layout of a programmable logic array (PLA) integrated circuit that realizes the given function. The layout is in MAGIC format, suitable for submission to a chip manufacturer. The CAD tool also allows the user to simulate the realized function so that he/she can verify correctness of design. The CAD tool is designed also to be an analysis tool for heuristic minimization algorithms. As part of this thesis, a random function generator and statistics gathering package were developed. In the present tool, two heuristics are provided and the user can choose one or both. In the latter case, the better realization is output to the user. The CAD tool is designed to be flexible, so that future improvements can be made in the heuristic algorithms, as well as the layout generator. Thus, the tool can be used to accommodate new technologies, for example, a voltage mode CMOS PLA rather than the current mode CMOS currently implemented.
http://archive.org/details/cadtoolforcurren00leeh
Lieutenant, Republic of Korea Navy
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Nayeem, Noor Muhammed. "Synthesis and testing of reversible Toffoli circuits." Thesis, Lethbridge, Alta. : University of Lethbridge, Dept. of Mathematics and Computer Science, c2012, 2012. http://hdl.handle.net/10133/3309.
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Recently, researchers have been interested in reversible computing because of its ability to
dissipate nearly zero heat and because of its applications in quantum computing and low
power VLSI design. Synthesis and testing are two important areas of reversible logic. The
thesis first presents an approach for the synthesis of reversible circuits from the exclusive-
OR sum-of-products (ESOP) representation of functions, which makes better use of shared
functionality among multiple outputs, resulting in up to 75% minimization of quantum cost
compared to the previous approach. This thesis also investigates the previous work on constructing
the online testable circuits and points out some design issues. A simple approach
for online fault detection is proposed for a particular type of ESOP-based reversible circuit,
which is also extended for any type of Toffoli circuits. The proposed online testable designs
not only address the problems of the previous designs but also achieve significant improvements
of up to 78% and 99% in terms of quantum cost and garbage outputs, respectively.xii, 82 leaves : ill. ; 29 cm
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Sun, Sheng. "High performance and energy efficient adder design /." Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/5865.
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Del, Duce A. "Quantum Logic circuits for solid-state quantum information processing." Thesis, University College London (University of London), 2010. http://discovery.ucl.ac.uk/20166/.
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This thesis describes research on the design of quantum logic circuits suitable for the experimental demonstration of a three-qubit quantum computation prototype. The design is based on a proposal for optically controlled, solid-state quantum logic gates. In this proposal, typically referred to as SFG model, the qubits are stored in the electron spin of donors in a solid-state substrate while the interactions between them are mediated through the optical excitation of control particles placed in their proximity. After a brief introduction to the area of quantum information processing, the basics of quantum information theory required for the understanding of the thesis work are introduced. Then, the literature on existing quantum computation proposals and experimental implementations of quantum computational systems is analysed to identify the main challenges of experimental quantum computation and typical system parameters of quantum computation prototypes. The details of the SFG model are subsequently described and the entangling characteristics of SFG two-qubit quantum gates are analysed by means of a geometrical approach, in order to understand what entangling gates would be available when designing circuits based on this proposal. Two numerical tools have been developed in the course of the research. These are a quantum logic simulator and an automated quantum circuit design algorithm based on a genetic programming approach. Both of these are used to design quantum logic circuits compatible with the SFG model for a three-qubit Deutsch-Jozsa algorithm. One of the design aims is to realise the shortest possible circuits in order to reduce the possibility of errors accumulating during computation, and different design procedures which have been tested are presented. The tolerance to perturbations of one of the designed circuits is then analysed by evaluating its performance under increasing fluctuations on some of the parameters relevant in the dynamics of SFG gates. Because interactions in SFG two-qubit quantum gates are mediated by the optical excitation of the control particles, the solutions for the generation of the optical control signal required for the proposed quantum circuits are discussed. Finally, the conclusions of this work are presented and areas for further research are identified.