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Journal articles on the topic 'Logic circuits'
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1
Jin, Chen. "A review on multiple-valued logic circuits." Applied and Computational Engineering 43, no. 1 (2024): 322–26. http://dx.doi.org/10.54254/2755-2721/43/20230857.
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Since the traditional binary logic has several disadvantages including inaccuracy, high complexity, and limited applications. Multiple-Valued Logic (MVL), which can store more information in one digit than binary logics, require less number of logic gates and take the third value in practical logic problems, is developed and introduced. More information stored per digit leads to higher computational efficiency. Less logic gates results in more spaces on the circuit board. Considering the third value means higher accuracy. In this research, some examples of different MVL circuit are designed to give a rough picture of current research in this domain. These designs are based on ternary and quaternary logics rather than binary logics. Besides, reliability evaluation through mathematical approach is presented in order to prove that the new design is more preferable. This can be carried out with mathematical analysis such as calculating a matrix that reflects its reliability, and simulating different designs to obtain certain values and comparing them with each other. Despite facing various challenges, including complicated physical implementation and difficulty to modulate the signals. This means that there is still potential of further research in this domain of logic circuits. This result in the conclusion that the MVL logic circuits will replace the conventional binary logic circuits in the future, and probably that decimal logic would be developed and no binary-to-decimal conversion unit will be required.
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Patel, Ambresh, and Ritesh Sadiwala. "Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 15, no. 01 (2023): 91–95. http://dx.doi.org/10.18090/10.18090/samriddhi.v15i01.13.
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The demand for VLSI low voltage high-performance low power systems are increasing significantly. Today's deviceapplications necessitate a system that consumes little power and conserves performance. Recent battery-powered lowvoltagedevices optimize power and high-speed constraints. Aside from that, there is a design constraint with burst-modetype integrated circuits for small devices to scale down. Low voltage low power static CMOS logic integrated circuitsoperate at a slower rate and cannot be used in high performance circuits. As a result, dynamic CMOS logic is used inintegrated circuits because it requires fewer transistors, has lower parasitic capacitance, is faster, and enables pipelinedsystem architecture with glitch-free circuits. It has, however, increased power dissipation. Both types of CMOS circuits withlow power dissipation overcome their own shortcomings.This paper discusses dynamic CMOS logic circuits and their structures. Various logics are also discussed and on the basisof the results obtained, logic which is best suited for designing CMOS logic circuit will be found out. The logic on the basisof structure layout and design which gives best results for high-speed VLSI circuits, is found out.
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Bundalo, Dusanka, Zlatko Bundalo, and Branimir Ðordjevic. "Design of quaternary logic systems and circuits." Facta universitatis - series: Electronics and Energetics 18, no. 1 (2005): 45–56. http://dx.doi.org/10.2298/fuee0501045b.
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The principles and possibilities of design of fully quaternary multiple valued combinational logic systems and circuits are described and proposed in the paper. Different ways of design of fully quaternary combinational logic systems and circuits are considered and described first. Then algorithm for automated computerized design of such systems and circuits is considered and proposed. The algorithm gives possibility for synthesis and optimization of quaternary logic systems and circuits. It is applied on design of CMOS quaternary multiple valued logic systems and circuits. The algorithm includes the most important aspects of design of quaternary logic circuits: logic circuit scheme synthesis and logic circuit optimization. Methods for synthesis of quaternary CMOS combinational logic circuits are proposed and described. Also, method for optimization of CMOS quaternary logic circuits, according to operation conditions and needed characteristics, is proposed and described. Design procedure is realized by personal computer using PSPICE for circuit simulation. Computer PSPICE simulation results confirming described methods and conclusions are given in the paper.
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Bansal, Deepika, Brahmadeo Prasad Singh, and Ajay Kumar. "Stack Contention-alleviated Precharge Keeper for Pseudo Domino Logic." Bulletin of Electrical Engineering and Informatics 6, no. 2 (2017): 122–32. http://dx.doi.org/10.11591/eei.v6i2.597.
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The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.
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Upadhyay, Shipra, R. A. Mishra, R. K. Nagaria, and S. P. Singh. "DFAL: Diode-Free Adiabatic Logic Circuits." ISRN Electronics 2013 (February 10, 2013): 1–12. http://dx.doi.org/10.1155/2013/673601.
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The manufacturing advances in semiconductor processing (continually reducing minimum feature size of transistors, increased complexity and ever increasing number of devices on a given IC) change the design challenges for circuit designers in CMOS technology. The important challenges are low power high speed computational devices. In this paper a novel low power adiabatic circuit topology is proposed. By removing the diode from the charging and discharging path, higher output amplitude is achieved and also the power dissipation of the diodes is eliminated. A mathematical expression has been developed to explain the energy dissipation in the proposed circuit. Performance of the proposed logic is analyzed and compared with CMOS and reported adiabatic logic styles. Also the layout of proposed inverter circuit has been drawn. Subsequently proposed topology-based various logic gates, combinational and sequential circuits and multiplier circuit are designed and simulated. The simulations were performed by VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In proposed inverter the energy efficiency has been improved to almost 60% up to 100 MHz in comparison to conventional CMOS circuits. The present research provides low power high speed results up to 100 MHz, and proposal has proven to be used in power aware high-performance VLSI circuitry.
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Kamde, Shilpa, Jitesh Shinde, Sanjay Badjate, and Pratik Hajare. "Comparative Analysis Domino Logic Based Techniques For VLSI Circuit." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 12, no. 8 (2014): 3803–8. http://dx.doi.org/10.24297/ijct.v12i8.2998.
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Domino logic is a CMOS-based evolution of the dynamic logic techniques  based on either PMOS or NMOS transistors. Domino logic technique is widely used in modern digital VLSI circuit. Dynamic logic is twice as fast as static CMOS logic because it uses only N fast transistors. The Dynamic (Domino) logic circuit are often favored in high performance designs because of the high speed and low area advantage.Four different dynamic circuit techniques including Basic domino logic circuit are compared in this paper for low power consumption and speed of domino logic circuits. For digital circuit simulation used BSIM(Berkeley Short Channel IGFET ) Model because it control leakage current.
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Muneesa, Sk Haleem, Jakkala Yoga Deepika, Obulam Yogendra Lakshmi Prasanna, Gummadi Sumasree, and Shaik Thaslim. "Design of Reconfigurable Logic Block Based Sequential Circuits Using Look Up Table Logics." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 15, no. 1 (2024): 195–204. http://dx.doi.org/10.61841/turcomat.v15i1.14612.
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Reconfigurable sequential circuits find applications in various digital systems, including communication networks, data processing units, embedded systems, and FPGA-based designs. Their ability to adapt and reconfigure their functionality onthe-fly allows them to accommodate dynamic requirements and optimize the use of hardware resources. Traditional implementations of sequential circuits involve static configurations, where the logic and functionality are fixed during synthesis. While these methods are straightforward to design and implement, they lack adaptability and cannot be modified without redesigning the entire circuit. The proposed method involves the utilization of a dedicated Reconfigurable Logic Block (RLB) within the sequential circuits, allowing for dynamic configuration changes without altering the overall circuit structure. The RLB can be programmed to provide different logic functions using look up tables, multiplexers, enabling the sequential circuit such as counters and shift registers to change its behaviour.
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Sun, Junwei, Qinfei Yang, and Yanfeng Wang. "Memristive Circuit Design of Five-Person Voter Based on Memristor Ratioed Logic." Journal of Nanoelectronics and Optoelectronics 15, no. 12 (2020): 1482–93. http://dx.doi.org/10.1166/jno.2020.2895.
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Conventional CMOS-based logic circuits are approaching their limits when it comes to speed and energy consumption, so the development of new electronic components becomes critical. Memristor is a nano-structured special electronic device with the advantages of simple structure, low power consumption and easy integration. This invention supplys a new method for developing complex logic circuits. This article mainly presents the design of a five-person voter circuit. The OR/AND logic can be accomplished by varying the polarity of two parallel memristors. On the basis of the two logic circuits, adder and comparator are constructed. Further, based on the adder and comparator, a five-person voter is implemented. The correctness and rationality of the five-person voter based on MRL are confirmed via logistical analysis and simulation. Compared with the traditional logic circuits, the logic circuit designed in this paper has advantages in area cost. The realization of the five-person voter circuit further proves that the logic circuit based on memristor can be cascaded. The research results are expected to build more complex circuits, which may provide a reference for the design of other practical circuits.
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Raman, Karthik, and Andreas Wagner. "The evolvability of programmable hardware." Journal of The Royal Society Interface 8, no. 55 (2010): 269–81. http://dx.doi.org/10.1098/rsif.2010.0212.
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In biological systems, individual phenotypes are typically adopted by multiple genotypes. Examples include protein structure phenotypes, where each structure can be adopted by a myriad individual amino acid sequence genotypes. These genotypes form vast connected ‘neutral networks’ in genotype space. The size of such neutral networks endows biological systems not only with robustness to genetic change, but also with the ability to evolve a vast number of novel phenotypes that occur near any one neutral network. Whether technological systems can be designed to have similar properties is poorly understood. Here we ask this question for a class of programmable electronic circuits that compute digital logic functions. The functional flexibility of such circuits is important in many applications, including applications of evolutionary principles to circuit design. The functions they compute are at the heart of all digital computation. We explore a vast space of 10 45 logic circuits (‘genotypes’) and 10 19 logic functions (‘phenotypes’). We demonstrate that circuits that compute the same logic function are connected in large neutral networks that span circuit space. Their robustness or fault-tolerance varies very widely. The vicinity of each neutral network contains circuits with a broad range of novel functions. Two circuits computing different functions can usually be converted into one another via few changes in their architecture. These observations show that properties important for the evolvability of biological systems exist in a commercially important class of electronic circuitry. They also point to generic ways to generate fault-tolerant, adaptable and evolvable electronic circuitry.
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Sun, Jun-Wei, Yu-Qi Tian, and Yan-Feng Wang. "Eight-Person Voter Implementation Based on Hewlett-Packard Memristor." Journal of Nanoelectronics and Optoelectronics 15, no. 3 (2020): 404–14. http://dx.doi.org/10.1166/jno.2020.2728.
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The logic function based on memristor has been proved and can be applied to the future large scale integrated circuits. In this paper, we use logic circuit based on memristor to realize the function of eight-person voter. The basic logic circuit designed in this paper is consisted of two Hewlett-Packard memristors in series connection and an operational amplifier. Operational amplifiers are used to regulate the output voltages to meet the requirements of the input signals in the next stage circuits. The adder, binary comparator and multi-input logic gate are realized by using the designed logic circuit. Full adders, binary comparators and multi-input logic gates are combined into eight-person voter circuit. Theoretical analysis and spice simulation results verify the feasibility of the circuit under different cases. This method is expected to be applied to more complex voter logic circuits based on memristor.
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Zhang, Shizhe. "Research on the Function and Application of Some Classical Combinational Logic Products." Highlights in Science, Engineering and Technology 46 (April 25, 2023): 28–35. http://dx.doi.org/10.54097/hset.v46i.7660.
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Digital signals are discrete and discontinuous signals both in time and quantity. The circuits used for digital signal processing are digital circuits. Digital electronics came into being. It is a fully developed technology, through the construction and use of specific digital circuits to achieve the logical operation of digital quantities and required logical functions. Therefore, the basic characteristic of digital circuit system is logical operation and logical processing function. The main applications of digital electronic technology are combinational logic circuit, sequential logic circuit, pulse waveform generation and shaping, digital and analog conversion circuit, etc. Here only describes the practical application products of combinatorial logic circuit and sequential logic circuit, namely decoder and counter.
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Sasipriya, P., and V. S. Kanchana Bhaaskaran. "Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL)." Journal of Circuits, Systems and Computers 27, no. 04 (2017): 1850052. http://dx.doi.org/10.1142/s0218126618500524.
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This paper presents the quasi-adiabatic logic for low power powered by two phase sinusoidal clock signal. The proposed logic called two phase adiabatic dynamic logic (2PADL) realizes the advantages of energy efficiency through the use of gate overdrive and reduced switching power. It has a single rail output and the proposed logic does not require the complementary input signals for any of its variables. The 2PADL logic is operated by two complementary clock signals acting as power supply. The validation of the proposed logic is carried out through practical circuits such as (i) sequential circuits using energy recovery technique suitable for memory circuits, (ii) an adiabatic carry look ahead adder (CLA) designed using 2PADL to study the speed performance and to prove its energy efficiency across a range of frequencies and (iii) a multiplier circuit using 2PADL compared against CMOS counterpart. The CLA adder is also implemented using the other static adiabatic logics, namely, quasi static energy recovery logic (QSERL), clocked CMOS adiabatic logic (CCAL) and conventional static CMOS logic to compare against 2PADL and validate its power advantages. The performance of the CCAL logic is tested for higher frequencies by implementing the widely presented CLA circuit. The result proves that the design is energy efficient and operates up to the frequency of 600 MHz. The simulation was carried out using industry standard Cadence® Virtuoso tool using 180[Formula: see text]nm technology library files.
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Islam, Riazul, and Satyendra N. Biswas. "A New Model of Dynamic Logic Circuit with NMOS based Keeper." Acta Universitatis Sapientiae, Electrical and Mechanical Engineering 12, no. 1 (2020): 1–14. http://dx.doi.org/10.2478/auseme-2020-0001.
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Abstract Dynamic logic circuits are widely popular due to a smaller number of transistors and consume less area. But the time to switch between logics is higher due to higher contention value. A new model of the logic using nMOS based keeper circuit is proposed and the performance is evaluated using Cadence tools. Comparative results demonstrate the suitability and competency of the proposed circuit.
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Zare, Mahdi, Hossein Manouchehrpour, and Ahmad Esmaeilkhah. "An efficient high speed, high frequency domino-logic based circuit." International Journal of Engineering & Technology 7, no. 2 (2018): 252. http://dx.doi.org/10.14419/ijet.v7i2.8219.
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As the Very Large-Scale Integration (VLSI) techniques are mostly focused on high-speed and low power consumption circuits, various techniques and technologies were investigated to gain these two precious goals. Domino-logic is one of the circuits which is regarded to have high speed, high frequency and low power consumption. This work proposes a Domini logic circuit which has improved PDP compare to the previous one. The suggested circuit was simulated and the attained results show a considerable improvement in circuit’s speed in respect with its ancestor. The PDP of the circuit in 90 nm, biased at 1V, has been calculated as 53% approximately improvement. This improvement for PDP in 65 nm, 45 nm and 32 nm are 48%, 47% and 51% respectively.
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JAHANIRAD, HADI, and KARIM MOHAMMADI. "SEQUENTIAL LOGIC CIRCUITS RELIABILITY ANALYSIS." Journal of Circuits, Systems and Computers 21, no. 05 (2012): 1250040. http://dx.doi.org/10.1142/s0218126612500405.
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Reliability analysis using error probabilities for combinational logic circuits has been investigated widely in the literature. Reliability analysis for sequential logic circuits using these methods would be inaccurate because of existence of loops in their architecture. In this paper a new method based on conversion of sequential circuit to combinational one and applying an iterative reliability analysis is developed. A Monte Carlo method-based reliability analysis is introduced for sequential circuits, which is used for first method validation. Experimental results demonstrate good accuracy of the method.
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Huang, Mingqiang, Xingli Wang, Guangchao Zhao, Philippe Coquet, and Bengkang Tay. "Design and Implementation of Ternary Logic Integrated Circuits by Using Novel Two-Dimensional Materials." Applied Sciences 9, no. 20 (2019): 4212. http://dx.doi.org/10.3390/app9204212.
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With the approaching end of Moore’s Law (that the number of transistors in a dense integrated circuit doubles every two years), the logic data density in modern binary digital integrated circuits can hardly be further improved due to the physical limitation. In this aspect, ternary logic (0, 1, 2) is a promising substitute to binary (0, 1) because of its higher number of logic states. In this work, we carry out a systematical study on the emerging two-dimensional (2D) materials (MoS2 and Black Phosphorus)-based ternary logic from individual ternary logic devices to large scale ternary integrated circuits. Various ternary logic devices, including the standard ternary inverter (STI), negative ternary inverter (NTI), positive ternary inverter (PTI) and especially the ternary decrement cycling inverter (DCI), have been successfully implemented using the 2D materials. Then, by taking advantage of the optimized ternary adder algorithm and the novel ternary cycling inverter, we design a novel ternary ripple-carry adder with great circuitry simplicity. Our design shows about a 50% reduction in the required number of transistors compared to the existing ternary technology. This work paves a new way for the ternary integrated circuits design, and shows potential to fulfill higher logic data density and a smaller chip area in the future.
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Galupa, Nicolae. "Logic Circuits Timing Analysis Using Timed Logic Variables." European Scientific Journal, ESJ 12, no. 18 (2016): 35. http://dx.doi.org/10.19044/esj.2016.v12n18p35.
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Combinational logic circuit timing analysis is an important issue that all designers need to address. The present paper presents a simple and compact analysis procedure. We follow the guidelines drawn by previous methods, but we shall define new time-dependent logic variables that help us improve their efficiency. By using the methodology suggested, we shall replace a very laborious technique (pure delay circuit + time constants method) with a simpler procedure that can pinpoint the specific conditions for a logic circuit’s anomalous behaviour within a few simple steps. Considering the logic function implemented the methodology presented will require analysis of only a limited number of situations/combinations to determine the presence of an anomalous behaviour. When anomalous behaviour is identified, the methodology provides a clear timing description.
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KIM, JEONG BEOM. "CURRENT MODE CMOS QUATERNARY LOGIC FULL-ADDER." Journal of Circuits, Systems and Computers 18, no. 01 (2009): 199–208. http://dx.doi.org/10.1142/s0218126609005022.
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This paper proposes a quaternary-to-binary logic decoder, a quaternary current buffer, and a quaternary full-adder using current-mode multiple-valued logic (MVL) CMOS circuits. The proposed full-adder is superior to the previous MVL CMOS circuit in both the circuit occupied area and the performance. Comparing with the binary logic full-adder, the proposed full-adder is superior in the circuit occupied area. However, the circuit performance is inferior to the binary logic full-adder. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.25 μm standard CMOS technology with the supply voltage 2.5 V.
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Fan, Fuyou, Guowu Yang, Gang Yang, and William N. N. Hung. "A Synthesis Method of Quantum Reversible Logic Circuit Based on Elementary Qutrit Quantum Logic Gates." Journal of Circuits, Systems and Computers 24, no. 08 (2015): 1550121. http://dx.doi.org/10.1142/s0218126615501212.
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Because ternary computer has more superiority than other d-ary number systems, we focus on the investigation of ternary elementary quantum gates and the synthesis algorithm of ternary quantum logic circuits. Above all, Pauli operators and their matrices on qutrit are introduced. Then eight qutrit operators are selected as elementary operators and eight qutrit quantum logic gates are defined. Permutation groups are introduced to characterize the quantum gates and quantum logic circuits. Some important qutrit quantum logic gates are defined also, such as QNOT, QKCXi, EQKCXi, QSwap, QCNOT and EQCNOT. Based on these elementary gates, we prove two very important theorems: (1) all qutrit quantum reversible logic circuit can be generated by Xi gate and QKCXi gate; (2) all qutrit quantum reversible logic circuits can be generated by Xi gate and QCNOT gate. The two theorems indicate that any complicated qutrit quantum reversible circuit can be constructed by the simplest ternary quantum gate. This will greatly simplify the implementation difficulty of quantum circuit. Subsequently, we propose a synthesis algorithm for qutrit quantum reversible logic circuit, which is verified through simulation experiment by the computer program we have designed.
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Wang, Xiaoyuan, Xinrui Zhang, Chuantao Dong, Shimul Kanti Nath, and Herbert Ho-Ching Iu. "Design and Application of Memristive Balanced Ternary Univariate Logic Circuit." Micromachines 14, no. 10 (2023): 1895. http://dx.doi.org/10.3390/mi14101895.
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This paper proposes a unique memristor-based design scheme for a balanced ternary digital logic circuit. First, a design method of a single-variable logic function circuit is proposed. Then, by combining with a balanced ternary multiplexer, some common application-type combinational logic circuits are proposed, including a balanced ternary half adder, multiplier and numerical comparator. The above circuits are all simulated and verified in LTSpice, which demonstrate the feasibility of the proposed scheme.
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ZHao, Hong-Quan, and Seiya Kasai. "WPG-Controlled Quantum BDD Circuits with BDD Architecture on GaAs-Based Hexagonal Nanowire Network Structure." Journal of Nanomaterials 2012 (2012): 1–6. http://dx.doi.org/10.1155/2012/726860.
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One-dimensional nanowire quantum devices and basic quantum logic AND and OR unit on hexagonal nanowire units controlled by wrap gate (WPG) were designed and fabricated on GaAs-based one-dimensional electron gas (1-DEG) regular nanowire network with hexagonal topology. These basic quantum logic units worked correctly at 35 K, and clear quantum conductance was achieved on the node device, logic AND circuit unit, and logic OR circuit unit. Binary-decision-diagram- (BDD-) based arithmetic logic unit (ALU) is realized on GaAs-based regular nanowire network with hexagonal topology by the same fabrication method as that of the quantum devices and basic circuits. This BDD-based ALU circuit worked correctly at room temperature. Since these quantum devices and circuits are basic units of the BDD ALU combinational circuit, the possibility of integrating these quantum devices and basic quantum circuits into the BDD-based quantum circuit with more complicated structures was discussed. We are prospecting the realization of quantum BDD combinational circuitries with very small of energy consumption and very high density of integration.
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Khitun, Alexander, Mingqiang Bao, and Kang L. Wang. "Magnonic logic circuits." Journal of Physics D: Applied Physics 43, no. 26 (2010): 264005. http://dx.doi.org/10.1088/0022-3727/43/26/264005.
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Zhan, Wei, and Richard M. Crooks. "Microelectrochemical Logic Circuits." Journal of the American Chemical Society 125, no. 33 (2003): 9934–35. http://dx.doi.org/10.1021/ja0366585.
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Hasuo, S., and T. Imamura. "Digital logic circuits." Proceedings of the IEEE 77, no. 8 (1989): 1177–93. http://dx.doi.org/10.1109/5.34118.
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Nilsson, D., N. Robinson, M. Berggren, and R. Forchheimer. "Electrochemical Logic Circuits." Advanced Materials 17, no. 3 (2005): 353–58. http://dx.doi.org/10.1002/adma.200401273.
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Balzani, Vincenzo, Alberto Credi, and Margherita Venturi. "Molecular Logic Circuits." ChemPhysChem 4, no. 1 (2002): 49–59. http://dx.doi.org/10.1002/cphc.200390007.
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Tiwari, Ayush. "Leakage Power Reduction in CMOS VLSI Circuits using Advance Leakage Reduction Method." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (2021): 962–66. http://dx.doi.org/10.22214/ijraset.2021.35065.
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Recently, consumption of power is key problem of logic circuits based on Very Large Scale Integration. More potentiality consumption isn’t considered an appropriate for storage cell life for the use in cell operations and changes parameters such as optimality, efficiency etc, more consumption of power also provides for minimization of cell storage cycle. In present scenario static consumption of power is major troubles in logic circuits based on CMOS. Layout of drainage less circuit is typically complex. Several derived methods for minimization of consumption of potentiality for logic circuits based on CMOS. For this research paper, a technique called Advance Leakage reduction (AL reduction) is proposed to reduce the leakage power in CMOS logic circuits. To draw our structure circuit related to CMOS like Inverter, inverted AND, and NOR etc. we have seen the power and delay for circuits. This paper incorporates, analyzing of several minimization techniques as compared with proposed work to illustrate minimization in ratio of energy and time usage and time duration for propagation. LECTOR, Source biasing, Stack ONOFIC method is observed and analyzed with the proposed method to evaluate the leakage power consumption and propagation delay for logic circuits based on CMOS. Entire work has done in LT Spice Software with 180nm library of CMOS.
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Wang, Lu, Hongyu Zhu, Ze Zuo, and Dianzhong Wen. "Full-function logic circuit based on egg albumen resistive memory." Applied Physics Letters 121, no. 24 (2022): 243505. http://dx.doi.org/10.1063/5.0124826.
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The logic gate is the basic unit of a digital circuit structure. The operation, memory, I/O, and other reading and writing functions of computer systems require logic circuits. Logic gates based on resistive memory can make existing integrated circuits denser, smaller, faster, and use fewer devices. In this paper, Al/polymethyl methacrylate (PMMA)/egg albumen (EA):Au nanoparticles/PMMA/Al multilayer biological resistive random access memory was prepared based on the natural biological material—egg albumen (EA). The device has bipolar switching behavior, a higher switching current ratio, a lower threshold voltage, and better stability. A circuit based on auxiliary logic is constructed using this device, and the logic functions of AND, OR, NOT, NAND, and NOR are realized. This device provides an effective potential solution for implementing high-performance electronic devices and large-scale integrated circuits.
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Kumaresan, Raja Sekar, Marshal Raj, and Lakshminarayanan Gopalakrishnan. "Design and implementation of a nano magnetic logic barrel shifter using beyond-CMOS technology." Journal of Electrical Engineering 73, no. 1 (2022): 1–10. http://dx.doi.org/10.2478/jee-2022-0001.
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Abstract Bit manipulation plays a significant role in high-speed digital signal processing (DSP) and data computing systems, and shift and rotation operations are crucial functions in it. In general, barrel shifters are used to perform these operations effectively. Nano magnetic logic circuits are among the promising beyond-CMOS alternative technologies for the design of high-speed circuits. Most of the existing circuits that have been developed using nano magnets are combinational circuits. In this work, a barrel shifter is implemented and realised using in-plane nano magnetic logic. The proposed design is the first of its kind nano magnetic logic circuit. The nano magnetic logic circuit implementation, layout generation, simulation, and validation were performed using the ToPoliNano and ModelSim tools. The logical equivalent design was synthesised and evaluated using the Synopsys Design Compiler tool. The proposed barrel shifter was realised using majority logic has 1769037 nano magnets with a boxing area of 481 × 13104 µm2 and 3276 clock zones after optimisation with the Barycenter algorithm. The proposed barrel shifter realised using Boolean logic has 315276 nano magnets with a boxing area of 265 × 5028 µm2 and 1257 clock zones after optimisation with the Barycenter algorithm. The proposed design results demonstrate that complex systems can be developed using nano magnetic logic by combining combinational and sequential circuits.
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Li, Haiwei, Maoqun Yao, Conghui Li, and Shanhu Shen. "A power constant logic circuit based on mask control." Journal of Physics: Conference Series 2645, no. 1 (2023): 012010. http://dx.doi.org/10.1088/1742-6596/2645/1/012010.
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Abstract As the structure of existing anti-power attack circuits has certain security problems, this paper proposes a new mask-based control constant power logic circuit based on the existing masking technology. By integrating OR/NOR and AND/NAND circuits into a dual-rail circuit, different circuit logic functions can be controlled by inputting different masks. By introducing two parameters, Normalised Energy Deviation (NED) and Normalised Standard Deviation (NSD), the structure proposed in this paper improves the level of resistance of the circuit to power attacks to a certain extent, as well as reduces the cost of the circuit compared to other power attack resistant circuits.
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Dawar, Anuj, and Gregory Wilsenach. "Symmetric Circuits for Rank Logic." ACM Transactions on Computational Logic 23, no. 1 (2022): 1–35. http://dx.doi.org/10.1145/3476227.
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Fixed-point logic with rank (FPR) is an extension of fixed-point logic with counting (FPC) with operators for computing the rank of a matrix over a finit field. The expressive power of FPR properly extends that of FPC and is contained in P, but it is not known if that containment is proper. We give a circuit characterization for FPR in terms of families of symmetric circuits with rank gates, along the lines of that for FPC given by Anderson and Dawar in 2017. This requires the development of a broad framework of circuits in which the individual gates compute functions that are not symmetric (i.e., invariant under all permutations of their inputs). This framework also necessitates the development of novel techniques to prove the equivalence of circuits and logic. Both the framework and the techniques are of greater generality than the main result.
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Morell, William, and Jin-Woo Choi. "Design and Analysis of Self-Tanked Stepwise Charging Circuit for Four-Phase Adiabatic Logic." Journal of Low Power Electronics and Applications 14, no. 3 (2024): 34. http://dx.doi.org/10.3390/jlpea14030034.
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Adiabatic logic has been proposed as a method for drastically reducing power consumption in specialized low-power circuits. They often require specialized clock drivers that also function as the main power supply, in contrast to standard CMOS logic, and these power clocks are often a point of difficulty in the design process. A novel, stepwise charging driver circuit for four-phase adiabatic logic is proposed and validated through a simulation study. The proposed circuit consists of two identical driver circuits each driving two opposite adiabatic logic phases. Its performance relative to ideal step-charging and a standard CMOS across mismatched phase loads is analyzed, and new best practices are established. It is compared to a reference circuit consisting of one driver circuit for each phase along with a paired on-chip tank capacitor. The proposed driver uses opposite logic phases to act as the tank capacitor for each other in a “self-tanked” fashion. Each circuit was simulated in 15 nm FinFET across a variety of frequencies for an arbitrary logic operation. Both circuits showed comparable power consumption at all frequencies tested, yet the proposed driver uses fewer transistors and control signals and eliminates the explicit tank capacitors entirely, vastly reducing circuit area, complexity, and development time.
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Wille, Robert, and Rolf Drechsler. "BDD-Based Synthesis of Reversible Logic." International Journal of Applied Metaheuristic Computing 1, no. 4 (2010): 25–41. http://dx.doi.org/10.4018/jamc.2010100102.
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Reversible logic became a promising alternative to traditional circuits because of its applications in emerging technologies such as quantum computing, low-power design, DNA computing, or nanotechnologies. As a result, synthesis of the respective circuits is an intensely studied topic. However, most synthesis methods are limited, because they rely on a truth table representation of the function to be synthesized. In this paper, the authors present a synthesis approach that is based on Binary Decision Diagrams (BDDs). The authors propose a technique to derive reversible or quantum circuits from BDDs by substituting all nodes of the BDD with a cascade of Toffoli or quantum gates, respectively. Boolean functions containing more than a hundred of variables can efficiently be synthesized. More precisely, a circuit can be obtained from a given BDD using an algorithm with linear worst case behavior regarding run-time and space requirements. Furthermore, using the proposed approach, theoretical results known from BDDs can be transferred to reversible circuits. Experiments show better results (with respect to the circuit cost) and a significantly better scalability in comparison to previous synthesis approaches.
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Al-Rabadi, Anas. "Three-dimensional lattice logic circuits, Part I: Fundamentals." Facta universitatis - series: Electronics and Energetics 18, no. 1 (2005): 1–13. http://dx.doi.org/10.2298/fuee0501001a.
Full textAbstract:
Fundamentals of regular three-dimensional (3D) lattice circuits are introduced. Lattice circuits represent an important class of regular circuits that allow for local interconnections, predictable timing, fault localization, and self-repair. In addition, three-dimensional lattice circuits can be potentially well suited for future 3D technologies, such as nanotechnologies, where the intrinsic physical delay of the irregular and lengthy interconnections limits the device performance. Although the current technology does not offer a menu for the immediate physical implementation of the proposed three-dimensional circuits, this paper deals with three-dimensional logic circuit design from a fundamental and foundational level for a rather new possible future directions in designing digital logic circuits.
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Yang, Fengjie, Yuan Liu, Bin Wang, Changjun Zhou, and Qiang Zhang. "Constructing Controllable Logic Circuits Based on DNAzyme Activity." Molecules 24, no. 22 (2019): 4134. http://dx.doi.org/10.3390/molecules24224134.
Full textAbstract:
Recently, DNA molecules have been widely used to construct advanced logic devices due to their unique properties, such as a simple structure and predictable behavior. In fact, there are still many challenges in the process of building logic circuits. Among them, the scalability of the logic circuit and the elimination of the crosstalk of the cascade circuit have become the focus of research. Inspired by biological allosteric regulation, we developed a controllable molecular logic circuit strategy based on the activity of DNAzyme. The E6 DNAzyme sequence was temporarily blocked by hairpin DNA and activated under appropriate input trigger conditions. Using a substrate with ribonucleobase (rA) modification as the detection strand, a series of binary basic logic gates (YES, AND, and INHIBIT) were implemented on the computational component platform. At the same time, we demonstrate a parallel demultiplexer and two multi-level cascade circuits (YES-YES and YES-Three input AND (YES-TAND)). In addition, the leakage of the cascade process was reduced by exploring factors such as concentration and DNA structure. The proposed DNAzyme activity regulation strategy provides great potential for the expansion of logic circuits in the future.
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Duncan, Philip N., Siavash Ahrar, and Elliot E. Hui. "Scaling of pneumatic digital logic circuits." Lab on a Chip 15, no. 5 (2015): 1360–65. http://dx.doi.org/10.1039/c4lc01048e.
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We present strategies for scaling pneumatic logic circuits to smaller dimensions. Our process achieves order-of-magnitude increases in both circuit density and speed, enabling the construction of a 12-bit counter.
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Jiang, Jin Tao, Li Fang Ye, and Jian Ping Hu. "Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration." Applied Mechanics and Materials 39 (November 2010): 73–78. http://dx.doi.org/10.4028/www.scientific.net/amm.39.73.
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Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with gate oxide materials. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the PAL-2P scheme. All circuits are simulated with HSPICE using the 65nm CMOS process with gate oxide materials. Based on the power dissipation models of PAL-2P adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. The PAL-2P circuits consume low static power compared with traditional PAL-2N ones.
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Gyawali, Yadu Prasad, and Mohit Angurala. "Design of Frequency Divider (FD/2 and FD 2/3) Circuits for a Phase Locked Loop." International Journal on Future Revolution in Computer Science & Communication Engineering 8, no. 1 (2022): 27–31. http://dx.doi.org/10.17762/ijfrcsce.v8i1.2103.
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This paper reports on three design of Frequency Divider (FD/2) and Frequency Divider (FD 2/3) circuits. Tanner EDA tool developed on 130nm CMOS technology with a voltage supply of 1.3 V is used to build, model, and compare all circuits. For the FD/2 circuit, E-TSPC Pass Transistor logic uses 1.77 µW, whereas TSPC logic consumes 5.57 µW for the FD 2/3 circuit. It implies that the TSPC logic is the best solution since it meets the speed and power consumption requirements.
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Panda, Rajendran, and Farid N. Najm. "Post-Mapping Transformations for Low-Power Synthesis." VLSI Design 7, no. 3 (1998): 289–301. http://dx.doi.org/10.1155/1998/96768.
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We propose a logic synthesis system that includes power optimization after technology mapping. Our approach is unique in that our post-mapping logic transformations take into account information on circuit delay, capacitance, arrival times, glitches, etc., to provide much better accuracy than previously proposed technology-independent power optimization methods. By changing connections in a mapped circuit, we achieve power improvements up to 13% in case of area- or delay-optimized circuits, with reductions also in area and delay. We show that by applying the proposed technique on circuits that are already restructured for lower switching activity using the technique presented in [11], total power savings up to 59% in case of area-optimized circuits and 38% in case of delay-optimized circuits are achievable. The post-mapping transformations are based on the transition density model of circuit switching activity and the concept of permissible logic functions. The techniques presented here are applicable equally well to both synchronous and asynchronous circuits. The power measurements are done under a general delay model.
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Fadaei, Mohammadreza. "Designing ALU using GDI method." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 3 (2019): 151. http://dx.doi.org/10.11591/ijres.v8.i3.pp151-161.
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<p>As CMOS technology is continuously becoming smaller and smaller in nanoscale regimes, and circuit resistance to changes in the process for the design of the circuit is a major obstacle. Storage elements such as memory and flip-flops are particularly vulnerable to the change process. Power consumption is also another challenge in today's Digital IC Design. In modern processors, there are a large number of transistors, more than a billion transistors, which increases the temperature and the breakdown of its performance. Therefore, circuit design with low power consumption is a critical need for integrated circuits today. In this study, we deal with GDI techniques for designing logic and arithmetic circuits. We show that this logic in addition to low power consumption has little complexity so that arithmetic and logic circuits can be implemented with fewer transistors. Various circuits such as adders, differentiation and multiplexers, etc. have been designed and implemented using these techniques, and published in various articles. In this study, we review and evaluate the advantages and disadvantages of these circuits.</p>
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Hossain, M., M. P. Singh, and J. K. Rakshit. "Modelling of one-bit Arithmetic Logic Circuit using silicon micro-ring resonator." Journal of Physics: Conference Series 2335, no. 1 (2022): 012003. http://dx.doi.org/10.1088/1742-6596/2335/1/012003.
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Abstract All-optical technology overcomes the problems that arise in traditional digital circuits such as speed limitation, energy consumption and size. In this manuscript, we have implemented a one-bit arithmetic logic circuit employing all-optical silicon micro-ring resonator that utilizes the advantages over other all-optical techniques. The Arithmetic logic circuit is the core component of ultra-fast combinational circuits. The proposed arithmetic logic circuit is validated through MATLAB at about 260 Gbps. Performance of our design has been investigated by numerical simulation. The critical parameters of MRR are optimized on the basis of performance metrics.
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Hoiriyah, Hoiriyah. "SIMULASI GERBANG DASAR LOGIKA DALAM APLIKASI." Jurnal Teknik Informatika dan Elektro 2, no. 2 (2022): 01–08. http://dx.doi.org/10.55542/jurtie.v2i2.405.
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It is no longer a secret that all science is currently developing and has technological advances that cannot be denied, especially in digital technology which is currently popular, one of which is a digital electronic system that is composed of logic gates so that it becomes a digital system formed from logic elements. the smallest is the logic gate (Logic Gate): OR, AND and NOT where the circuit work process on this logic gate uses Boolean algebra principles. In its implementation it is rather difficult to provide an understanding of logic gates manually or in theory to the public and the general public in understanding gate circuits electronics to understand the functions and uses of logic gates in electronic circuits with EWB (Electronic WorkBanch) as an electronic computer software that can be used to simulate the workings of an electronic circuit, both analog and digital. The EWB application is very helpful in providing an indirect understanding of understanding basic logic gate circuits as simulations in applications to reduce possible dangerous risks, with this application it makes it easy to know the conditions you want to design and create before implementing them in real form..
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Seo, Jinyoung, Sungi Kim, Ha H. Park, Da Yeon Choi, and Jwa-Min Nam. "Nano-bio-computing lipid nanotablet." Science Advances 5, no. 2 (2019): eaau2124. http://dx.doi.org/10.1126/sciadv.aau2124.
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Using nanoparticles as substrates for computation enables algorithmic and autonomous controls of their unique and beneficial properties. However, scalable architecture for nanoparticle-based computing systems is lacking. Here, we report a platform for constructing nanoparticle logic gates and circuits at the single-particle level on a supported lipid bilayer. Our “lipid nanotablet” platform, inspired by cellular membranes that are exploited to compartmentalize and control signaling networks, uses a lipid bilayer as a chemical circuit board and nanoparticles as computational units. On a lipid nanotablet, a single-nanoparticle logic gate senses molecules in solution as inputs and triggers particle assembly or disassembly as an output. We demonstrate a set of Boolean logic operations, fan-in/fan-out of logic gates, and a combinational logic circuit such as a multiplexer. We envisage that our approach to modularly implement nanoparticle circuits on a lipid bilayer will create new paradigms and opportunities in molecular computing, nanoparticle circuits, and systems nanoscience.
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Amgoth Laxman, Et al. "Design and Implementation of Hybrid Multiplier for DSP Applications." International Journal on Recent and Innovation Trends in Computing and Communication 11, no. 10 (2023): 623–28. http://dx.doi.org/10.17762/ijritcc.v11i10.8556.
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In recent decades, there has been a consistent reduction in feature sizes in integrated circuit (IC) technology, leading to the need for increased placement of functional circuits on each chip. When it comes to the design of digital circuits, there is a significant focus on hybrid logic. Hybrid logic is highly regarded due to its ability to consume less power while achieving higher efficiency. Hybrid logic circuits have similarities to complementary metal-oxide-semiconductor (CMOS) transistors, yet possess a reduced transistor count while offering enhanced performance and reliability capabilities. This study examines the modeling and implementation hybrid multiplier with of help of hybrid adder. The functionality of adder is determined with the help of hybrid logic producing XOR/XNOR functionalities in single circuit. The proposed hybrid Multiplier, which incorporates a hybrid Adder, has been successfully designed and implemented using CMOS 45nm technology and Mentor Graphics software the hybrid transistor logic multiplier demonstrates a decrease in total delay of 60% compared to CMOS.
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Lin, Shan, Tao Lin, and Zhan Wen Liu. "A Discussion of the Design Method of Full Adder Circuit." Applied Mechanics and Materials 135-136 (October 2011): 15–20. http://dx.doi.org/10.4028/www.scientific.net/amm.135-136.15.
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A bit full adder is a very important component in the digital system. Design of a full-adder circuit, as an example, by changing its output function expression in the form of expression, use the gates, decoder, multiplexer etc 74 series devices, the eight circuits realization form are given respectively, and briefly analyzed the advantages and disadvantages of the various circuit implementation. The example show that the design of combinational logic circuits has mobility and variety, it could give the instructiveness and the guiding for other design of combinational logic circuits.
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Bernstein, Kerry. "Circuit Responses to Radiation-Induced Upsets." MRS Bulletin 28, no. 2 (2003): 126–30. http://dx.doi.org/10.1557/mrs2003.40.
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AbstractHistorically, radiation-induced corruption of data in high-speed complementary metal oxide semiconductor designs has been limited to on-board static random-access memory in various memory caches. Successive generations of scaling, however, have resulted in capacitance reductions in key logic circuits, increasing their vulnerability to these “soft errors.” Charge delivered by radiation events now carries a substantial probability of inducing upsets, not only in bistable elements, but in logic evaluation circuits as well. This article introduces the reader to common logic-circuit topologies in high-speed microprocessors, radiation circuit response mechanisms that can compromise logic evaluation integrity, and existing techniques that mitigate this exposure.
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PARK, DONGKYU, SEOKSOO YOON, INHWA JUNG, and CHULWOO KIM. "NOISE-AWARE SPLIT-PATH DOMINO LOGIC AND ITS CLOCK DELAYING SCHEME." Journal of Circuits, Systems and Computers 16, no. 01 (2007): 139–54. http://dx.doi.org/10.1142/s0218126607003563.
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This paper describes an improved domino logic using split-path (SP) and revised clock-delaying (CD) scheme. SP domino logic is a high-speed operation because it ameliorates the charge-sharing problem by splitting the stacked NMOS transistors used for logic evaluation. Additionally, SP domino logic removes the use of signal ordering. Dual threshold voltage (Vt) assignment methodology for the SP domino logic circuit is also proposed in order to provide the improved performance with low power-consumption overhead. Our experimental results of SP domino logic circuit show that the proposed logic provides the performance improvement up to 15% compared to the conventional domino logic circuit, under the same noise conditions. For further performance enhancement of the domino logic, CD methodology is applied. Moreover, an optimized delay cell is proposed to reduce the clock-delay overhead required to compensate the process, voltage, and temperature (PVT) variations. 32-b Han–Carlson prefix adders using the proposed CD SP domino logic circuits and the conventional CD domino logic circuits were designed to verify the performance enhancement of the proposed circuit. Simulation results show that the total delay of the 32-b adder using the proposed circuit is 454 ps of 5.47FO4 in a 0.18-μm CMOS process.
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Upadhyaya, Devanshi, Maël Gay, and Ilia Polian. "Locking-Enabled Security Analysis of Cryptographic Circuits." Cryptography 8, no. 1 (2024): 2. http://dx.doi.org/10.3390/cryptography8010002.
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Hardware implementations of cryptographic primitives require protection against physical attacks and supply chain threats. This raises the question of secure composability of different attack countermeasures, i.e., whether protecting a circuit against one threat can make it more vulnerable against a different threat. In this article, we study the consequences of applying logic locking, a popular design-for-trust solution against intellectual property piracy and overproduction, to cryptographic circuits. We show that the ability to unlock the circuit incorrectly gives the adversary new powerful attack options. We introduce LEDFA (locking-enabled differential fault analysis) and demonstrate for several ciphers and families of locking schemes that fault attacks become possible (or consistently easier) for incorrectly unlocked circuits. In several cases, logic locking has made circuit implementations prone to classical algebraic attacks with no fault injection needed altogether. We refer to this “zero-fault” version of LEDFA by the term LEDA, investigate its success factors in-depth and propose a countermeasure to protect the logic-locked implementations against LEDA. We also perform test vector leakage assessment (TVLA) of incorrectly unlocked AES implementations to show the effects of logic locking regarding side-channel leakage. Our results indicate that logic locking is not safe to use in cryptographic circuits, making them less rather than more secure.
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Bhoi, Bandan Kumar. "Optimized Logic Gate Design using QCA." International Journal for Research in Applied Science and Engineering Technology 12, no. 6 (2024): 1111–13. http://dx.doi.org/10.22214/ijraset.2024.63273.
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Abstract: Quantum-dot cellular automaton (QCA) represents a burgeoning and auspicious nanoelectronic computational framework for the forthcoming generation, where binary data is encoded through the electronic charge arrangement within a cell. This architec- ture, rooted in digital logic, leverages individual electrons within arrays of quantum dots to execute binary operations. At the core of QCA circuits lies the QCA cell, serving as a fundamental unit for constructing basic gates and logic devices within QCA architectures. An assessment of diverse QCA-based XOR gate implementations is conducted in this study, alongside the proposition of novel layouts exhibiting enhanced performance metrics. The paper delves into various methodologies for designing QCA circuits, specifically focus- ing on the XOR gate. These layouts demonstrate a reduced number of crossovers and a diminished cell count in comparison to the conventional structures documented in existing literature. Notably, these design configurations hold significance for communication- centric circuit applications, particularly in activities such as phase detection within digital circuits, arithmetic computations, and error identification and rectification processes. A comparative analysis of different circuit designs is also provided, illustrating the potential of the proposed layouts in realizing more intricate circuits. The simulations in this study are executed utilizing the QCADesigner tool.
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Amirany, Abdolah, and Ramin Rajaei. "Spin-Based Fully Nonvolatile Full-Adder Circuit for Computing in Memory." SPIN 09, no. 01 (2019): 1950007. http://dx.doi.org/10.1142/s2010324719500073.
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As CMOS technology scales down toward below 2-digit nanometer dimensions, exponentially increasing leakage power, vulnerability to radiation induced soft errors have become a major problem in today’s logic circuits. Emerging spin-based logic circuits and architectures based on nonvolatile magnetic tunnel junction (MTJ) cells show a great potential to overcome the aforementioned issues. However, radiation induced soft errors are still a problem in MTJ-based circuits as they need sequential peripheral CMOS circuits for sensing the MTJs. This paper proposes a novel nonvolatile and low-cost radiation hardened magnetic full adder (MFA). In comparison with the previous designs, the proposed MFA is capable of tolerating particle strikes regardless of the amount of charge induced to a single node and even multiple nodes. Besides, the proposed MFA offers low power operation, low area and high performance as compared with previous counterparts. One of the most important features suggested by the proposed MFA circuit is full nonvolatility. Nonvolatile logic circuits remove the cost of high volume data transactions between memory and logic and also facilitate power gating in logic-in-memory architectures.